diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi index cb91161d4e6b..9c221b095208 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi @@ -34,6 +34,8 @@ opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-microvolt = <900000>; + opp-microvolt-L0 = <900000>; + opp-microvolt-L1 = <850000>; }; /delete-node/ opp-1560000000; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi index b8c78e627d94..a2356349da71 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi @@ -338,6 +338,12 @@ }; }; +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + &can0 { assigned-clocks = <&cru CLK_CAN0>; assigned-clock-rates = <150000000>; @@ -1630,6 +1636,7 @@ }; &rkvenc { + venc-supply = <&vdd_logic>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 86ff626a056e..2d7ae0b124b3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -132,16 +132,30 @@ compatible = "operating-points-v2"; opp-shared; + mbist-vmin = <825000 900000 950000>; + nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; + rockchip,pvtm-voltage-sel = < + 0 82000 0 + 82001 93000 1 + 93001 100000 2 + >; + rockchip,pvtm-freq = <408000>; + rockchip,pvtm-volt = <900000>; + rockchip,pvtm-ch = <0 5>; + rockchip,pvtm-sample-time = <1000>; + rockchip,pvtm-number = <10>; + rockchip,pvtm-error = <1000>; + rockchip,pvtm-ref-temp = <40>; + rockchip,pvtm-temp-prop = <26 26>; + rockchip,thermal-zone = "soc-thermal"; rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <0>; rockchip,low-temp-adjust-volt = < /* MHz MHz uV */ - 1104 1608 75000 + 0 1608 75000 >; - nvmem-cells = <&cpu_leakage>; - nvmem-cell-names = "leakage"; - opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <825000 825000 1150000>; @@ -1058,16 +1072,16 @@ npu_opp_table: npu-opp-table { compatible = "operating-points-v2"; + mbist-vmin = <825000 900000 950000>; + nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <0>; rockchip,low-temp-adjust-volt = < /* MHz MHz uV */ - 700 700 50000 + 0 700 50000 >; - nvmem-cells = <&npu_leakage>; - nvmem-cell-names = "leakage"; - opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-microvolt = <825000 825000 1000000>; @@ -1099,6 +1113,42 @@ opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1000000 1000000 1000000>; + status = "disabled"; + }; + }; + + bus_npu: bus-npu { + compatible = "rockchip,rk3568-bus"; + rockchip,busfreq-policy = "clkfreq"; + clocks = <&scmi_clk 2>; + clock-names = "bus"; + operating-points-v2 = <&bus_npu_opp_table>; + status = "disabled"; + }; + + bus_npu_opp_table: bus-npu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&core_pvtm>; + nvmem-cell-names = "pvtm"; + rockchip,pvtm-voltage-sel = < + 0 82000 0 + 82001 93000 1 + 93001 100000 2 + >; + rockchip,pvtm-ch = <0 5>; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <950000>; + opp-microvolt-L0 = <950000>; + opp-microvolt-L1 = <925000>; + opp-microvolt-L2 = <0>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <0>; }; }; @@ -1147,8 +1197,9 @@ gpu_opp_table: opp-table2 { compatible = "operating-points-v2"; - nvmem-cells = <&gpu_leakage>; - nvmem-cell-names = "leakage"; + mbist-vmin = <825000 900000 950000>; + nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; @@ -1364,7 +1415,7 @@ clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_RKVENC_CORE>; clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; - rockchip,normal-rates = <297000000>, <0>, <400000000>; + rockchip,normal-rates = <297000000>, <0>, <297000000>; resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>, <&cru SRST_RKVENC_CORE>; reset-names = "video_a", "video_h", "video_core"; @@ -1376,9 +1427,38 @@ rockchip,taskqueue-node = <3>; rockchip,resetgroup-node = <3>; power-domains = <&power RK3568_PD_RKVENC>; + operating-points-v2 = <&rkvenc_opp_table>; status = "disabled"; }; + rkvenc_opp_table: rkvenc-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&core_pvtm>; + nvmem-cell-names = "pvtm"; + rockchip,pvtm-voltage-sel = < + 0 82000 0 + 82001 93000 1 + 93001 100000 2 + >; + rockchip,pvtm-ch = <0 5>; + + opp-297000000 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <900000>; + opp-microvolt-L0 = <900000>; + opp-microvolt-L1 = <900000>; + opp-microvolt-L2 = <850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <950000>; + opp-microvolt-L0 = <950000>; + opp-microvolt-L1 = <900000>; + opp-microvolt-L2 = <850000>; + }; + }; + rkvenc_mmu: iommu@fdf40f00 { compatible = "rockchip,iommu-v2"; reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>; @@ -2053,33 +2133,50 @@ dmc_opp_table: dmc-opp-table { compatible = "operating-points-v2"; + mbist-vmin = <825000 900000 950000>; + nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <0>; rockchip,low-temp-adjust-volt = < /* MHz MHz uV */ - 0 1560 25000 + 0 1560 25000 + >; + rockchip,leakage-voltage-sel = < + 1 80 0 + 81 254 1 >; opp-324000000 { opp-hz = /bits/ 64 <324000000>; opp-microvolt = <900000>; + opp-microvolt-L0 = <900000>; + opp-microvolt-L1 = <850000>; }; opp-528000000 { opp-hz = /bits/ 64 <528000000>; opp-microvolt = <900000>; + opp-microvolt-L0 = <900000>; + opp-microvolt-L1 = <850000>; }; opp-780000000 { opp-hz = /bits/ 64 <780000000>; opp-microvolt = <900000>; + opp-microvolt-L0 = <900000>; + opp-microvolt-L1 = <850000>; }; opp-920000000 { opp-hz = /bits/ 64 <920000000>; opp-microvolt = <900000>; + opp-microvolt-L0 = <900000>; + opp-microvolt-L1 = <850000>; status = "disabled"; }; opp-1560000000 { opp-hz = /bits/ 64 <1560000000>; opp-microvolt = <900000>; + opp-microvolt-L0 = <900000>; + opp-microvolt-L1 = <850000>; }; }; @@ -2396,6 +2493,10 @@ reg = <0x08 0x1>; bits = <3 3>; }; + mbist_vmin: mbist-vmin@9 { + reg = <0x09 0x1>; + bits = <0 4>; + }; otp_id: id@a { reg = <0x0a 0x10>; }; @@ -2411,6 +2512,9 @@ gpu_leakage: gpu-leakage@1d { reg = <0x1d 0x1>; }; + core_pvtm:core-pvtm@2a { + reg = <0x2a 0x2>; + }; }; i2s0_8ch: i2s@fe400000 {