From 75f941d3475505cbbd1dc2df0b7f4db74468662a Mon Sep 17 00:00:00 2001
From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Wed, 11 Nov 2020 14:22:56 +0800
Subject: [PATCH] clk: rockchip: rk3568: mark npll as critical clock

npll is for dsu high freq.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I4fd3141e577ee0933d8eac07bd154c1d1b341edd
---
 drivers/clk/rockchip/clk-rk3568.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 90267d43b095..aa77ab89bf3f 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1598,6 +1598,7 @@ static const char *const rk3568_cru_critical_clocks[] __initconst = {
 	"aclk_secure_flash",
 	"hclk_secure_flash",
 	"aclk_core_niu2bus",
+	"npll",
 };
 
 static const char *const rk3568_pmucru_critical_clocks[] __initconst = {