From 7613cd2882af93a762624af0f2ad8a28fafa13fd Mon Sep 17 00:00:00 2001 From: Chuangcheng Peng Date: Mon, 12 Mar 2018 19:33:53 +0800 Subject: [PATCH] dvb:Update demux register & support gl2a board & support demod/tuner attach PD#156734 Update demux register & support gl2a board PD#163384 Support to seperate demod & tuner Change-Id: I85b1a38a434a832865e1c4b4aa3feeef17a58dea Signed-off-by: Chuangcheng Peng --- .../common/media_clock/switch/amports_gate.c | 6 + .../stream_input/amports/amstream.c | 4 +- .../stream_input/parser/hw_demux/Makefile | 4 +- .../parser/hw_demux/aml_demod_gt.h | 40 + .../stream_input/parser/hw_demux/aml_dmx.c | 17 +- .../stream_input/parser/hw_demux/aml_dvb.c | 309 +- .../parser/hw_demux/aml_dvb_reg.h | 12 +- .../parser/hw_demux/c_stb_define.h | 802 +- .../parser/hw_demux/c_stb_regs_define.h | 9040 +---------------- .../stream_input/parser/tsdemux.c | 4 - 10 files changed, 1066 insertions(+), 9172 deletions(-) create mode 100644 drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_demod_gt.h diff --git a/drivers/amlogic/media_modules/common/media_clock/switch/amports_gate.c b/drivers/amlogic/media_modules/common/media_clock/switch/amports_gate.c index c2119f2f1ece..3d917e1f72b1 100644 --- a/drivers/amlogic/media_modules/common/media_clock/switch/amports_gate.c +++ b/drivers/amlogic/media_modules/common/media_clock/switch/amports_gate.c @@ -55,6 +55,12 @@ struct gate_switch_node gates[] = { { .name = "clk_hevcb_mux", }, + { + .name = "ahbarb0", + }, + { + .name = "asyncfifo", + }, }; /* diff --git a/drivers/amlogic/media_modules/stream_input/amports/amstream.c b/drivers/amlogic/media_modules/stream_input/amports/amstream.c index 42a227d9a59e..778ac89b9da6 100644 --- a/drivers/amlogic/media_modules/stream_input/amports/amstream.c +++ b/drivers/amlogic/media_modules/stream_input/amports/amstream.c @@ -80,7 +80,7 @@ #include "../../frame_provider/decoder/utils/firmware.h" #include "../../common/chips/chips.h" -#define G12A_BRINGUP_DEBUG +//#define G12A_BRINGUP_DEBUG #define CONFIG_AM_VDEC_REAL //DEBUG_TMP @@ -1090,8 +1090,6 @@ static ssize_t amstream_vbuf_write(struct file *file, const char *buf, struct stream_port_s *port = priv->port; struct stream_buf_s *pbuf = NULL; int r; - - if (has_hevc_vdec()) { pbuf = (port->type & PORT_TYPE_HEVC) ? &bufs[BUF_TYPE_HEVC] : &bufs[BUF_TYPE_VIDEO]; diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/Makefile b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/Makefile index 86d5b63ab5a0..e0315940b63a 100644 --- a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/Makefile +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/Makefile @@ -1,8 +1,8 @@ obj-m += aml_hardware_dmx.o -ccflags-y += -I$(srctree)/drivers/media/dvb-core -I$(srctree)/drivers/gpio -I$(srctree)/include +ccflags-y += -I$(srctree)/drivers/media/dvb-core -I$(srctree)/drivers/gpio -I$(srctree)/include -DENABLE_DEMUX_DRIVER aml_hardware_dmx-objs += aml_dvb.o aml_hardware_dmx-objs += aml_dmx.o -obj-y += dvb_ci/ +#obj-y += dvb_ci/ diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_demod_gt.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_demod_gt.h new file mode 100644 index 000000000000..7c06972e2c7b --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_demod_gt.h @@ -0,0 +1,40 @@ +/* + * test + * + * Copyright (C) 2018 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef __AML_DEMOD_GT_H__ +#define __AML_DEMOD_GT_H__ + +#include "dvb_frontend.h" + +struct amlfe_exp_config { + /*config by aml_fe ?*/ + /* */ + int set_mode; +}; + +static inline struct dvb_frontend* aml_dtvdm_attach (const struct amlfe_exp_config *config) { + return NULL; +} + +static inline struct dvb_frontend* si2151_attach (struct dvb_frontend *fe, u8 addr, + struct i2c_adapter *i2c/*, + struct si2151_config *cfg*/) +{ + return NULL; +} + +#endif /*__AML_DEMOD_GT_H__*/ diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dmx.c b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dmx.c index 56a40f1a807f..1d43c83cf987 100644 --- a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dmx.c +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dmx.c @@ -141,13 +141,13 @@ MODULE_PARM_DESC(use_of_sop, "\n\t\t Enable use of sop input"); static int use_of_sop; module_param(use_of_sop, int, 0644); -#define CIPLUS_KEY0 0x16f8 +/*#define CIPLUS_KEY0 0x16f8 #define CIPLUS_KEY1 0x16f9 #define CIPLUS_KEY2 0x16fa #define CIPLUS_KEY3 0x16fb #define CIPLUS_KEY_WR 0x16fc #define CIPLUS_CONFIG 0x16fd -#define CIPLUS_ENDIAN 0x16fe +#define CIPLUS_ENDIAN 0x16fe*/ static u32 old_stb_top_config; static u32 old_fec_input_control; @@ -1759,14 +1759,14 @@ static int dsc_set_csa_key(struct aml_dsc_channel *ch, int flags, } /************************* AES DESC************************************/ -#define STB_TOP_CONFIG 0x16f0 +/*#define STB_TOP_CONFIG 0x16f0 #define CIPLUS_KEY0 0x16f8 #define CIPLUS_KEY1 0x16f9 #define CIPLUS_KEY2 0x16fa #define CIPLUS_KEY3 0x16fb #define CIPLUS_KEY_WR 0x16fc #define CIPLUS_CONFIG 0x16fd -#define CIPLUS_ENDIAN 0x16fe +#define CIPLUS_ENDIAN 0x16fe*/ #define ENABLE_DEC_PL 7 #define ENABLE_DES_PL_CLK 15 @@ -2771,7 +2771,7 @@ static int dmx_enable(struct aml_dmx *dmx) (1 << OTHER_PES_PACKET)); DMX_WRITE_REG(dmx->id, PES_STRONG_SYNC, 0x1234); DMX_WRITE_REG(dmx->id, DEMUX_ENDIAN, - (1<dump_ts_select) << TS_RECORDER_SELECT) | (record << TS_RECORDER_ENABLE) | @@ -4381,11 +4381,8 @@ int aml_asyncfifo_hw_init(struct aml_asyncfifo *afifo) int aml_asyncfifo_hw_deinit(struct aml_asyncfifo *afifo) { - struct aml_dvb *dvb = afifo->dvb; - unsigned long flags; int ret; - spin_lock_irqsave(&dvb->slock, flags); ret = async_fifo_deinit(afifo, 1); /* *#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 @@ -4394,8 +4391,6 @@ int aml_asyncfifo_hw_deinit(struct aml_asyncfifo *afifo) */ /*afifo_reset(1);*/ - spin_unlock_irqrestore(&dvb->slock, flags); - return ret; } diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c index 82085fb82a42..58d8f8de9576 100644 --- a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c @@ -2,7 +2,8 @@ * AMLOGIC DVB driver. */ -#define ENABLE_DEMUX_DRIVER +//move to define in Makefile +//#define ENABLE_DEMUX_DRIVER #include #include @@ -35,6 +36,22 @@ #include "aml_dvb_reg.h" #include "../../tv_frontend/aml_fe.h" +#include "aml_demod_gt.h" +#include "../../../common/media_clock/switch/amports_gate.h" + +typedef enum __demod_type +{ + DEMOD_INVALID, + DEMOD_INTERNAL, + DEMOD_MAX_NUM +}demod_type; + +typedef enum __tuner_type +{ + TUNER_INVALID, + TUNER_SI2151, + TUNER_MAX_NUM +}tuner_type; #define pr_dbg(args...)\ do {\ @@ -58,6 +75,11 @@ module_param(dsc_max, int, 0644); static struct aml_dvb aml_dvb_device; static struct class aml_stb_class; + +static struct dvb_frontend *frontend = NULL; +static demod_type s_demod_type = DEMOD_INVALID; +static tuner_type s_tuner_type = TUNER_INVALID; + #if 0 static struct reset_control *aml_dvb_demux_reset_ctl; static struct reset_control *aml_dvb_afifo_reset_ctl; @@ -95,6 +117,32 @@ static struct tsdemux_ops aml_tsdemux_ops = { .set_demux = aml_tsdemux_set_demux }; +long aml_stb_get_base(int id) +{ + int newbase = 0; + if (MESON_CPU_MAJOR_ID_TXL < get_cpu_type() + && MESON_CPU_MAJOR_ID_GXLX != get_cpu_type()) { + newbase = 1; + } + + switch (id) { + case ID_STB_CBUS_BASE: + return (newbase) ? 0x1800 : 0x1600; + case ID_SMARTCARD_REG_BASE: + return (newbase) ? 0x9400 : 0x2110; + case ID_ASYNC_FIFO_REG_BASE: + return (newbase) ? 0x2800 : 0x2310; + case ID_ASYNC_FIFO2_REG_BASE: + return (newbase) ? 0x2400 : 0x2314; + case ID_RESET_BASE: + return (newbase) ? 0x0400 : 0x1100; + case ID_PARSER_SUB_START_PTR_BASE: + return (newbase) ? 0x3800 : 0x2900; + default: + return 0; + } + return 0; +} static void aml_dvb_dmx_release(struct aml_dvb *advb, struct aml_dmx *dmx) { int i; @@ -620,7 +668,6 @@ static int aml_dvb_asyncfifo_init(struct aml_dvb *advb, return aml_asyncfifo_hw_init(asyncfifo); } - static void aml_dvb_asyncfifo_release(struct aml_dvb *advb, struct aml_asyncfifo *asyncfifo) { @@ -1553,38 +1600,46 @@ static int aml_dvb_probe(struct platform_device *pdev) reset_control_deassert(aml_dvb_uparsertop_reset_ctl); #else - aml_dvb_demux_clk = - devm_clk_get(&pdev->dev, "demux"); - if (IS_ERR_OR_NULL(aml_dvb_demux_clk)) { - dev_err(&pdev->dev, "get demux clk fail\n"); - return -1; - } - clk_prepare_enable(aml_dvb_demux_clk); + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) + { + aml_dvb_demux_clk = + devm_clk_get(&pdev->dev, "demux"); + if (IS_ERR_OR_NULL(aml_dvb_demux_clk)) { + dev_err(&pdev->dev, "get demux clk fail\n"); + return -1; + } + clk_prepare_enable(aml_dvb_demux_clk); - aml_dvb_afifo_clk = - devm_clk_get(&pdev->dev, "asyncfifo"); - if (IS_ERR_OR_NULL(aml_dvb_afifo_clk)) { - dev_err(&pdev->dev, "get asyncfifo clk fail\n"); - return -1; - } - clk_prepare_enable(aml_dvb_afifo_clk); + aml_dvb_afifo_clk = + devm_clk_get(&pdev->dev, "asyncfifo"); + if (IS_ERR_OR_NULL(aml_dvb_afifo_clk)) { + dev_err(&pdev->dev, "get asyncfifo clk fail\n"); + return -1; + } + clk_prepare_enable(aml_dvb_afifo_clk); - aml_dvb_ahbarb0_clk = - devm_clk_get(&pdev->dev, "ahbarb0"); - if (IS_ERR_OR_NULL(aml_dvb_ahbarb0_clk)) { - dev_err(&pdev->dev, "get ahbarb0 clk fail\n"); - return -1; - } - clk_prepare_enable(aml_dvb_ahbarb0_clk); + aml_dvb_ahbarb0_clk = + devm_clk_get(&pdev->dev, "ahbarb0"); + if (IS_ERR_OR_NULL(aml_dvb_ahbarb0_clk)) { + dev_err(&pdev->dev, "get ahbarb0 clk fail\n"); + return -1; + } + clk_prepare_enable(aml_dvb_ahbarb0_clk); - - aml_dvb_uparsertop_clk = - devm_clk_get(&pdev->dev, "uparsertop"); - if (IS_ERR_OR_NULL(aml_dvb_uparsertop_clk)) { - dev_err(&pdev->dev, "get uparsertop clk fail\n"); - return -1; + aml_dvb_uparsertop_clk = + devm_clk_get(&pdev->dev, "uparsertop"); + if (IS_ERR_OR_NULL(aml_dvb_uparsertop_clk)) { + dev_err(&pdev->dev, "get uparsertop clk fail\n"); + return -1; + } + clk_prepare_enable(aml_dvb_uparsertop_clk); + } + else + { + amports_switch_gate("demux", 1); + amports_switch_gate("ahbarb0", 1); + amports_switch_gate("parser_top", 1); } - clk_prepare_enable(aml_dvb_uparsertop_clk); #endif advb = &aml_dvb_device; memset(advb, 0, sizeof(aml_dvb_device)); @@ -1612,6 +1667,7 @@ static int aml_dvb_probe(struct platform_device *pdev) advb->ts[i].mode = AM_TS_DISABLE; advb->ts[i].s2p_id = -1; + advb->ts[i].pinctrl = NULL; memset(buf, 0, 32); snprintf(buf, sizeof(buf), "ts%d", i); ret = @@ -1698,6 +1754,13 @@ static int aml_dvb_probe(struct platform_device *pdev) for (i = 0; i < DMX_DEV_COUNT; i++) advb->dmx[i].id = -1; + for (i = 0; idsc[i].id = -1; + + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) { + for (i = 0; i < ASYNCFIFO_COUNT; i++) + advb->asyncfifo[i].id = -1; + } advb->dvb_adapter.priv = advb; dev_set_drvdata(advb->dev, advb); @@ -1712,14 +1775,15 @@ static int aml_dvb_probe(struct platform_device *pdev) if (ret < 0) goto error; } - - /*Init the async fifos */ - for (i = 0; i < ASYNCFIFO_COUNT; i++) { - ret = aml_dvb_asyncfifo_init(advb, &advb->asyncfifo[i], i); - if (ret < 0) - goto error; + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) + { + /*Init the async fifos */ + for (i = 0; i < ASYNCFIFO_COUNT; i++) { + ret = aml_dvb_asyncfifo_init(advb, &advb->asyncfifo[i], i); + if (ret < 0) + goto error; + } } - aml_regist_dmx_class(); if (class_register(&aml_stb_class) < 0) { @@ -1727,15 +1791,113 @@ static int aml_dvb_probe(struct platform_device *pdev) goto error; } +#ifdef ENABLE_DEMUX_DRIVER tsdemux_set_ops(&aml_tsdemux_ops); +#else + tsdemux_set_ops(NULL); +#endif - return ret; -error: - for (i = 0; i < ASYNCFIFO_COUNT; i++) { - if (advb->asyncfifo[i].id != -1) - aml_dvb_asyncfifo_release(advb, &advb->asyncfifo[i]); + //pengcc add for dvb using linux TV frontend api init + { + struct amlfe_exp_config config; + struct i2c_adapter *i2c_adapter = NULL; + char buf[32]; + const char *str = NULL; + u32 adap_id = 0xFFFFFFFF; + u32 i2c_addr = 0xFFFFFFFF; + + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "demod"); + ret = of_property_read_string(pdev->dev.of_node, buf, &str); + if (ret) { + pr_error("can't find demod name\n"); + goto error_fe; + } + if (!strcmp(str,"internal")) + { + config.set_mode = 0; + frontend = dvb_attach(aml_dtvdm_attach,&config); + if (frontend == NULL) { + pr_error("dvb attach demod error\n"); + goto error_fe; + } else { + pr_inf("dtvdemod attatch sucess\n"); + s_demod_type = DEMOD_INTERNAL; + } + } else { + pr_error("dvb attach demod error\n"); + goto error_fe; + } + for (i=0; idev.of_node, buf, &str); + if (ret) { +// pr_error("tuner%d type error\n",i); + ret = 0; + continue; + } + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "tuner%d_i2c_adap_id",i); + ret = of_property_read_u32(pdev->dev.of_node, buf,&adap_id); + if (ret) { + pr_error("tuner_i2c_adap_id error\n"); + } else { + i2c_adapter = i2c_get_adapter(adap_id); + if (i2c_adapter == NULL) { + pr_error("i2c_get_adapter error\n"); + goto error_fe; + } + } + + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "tuner%d_i2c_addr",i); + ret = of_property_read_u32(pdev->dev.of_node, buf,&i2c_addr); + if (ret) { + pr_error("i2c_addr error\n"); + } + /* define general-purpose callback pointer */ + frontend->callback = NULL; + + if (!strcmp(str,"si2151_tuner")) { + if (!dvb_attach(si2151_attach, frontend,i2c_addr, + i2c_adapter)) { + pr_error("dvb attach tuner error\n"); + goto error_fe; + } else { + pr_inf("si2151 attach sucess\n"); + s_tuner_type = TUNER_SI2151; + } + }else { + pr_error("can't support tuner type: %s\n",str); + } + ret = dvb_register_frontend(&advb->dvb_adapter, frontend); + if (ret) { + pr_error("register dvb frontend failed\n"); + goto error_fe; + } + } +error_fe: + if (s_demod_type == DEMOD_INTERNAL) { + dvb_detach(aml_dtvdm_attach); + frontend = NULL; + s_demod_type = DEMOD_INVALID; + } + if (s_tuner_type == TUNER_SI2151) { + dvb_detach(si2151_attach); + s_tuner_type = TUNER_INVALID; + } + return 0; + } + return 0; +error: + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) + { + for (i = 0; i < ASYNCFIFO_COUNT; i++) { + if (advb->asyncfifo[i].id != -1) + aml_dvb_asyncfifo_release(advb, &advb->asyncfifo[i]); + } } - for (i = 0; i < DMX_DEV_COUNT; i++) { if (advb->dmx[i].id != -1) aml_dvb_dmx_release(advb, &advb->dmx[i]); @@ -1750,27 +1912,51 @@ error: return ret; } - static int aml_dvb_remove(struct platform_device *pdev) { struct aml_dvb *advb = (struct aml_dvb *)dev_get_drvdata(&pdev->dev); int i; + if (s_demod_type == DEMOD_INTERNAL) { + dvb_detach(aml_dtvdm_attach); + } + if (s_tuner_type == TUNER_SI2151) { + dvb_detach(si2151_attach); + } + if (frontend && (s_tuner_type == TUNER_SI2151)) { + dvb_unregister_frontend(frontend); + dvb_frontend_detach(frontend); + } + frontend = NULL; + s_demod_type = DEMOD_INVALID; + s_tuner_type = TUNER_INVALID; + tsdemux_set_ops(NULL); aml_unregist_dmx_class(); class_unregister(&aml_stb_class); + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) + { + for (i = 0; i < ASYNCFIFO_COUNT; i++) { + if (advb->asyncfifo[i].id != -1) + aml_dvb_asyncfifo_release(advb, &advb->asyncfifo[i]); + } + } - for (i = 0; i < DSC_DEV_COUNT; i++) - aml_dvb_dsc_release(advb, &advb->dsc[i]); - - for (i = 0; i < DMX_DEV_COUNT; i++) - aml_dvb_dmx_release(advb, &advb->dmx[i]); + for (i = 0; i < DMX_DEV_COUNT; i++) { + pr_error("remove demx %d, id is %d\n",i,advb->dmx[i].id); + if (advb->dmx[i].id != -1) + aml_dvb_dmx_release(advb, &advb->dmx[i]); + } + for (i = 0; i < DSC_DEV_COUNT; i++) { + if (advb->dsc[i].id != -1) + aml_dvb_dsc_release(advb, &advb->dsc[i]); + } dvb_unregister_adapter(&advb->dvb_adapter); for (i = 0; i < TS_IN_COUNT; i++) { - if (advb->ts[i].pinctrl) + if (advb->ts[i].pinctrl && !IS_ERR_VALUE(advb->ts[i].pinctrl)) devm_pinctrl_put(advb->ts[i].pinctrl); } @@ -1781,10 +1967,21 @@ static int aml_dvb_remove(struct platform_device *pdev) reset_control_assert(aml_dvb_afifo_reset_ctl); reset_control_assert(aml_dvb_demux_reset_ctl); #else - clk_disable_unprepare(aml_dvb_uparsertop_clk); - clk_disable_unprepare(aml_dvb_ahbarb0_clk); - clk_disable_unprepare(aml_dvb_afifo_clk); - clk_disable_unprepare(aml_dvb_demux_clk); +#if 1 + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) + { + clk_disable_unprepare(aml_dvb_uparsertop_clk); + clk_disable_unprepare(aml_dvb_ahbarb0_clk); + clk_disable_unprepare(aml_dvb_afifo_clk); + clk_disable_unprepare(aml_dvb_demux_clk); + } + else + { + amports_switch_gate("demux", 0); + amports_switch_gate("ahbarb0", 0); + amports_switch_gate("parser_top", 0); + } +#endif #endif return 0; } @@ -1824,7 +2021,7 @@ static struct platform_driver aml_dvb_driver = { .name = "amlogic-dvb", .owner = THIS_MODULE, #ifdef CONFIG_OF - .of_match_table = aml_dvb_dt_match, + .of_match_table = aml_dvb_dt_match, #endif } }; @@ -1950,7 +2147,6 @@ static int aml_tsdemux_set_vid(int vpid) int ret = 0; spin_lock_irqsave(&dvb->slock, flags); - dmx = get_stb_dmx(); if (dmx) { if (dmx->vid_chan != -1) { @@ -1981,7 +2177,6 @@ static int aml_tsdemux_set_aid(int apid) int ret = 0; spin_lock_irqsave(&dvb->slock, flags); - dmx = get_stb_dmx(); if (dmx) { if (dmx->aud_chan != -1) { diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb_reg.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb_reg.h index 16163992d531..180b3d897e96 100644 --- a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb_reg.h +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb_reg.h @@ -20,6 +20,16 @@ #include +#include + +#define ID_STB_CBUS_BASE 0 +#define ID_SMARTCARD_REG_BASE 1 +#define ID_ASYNC_FIFO_REG_BASE 2 +#define ID_ASYNC_FIFO2_REG_BASE 3 +#define ID_RESET_BASE 4 +#define ID_PARSER_SUB_START_PTR_BASE 5 + +long aml_stb_get_base(int id); #include "c_stb_define.h" #include "c_stb_regs_define.h" @@ -36,7 +46,7 @@ #define AM_IRQ(reg) (reg + BASE_IRQ) #define INT_DEMUX AM_IRQ(23) #define INT_DEMUX_1 AM_IRQ(5) -#define INT_DEMUX_2 AM_IRQ(53) +#define INT_DEMUX_2 AM_IRQ(21) //AM_IRQ(53) #define INT_ASYNC_FIFO_FILL AM_IRQ(18) #define INT_ASYNC_FIFO_FLUSH AM_IRQ(19) #define INT_ASYNC_FIFO2_FILL AM_IRQ(24) diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h index 6447bbb77d87..a5309d52753c 100644 --- a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h @@ -18,19 +18,17 @@ /* STB Registers Start*/ /*=================================================*/ /* -----------------------------------------------*/ -#define STB_CBUS_BASE 0x1600 +/*#define STB_CBUS_BASE 0x1600*/ /* -----------------------------------------------*/ /* There are two instantiations under one CBUS slave. - * Each CBUS slave can support - */ + * Each CBUS slave can support*/ /* 256 registers. - * Each demux is allocated 128 registers so set the offset in - */ + * Each demux is allocated 128 registers so set the offset in*/ /* the middle*/ /* Copy this define but don't add a base address*/ -#define DEMUX_1_OFFSET 0x00 -#define DEMUX_2_OFFSET 0x50 -#define DEMUX_3_OFFSET 0xa0 +/*#define DEMUX_1_OFFSET 0x00*/ +/*#define DEMUX_2_OFFSET 0x50*/ +/*#define DEMUX_3_OFFSET 0xa0*/ /*======================================================*/ /* STB TOP Registers (8'hf0 - 8'hf7)*/ /*======================================================*/ @@ -45,16 +43,13 @@ /* bit 19 -- invert fec_valid for S2P1*/ /* bit 18 -- invert fec_clk for S2P1*/ /* bit 17:16 -- fec_s_sel for S2P1 - * 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved - */ + * 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved*/ /* Bit 15 -- enable_des_pl_clk*/ /* Bit 14:13 -- reserved*/ /* Bit 12:10 -- ts_out_select, - * 0-TS0, 1-TS1, 2-TS2, 3,4-Reserved, 5-S2P1, 6-S2P0, 7-File - */ + * 0-TS0, 1-TS1, 2-TS2, 3,4-Reserved, 5-S2P1, 6-S2P0, 7-File*/ /* bit 9:8 -- des_i_sel 00 -- select demux0 as des input, - * 01 -- select_demux1, 10 -- select_demux2, 11 - reserved - */ +* 01 -- select_demux1, 10 -- select_demux2, 11 - reserved*/ /* bit 7 -- enable_des_pl*/ /* bit 6 -- invert fec_error for S2P0*/ /* bit 5 -- invert fec_data for S2P0*/ @@ -62,8 +57,7 @@ /* bit 3 -- invert fec_valid for S2P0*/ /* bit 2 -- invert fec_clk for S2P0*/ /* bit 1:0 -- fec_s_sel for S2P0 - * 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved - */ + * 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved*/ /*#define STB_TOP_CONFIG (STB_CBUS_BASE + 0xf0) // 0x16f0*/ /*----------- bit define -----------*/ #define INVERT_S2P1_FEC_ERROR 22 @@ -136,17 +130,14 @@ /*#define COMM_DESC_KEY0 * (STB_CBUS_BASE + 0xf5) // 0x16f5 - Common descrambler key (key bits[63:32]) -*/ + Common descrambler key (key bits[63:32])*/ /*#define COMM_DESC_KEY1 * (STB_CBUS_BASE + 0xf6) // 0x16f6 - Common descrambler key (key bits[31:0]) -*/ + Common descrambler key (key bits[31:0])*/ /*#define COMM_DESC_KEY_RW * (STB_CBUS_BASE + 0xf7) // 0x16f7 // bits[3:0] * point to the address to write the key - * {COMM_DESC_KEY3,...,COMM_DESC_KEY0} - */ + * {COMM_DESC_KEY3,...,COMM_DESC_KEY0}*/ /* Writing this register writes the key to RAM*/ /* bit 15:8 - des_out_dly_2*/ @@ -155,9 +146,8 @@ /* bit 5 - enable_des_pl_2*/ /* bit 4:2 -- use_des_2 bit[2] -- demux0, bit[3] -- demux1, bit[4] -- demux2*/ /* bit 1:0 -- des_i_sel_2 00 -- select_fec_0, 01 -- select_fec_1, - * 10 -- select_fec_2, 11 - reserved - */ -#define COMM_DESC_2_CTL (STB_CBUS_BASE + 0xff) /*0x16ff*/ + * 10 -- select_fec_2, 11 - reserved*/ +/*#define COMM_DESC_2_CTL (STB_CBUS_BASE + 0xff) *//*0x16ff*/ /*=======================================================*/ /* Multiple STB Registers (8'h00 - 8'h45)*/ @@ -165,43 +155,33 @@ /* STB registers are 8'h0x*/ /* Bit 15:0 -- version number : 0x0002 (v0.01)*/ /*#define STB_VERSION - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x00) // 0x1600 // read only - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x00) // 0x1600 // read only*/ /*#define STB_VERSION_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x00) // 0x1650 // read only - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x00) // 0x1650 // read only*/ /*#define STB_VERSION_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x00) // 0x16a0 // read only - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x00) // 0x16a0 // read only*/ /*#define STB_TEST_REG - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x01) // 0x1601 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x01) // 0x1601*/ /*#define STB_TEST_REG_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x01) // 0x1651 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x01) // 0x1651*/ /*#define STB_TEST_REG_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x01) // 0x16a1 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x01) // 0x16a1*/ /* Bit 15 -- fec_core_select 1 - select descramble output*/ /* Bit 14:12 - fec_select - * 0-TS0, 1-TS1, 2-TS2, 3,4-Reserved, 5-S2P1, 6-S2P0, 7-File - */ + * 0-TS0, 1-TS1, 2-TS2, 3,4-Reserved, 5-S2P1, 6-S2P0, 7-File*/ /* Bit 11 -- FEC_CLK*/ /* Bit 10 -- SOP*/ /* Bit 9 -- D_VALID*/ /* Bit 8 -- D_FAIL*/ /* Bit 7:0 -- D_DATA 7:0*/ /*#define FEC_INPUT_CONTROL - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x02) // 0x1602 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x02) // 0x1602*/ /*#define FEC_INPUT_CONTROL_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x02) // 0x1652 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x02) // 0x1652*/ /*#define FEC_INPUT_CONTROL_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x02) // 0x16a2 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x02) // 0x16a2*/ /*----------- bit define -----------*/ #define FEC_CORE_SEL 15 #define FEC_SEL 12 @@ -211,14 +191,11 @@ #define FEC_INPUT_D_FAIL 8 /*#define FEC_INPUT_DATA - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x03) // 0x1603 // read only - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x03) // 0x1603 // read only*/ /*#define FEC_INPUT_DATA_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x03) // 0x1653 // read only - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x03) // 0x1653 // read only*/ /*#define FEC_INPUT_DATA_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x03) // 0x16a3 // read only - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x03) // 0x16a3 // read only*/ /* bit 31 -- enable_free_clk_fec_data_valid*/ /* bit 30 -- enable_free_clk_stb_reg*/ @@ -248,19 +225,15 @@ /* Bit 4 - stb demux enable*/ /* Bit 3 - do not reset state machine on SOP*/ /* Bit 2 - search SOP when error happened - * ( when ignore_fail_n_sop, will have this case) - */ + * ( when ignore_fail_n_sop, will have this case)*/ /* Bit 1 - do not use SOP input ( check FEC sync byte instead )*/ /* Bit 0 - ignore fec_error bit when non sop ( check error on SOP only)*/ /*#define DEMUX_CONTROL - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x04) // 0x1604 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x04) // 0x1604*/ /*#define DEMUX_CONTROL_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x04) // 0x1654 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x04) // 0x1654*/ /*#define DEMUX_CONTROL_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x04) // 0x16a4 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x04) // 0x16a4*/ /*----------- bit define -----------*/ #define ENABLE_FREE_CLK_FEC_DATA_VALID 31 #define ENABLE_FREE_CLK_STB_REG 30 @@ -271,14 +244,14 @@ #define INSERT_VIDEO_PES_STRONG_SYNC 16 #define SECTION_LENGTH_UNTRUSTY 15 #define OM_CMD_PUSH_EVEN_ZERO 14 -#define OTHER_INT_AT_PES_BEGINNING 12 +#define OTHER_INT_AT_PES_BEGINING 12 #define DISCARD_AV_PACKAGE 11 #define TS_RECORDER_SELECT 10 #define TS_RECORDER_ENABLE 9 #define SECTION_END_WITH_TABLE_ID 8 #define SEND_COMPLETE_SECTION_ONLY 7 #define KEEP_DUPLICATE_PACKAGE 6 -#define SEARCH_SOP_ON_TRANSPORT_ERROR 5 +#define SEACH_SOP_ON_TRANSPORT_ERROR 5 #define STB_DEMUX_ENABLE 4 #define NO_RESET_ON_SOP 3 #define SEARCH_SOP_ON_ERROR 2 @@ -288,14 +261,11 @@ /* bit 15:8 demux package length - 1 ( default : 187 )*/ /* bit 7:0 default is 0x47*/ /*#define FEC_SYNC_BYTE - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x05) // 0x1605 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x05) // 0x1605*/ /*#define FEC_SYNC_BYTE_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x05) // 0x1655 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x05) // 0x1655*/ /*#define FEC_SYNC_BYTE_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x05) // 0x16a5 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x05) // 0x16a5*/ /**************************************** * FM Memory Usage : @@ -341,14 +311,11 @@ /* bit 31:16 -- filter memory write data hi[31:16]*/ /* bit 15:0 -- filter memory write data low [15:0]*/ /*#define FM_WR_DATA - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x06) // 0x1606 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x06) // 0x1606*/ /*#define FM_WR_DATA_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x06) // 0x1656 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x06) // 0x1656*/ /*#define FM_WR_DATA_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x06) // 0x16a6 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x06) // 0x16a6*/ /*----------- bit define -----------*/ #define FM_WR_DATA_HI 16 @@ -357,14 +324,11 @@ /* bit 15 -- filter memory write data request*/ /* bit 7:0 -- filter memory write addr*/ /*#define FM_WR_ADDR - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x07) // 0x1607 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x07) // 0x1607*/ /*#define FM_WR_ADDR_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x07) // 0x1657 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x07) // 0x1657*/ /*#define FM_WR_ADDR_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x07) // 0x16a7 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x07) // 0x16a7*/ /*----------- bit define -----------*/ #define FM_ADVANCED_SETTING_HI 24 #define FM_ADVANCED_SETTING_LO 16 @@ -374,14 +338,11 @@ /* bit 7:4 -- maxnum section filter compare address*/ /* bit 3:0 -- maxnum PID filter compare address*/ /*#define MAX_FM_COMP_ADDR - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x08) // 0x1608 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x08) // 0x1608*/ /*#define MAX_FM_COMP_ADDR_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x08) // 0x1658 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x08) // 0x1658*/ /*#define MAX_FM_COMP_ADDR_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x08) // 0x16a8 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x08) // 0x16a8*/ /*----------- bit define -----------*/ #define DEMUX_STATE 8 #define MAX_FM_SECTION_FILTER_COMP_ADDR 4 @@ -391,14 +352,11 @@ /* bit 13 - transport_priority*/ /* bit 12:0 - PID*/ /*#define TS_HEAD_0 - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x09) // 0x1609 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x09) // 0x1609*/ /*#define TS_HEAD_0_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x09) // 0x1659 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x09) // 0x1659*/ /*#define TS_HEAD_0_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x09) // 0x16a9 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x09) // 0x16a9*/ /*----------- bit define -----------*/ #define TRANSPORT_ERROR_INDICATOR 15 #define PAYLOAD_UNIT_START_INDICATOR 14 @@ -408,14 +366,11 @@ /* bit 5:4 adaptation_field_control*/ /* bit 3:0 continuity_counter*/ /*#define TS_HEAD_1 - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0a) // 0x160a - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0a) // 0x160a*/ /*#define TS_HEAD_1_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0a) // 0x165a - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0a) // 0x165a*/ /*#define TS_HEAD_1_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0a) // 0x16aa - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0a) // 0x16aa*/ /*----------- bit define -----------*/ #define TRANSPORT_SCRAMBLING_CONTROL 6 #define ADAPTATION_FIELD_CONTROL 4 @@ -429,14 +384,11 @@ /* bit 0 -- om_cmd_pending (read)*/ /* bit 0 -- om_cmd_read_finished (write)*/ /*#define OM_CMD_STATUS - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0b) // 0x160b - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0b) // 0x160b*/ /*#define OM_CMD_STATUS_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0b) // 0x165b - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0b) // 0x165b*/ /*#define OM_CMD_STATUS_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0b) // 0x16ab - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0b) // 0x16ab*/ /*----------- bit define -----------*/ #define OM_CMD_COUNT 12 #define OM_OVERFLOW_COUNT 9 @@ -448,61 +400,45 @@ /* bit 15:9 -- count_stb_om_w_rd (read only)*/ /* bit 8:0 -- start_stb_om_wa_rd (read only)*/ /*#define OM_CMD_DATA - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0c) // 0x160c - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0c) // 0x160c*/ /*#define OM_CMD_DATA_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0c) // 0x165c - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0c) // 0x165c*/ /*#define OM_CMD_DATA_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0c) // 0x16ac - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0c) // 0x16ac*/ /*----------- bit define -----------*/ #define COUNT_STB_OM_W_RD 9 /* bit 11:0 -- offset for section data*/ /*#define OM_CMD_DATA2 - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0d) // 0x160d - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0d) // 0x160d*/ /*#define OM_CMD_DATA2_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0d) // 0x165d - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0d) // 0x165d*/ /*#define OM_CMD_DATA2_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0d) // 0x16ad - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0d) // 0x16ad*/ /* bit 31:16 -- base address for section buffer group 0 - * (*0x400 to get real address) - */ + * (*0x400 to get real address)*/ /* bit 15:0 -- base address for section buffer group 1 - * (*0x400 to get real address) - */ + * (*0x400 to get real address)*/ /*#define SEC_BUFF_01_START - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0e) // 0x160e - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0e) // 0x160e*/ /*#define SEC_BUFF_01_START_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0e) // 0x165e - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0e) // 0x165e*/ /*#define SEC_BUFF_01_START_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0e) // 0x16ae - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0e) // 0x16ae*/ /*----------- bit define -----------*/ #define SEC_BUFF_0_BASE_ADDR 16 /* bit 31:16 -- base address for section buffer group 2 - * (*0x400 to get real address) - */ + * (*0x400 to get real address)*/ /* bit 15:0 -- base address for section buffer group 3 - * (*0x400 to get real address) - */ + * (*0x400 to get real address)*/ /*#define SEC_BUFF_23_START - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0f) // 0x160f - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0f) // 0x160f*/ /*#define SEC_BUFF_23_START_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0f) // 0x165f - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0f) // 0x165f*/ /*#define SEC_BUFF_23_START_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0f) // 0x16af - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0f) // 0x16af*/ /*----------- bit define -----------*/ #define SEC_BUFF_2_BASE_ADDR 16 @@ -510,17 +446,13 @@ /* bit 11:8 -- section buffer size for group 2*/ /* bit 7:4 -- section buffer size for group 1*/ /* bit 3:0 -- section buffer size for group 0 - * (bit used, for example, 10 means 1K) - */ + * (bit used, for example, 10 means 1K)*/ /*#define SEC_BUFF_SIZE - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x10) // 0x1610 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x10) // 0x1610*/ /*#define SEC_BUFF_SIZE_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x10) // 0x1660 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x10) // 0x1660*/ /*#define SEC_BUFF_SIZE_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x10) // 0x16b0 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x10) // 0x16b0*/ /*----------- bit define -----------*/ #define SEC_BUFF_3_SIZE 12 #define SEC_BUFF_2_SIZE 8 @@ -528,40 +460,31 @@ /* section buffer busy status for buff 31:0 ( Read Only )*/ /*#define SEC_BUFF_BUSY - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x11) // 0x1611 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x11) // 0x1611*/ /*#define SEC_BUFF_BUSY_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x11) // 0x1661 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x11) // 0x1661*/ /*#define SEC_BUFF_BUSY_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x11) // 0x16b1 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x11) // 0x16b1*/ /* section buffer write status for buff 31:0 -- Read*/ /* clear buffer status ( buff READY and BUSY ) -- write*/ /*#define SEC_BUFF_READY - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x12) // 0x1612 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x12) // 0x1612*/ /*#define SEC_BUFF_READY_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x12) // 0x1662 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x12) // 0x1662*/ /*#define SEC_BUFF_READY_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x12) // 0x16b2 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x12) // 0x16b2*/ /* bit 15 -- section_reset_busy (Read Only)*/ /* bit 14 -- output_section_buffer_valid*/ /* bit 12:8 -- SEC_BUFFER_NUMBER for the INDEX buffer Read_Only*/ /* bit 4:0 -- SEC_BUFFER_INDEX RW*/ /*#define SEC_BUFF_NUMBER - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x13) // 0x1613 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x13) // 0x1613*/ /*#define SEC_BUFF_NUMBER_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x13) // 0x1663 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x13) // 0x1663*/ /*#define SEC_BUFF_NUMBER_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x13) // 0x16b3 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x13) // 0x16b3*/ /*----------- bit define -----------*/ #define SECTION_RESET_BUSY 15 #define OUTPUT_SECTION_BUFFER_VALID 14 @@ -570,127 +493,94 @@ /* bit 9:5 -- BYPASS PID number*/ /* bit 4:0 -- PCR PID number*/ /*#define ASSIGN_PID_NUMBER - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x14) // 0x1614 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x14) // 0x1614*/ /*#define ASSIGN_PID_NUMBER_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x14) // 0x1664 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x14) // 0x1664*/ /*#define ASSIGN_PID_NUMBER_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x14) // 0x16b4 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x14) // 0x16b4*/ /*----------- bit define -----------*/ #define BYPASS_PID_NUMBER 5 /* bit 15:0 -- stream_id filter bit enable*/ /* bit 7:0 -- stream_id filter target*/ /*#define VIDEO_STREAM_ID - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x15) // 0x1615 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x15) // 0x1615*/ /*#define VIDEO_STREAM_ID_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x15) // 0x1665 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x15) // 0x1665*/ /*#define VIDEO_STREAM_ID_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x15) // 0x16b5 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x15) // 0x16b5*/ /*#define AUDIO_STREAM_ID - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x16) // 0x1616 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x16) // 0x1616*/ /*#define AUDIO_STREAM_ID_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x16) // 0x1666 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x16) // 0x1666*/ /*#define AUDIO_STREAM_ID_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x16) // 0x16b6 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x16) // 0x16b6*/ /*#define SUB_STREAM_ID - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x17) // 0x1617 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x17) // 0x1617*/ /*#define SUB_STREAM_ID_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x17) // 0x1667 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x17) // 0x1667*/ /*#define SUB_STREAM_ID_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x17) // 0x16b7 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x17) // 0x16b7*/ /*#define OTHER_STREAM_ID - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x18) // 0x1618 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x18) // 0x1618*/ /*#define OTHER_STREAM_ID_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x18) // 0x1668 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x18) // 0x1668*/ /*#define OTHER_STREAM_ID_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x18) // 0x16b8 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x18) // 0x16b8*/ /* bit 12 -- PCR_EN*/ /* bit 11:0 -- PCR90K_DIV*/ /*#define PCR90K_CTL - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x19) // 0x1619 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x19) // 0x1619*/ /*#define PCR90K_CTL_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x19) // 0x1669 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x19) // 0x1669*/ /*#define PCR90K_CTL_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x19) // 0x16b9 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x19) // 0x16b9*/ /*----------- bit define -----------*/ #define PCR_EN 12 /* bit 15:0 -- PCR[31:0] R/W*/ /*#define PCR_DEMUX - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1a) // 0x161a - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1a) // 0x161a*/ /*#define PCR_DEMUX_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1a) // 0x166a - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1a) // 0x166a*/ /*#define PCR_DEMUX_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1a) // 0x16ba - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1a) // 0x16ba*/ /* bit 15:0 -- VPTS[31:0] R/W*/ /*#define VIDEO_PTS_DEMUX - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1b) // 0x161b - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1b) // 0x161b*/ /*#define VIDEO_PTS_DEMUX_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1b) // 0x166b - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1b) // 0x166b*/ /*#define VIDEO_PTS_DEMUX_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1b) // 0x16bb - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1b) // 0x16bb*/ /* bit 15:0 -- VDTS[31:0] R/W*/ /*#define VIDEO_DTS_DEMUX - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1c) // 0x161c - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1c) // 0x161c*/ /*#define VIDEO_DTS_DEMUX_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1c) // 0x166c - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1c) // 0x166c*/ /*#define VIDEO_DTS_DEMUX_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1c) // 0x16bc - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1c) // 0x16bc*/ /* bit 15:0 -- APTS[31:0] R/W*/ /*#define AUDIO_PTS_DEMUX - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1d) // 0x161d - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1d) // 0x161d*/ /*#define AUDIO_PTS_DEMUX_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1d) // 0x166d - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1d) // 0x166d*/ /*#define AUDIO_PTS_DEMUX_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1d) // 0x16bd - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1d) // 0x16bd*/ /* bit 15:0 -- SPTS[31:0] R/W*/ /*#define SUB_PTS_DEMUX - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1e) // 0x161e - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1e) // 0x161e*/ /*#define SUB_PTS_DEMUX_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1e) // 0x166e - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1e) // 0x166e*/ /*#define SUB_PTS_DEMUX_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1e) // 0x16be - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1e) // 0x16be*/ /* read -- status, write 1 clear status*/ /* bit 15 -- SUB_PTS[32]*/ @@ -702,14 +592,11 @@ /* bit 1 -- video_dts_ready*/ /* bit 0 -- video_pts_ready*/ /*#define STB_PTS_DTS_STATUS - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1f) // 0x161f - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1f) // 0x161f*/ /*#define STB_PTS_DTS_STATUS_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1f) // 0x166f - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1f) // 0x166f*/ /*#define STB_PTS_DTS_STATUS_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1f) // 0x16bf - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1f) // 0x16bf*/ /*----------- bit define -----------*/ #define SUB_PTS_BIT32 15 #define AUDIO_PTS_BIT32 14 @@ -726,37 +613,31 @@ /* 2 -- pes_package_bytes_left[15:0]*/ /* 3 -- pes_ctr_byte[7:0], pes_flag_byte[7:0]*/ /*#define STB_DEBUG_INDEX - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x20) // 0x1620 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x20) // 0x1620*/ /*#define STB_DEBUG_INDEX_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x20) // 0x1670 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x20) // 0x1670*/ /*#define STB_DEBUG_INDEX_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x20) // 0x16c0 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x20) // 0x16c0*/ /* read only*/ /*#define STB_DEBUG_DATA_OUT - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x21) // 0x1621 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x21) // 0x1621*/ /*#define STB_DEBUG_DATA_OUT_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x21) // 0x1671 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x21) // 0x1671*/ /*#define STB_DEBUG_DATA_OUT_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x21) // 0x16c1 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x21) // 0x16c1*/ /* bit[31] -- no_match_record_en*/ /* bit[30:16] - reserved*/ /* default : 0x807f*/ /* bit 15:9 -- MAX OM DMA COUNT (default: 0x40)*/ /* bit 8:0 -- LAST ADDR OF OM ADDR (default: 127)*/ -#define STB_OM_CTL \ - (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x22) /* 0x1622*/ -#define STB_OM_CTL_2 \ - (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x22) /* 0x1672*/ -#define STB_OM_CTL_3 \ - (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x22) /* 0x16c2*/ +/*#define STB_OM_CTL \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x22) // 0x1622*/ +/*#define STB_OM_CTL_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x22) // 0x1672*/ +/*#define STB_OM_CTL_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x22) // 0x16c2*/ /*----------- bit define -----------*/ #define MAX_OM_DMA_COUNT 9 #define LAST_OM_ADDR 0 @@ -776,14 +657,11 @@ /* 1 -- transport_error_indicator*/ /* 0 -- TS ERROR PIN*/ /*#define STB_INT_STATUS - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x23) // 0x1623 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x23) // 0x1623*/ /*#define STB_INT_STATUS_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x23) // 0x1673 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x23) // 0x1673*/ /*#define STB_INT_STATUS_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x23) // 0x16c3 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x23) // 0x16c3*/ /*----------- bit define -----------*/ #define INPUT_TIME_OUT 12 #define PCR_READY 11 @@ -800,8 +678,7 @@ #define TS_ERROR_PIN 0 /* When Bit 31 - 1 write will indicate all type use sepertate endian - * (Write Only) - */ + * (Write Only)*/ /* When Bit 31 - 0 write will indicate all type else use Bit 8:6*/ /* Bit 23:21 - demux om write endian control for OTHER_PES_PACKET*/ /* Bit 20:18 - demux om write endian control for SCR_ONLY_PACKET*/ @@ -812,16 +689,13 @@ /* Bit 5:3 - demux om write endian control for bypass*/ /* Bit 2:0 - demux om write endian control for section*/ /*#define DEMUX_ENDIAN - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x24) // 0x1624 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x24) // 0x1624*/ /*#define DEMUX_ENDIAN_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x24) // 0x1674 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x24) // 0x1674*/ /*#define DEMUX_ENDIAN_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x24) // 0x16c4 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x24) // 0x16c4*/ /*----------- bit define -----------*/ -#define SEPARATE_ENDIAN 31 +#define SEPERATE_ENDIAN 31 #define OTHER_PES_ENDIAN 21 #define SCR_ENDIAN 18 #define SUB_ENDIAN 15 @@ -837,30 +711,23 @@ /* Bit 1 ts_source_sel */ /* Bit 0 - Hiu TS generate enable */ /*#define TS_HIU_CTL - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x25) // 0x1625 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x25) // 0x1625*/ /*#define TS_HIU_CTL_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x25) // 0x1675 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x25) // 0x1675*/ /*#define TS_HIU_CTL_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x25) // 0x16c5 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x25) // 0x16c5*/ /*----------- bit define -----------*/ #define LAST_BURST_THRESHOLD 8 #define USE_HI_BSF_INTERFACE 7 /* bit 15:0 -- base address for section buffer start - * (*0x10000 to get real base) - */ + * (*0x10000 to get real base)*/ /*#define SEC_BUFF_BASE - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x26) // 0x1626 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x26) // 0x1626*/ /*#define SEC_BUFF_BASE_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x26) // 0x1676 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x26) // 0x1676*/ /*#define SEC_BUFF_BASE_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x26) // 0x16c6 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x26) // 0x16c6*/ /* bit 11 -- mask bit for OTHER_PES_AHB_DMA_EN*/ /* bit 10 -- mask bit for SUB_AHB_DMA_EN*/ @@ -869,14 +736,11 @@ /* bit 7 -- mask bit for recoder stream*/ /* bit 6:0 -- mask bit for each type*/ /*#define DEMUX_MEM_REQ_EN - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x27) // 0x1627 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x27) // 0x1627*/ /*#define DEMUX_MEM_REQ_EN_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x27) // 0x1677 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x27) // 0x1677*/ /*#define DEMUX_MEM_REQ_EN_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x27) // 0x16c7 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x27) // 0x16c7*/ /*----------- bit define -----------*/ #define VIDEO2_DMA_EN_BIT 12 #define OTHER_PES_AHB_DMA_EN 11 @@ -894,114 +758,84 @@ /* bit 31:0 -- vb_wr_ptr for video PDTS*/ /*#define VIDEO_PDTS_WR_PTR - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x28) // 0x1628 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x28) // 0x1628*/ /*#define VIDEO_PDTS_WR_PTR_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x28) // 0x1678 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x28) // 0x1678*/ /*#define VIDEO_PDTS_WR_PTR_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x28) // 0x16c8 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x28) // 0x16c8*/ /* bit 31:0 -- ab_wr_ptr for audio PDTS*/ /*#define AUDIO_PDTS_WR_PTR - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x29) // 0x1629 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x29) // 0x1629*/ /*#define AUDIO_PDTS_WR_PTR_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x29) // 0x1679 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x29) // 0x1679*/ /*#define AUDIO_PDTS_WR_PTR_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x29) // 0x16c9 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x29) // 0x16c9*/ /* bit 20:0 -- SB_WRITE_PTR (sb_wr_ptr << 3 == byte write position)*/ /*#define SUB_WR_PTR - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2a) // 0x162a - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2a) // 0x162a*/ /*#define SUB_WR_PTR_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2a) // 0x167a - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2a) // 0x167a*/ /*#define SUB_WR_PTR_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2a) // 0x16ca - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2a) // 0x16ca*/ /* bit 19:0 -- SB_START (sb_start << 12 == byte address);*/ /*#define SB_START - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2b) // 0x162b - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2b) // 0x162b*/ /*#define SB_START_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2b) // 0x167b - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2b) // 0x167b*/ /*#define SB_START_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2b) // 0x16cb - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2b) // 0x16cb*/ /* bit 20:0 -- SB_SIZE (sb_size << 3 == byte size, 16M maximun)*/ /*#define SB_LAST_ADDR - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2c) // 0x162c - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2c) // 0x162c*/ /*#define SB_LAST_ADDR_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2c) // 0x167c - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2c) // 0x167c*/ /*#define SB_LAST_ADDR_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2c) // 0x16cc - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2c) // 0x16cc*/ /* bit 31:0 -- sb_wr_ptr for sub PES*/ /*#define SB_PES_WRITE_PTR - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2d) // 0x162d - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2d) // 0x162d*/ /*#define SB_PES_WRITE_PTR_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2d) // 0x167d - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2d) // 0x167d*/ /*#define SB_PES_WRITE_PTR_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2d) // 0x16cd - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2d) // 0x16cd*/ /* bit 31:16 -- ob_wr_ptr for other PES*/ /* bit 20:0 -- OB_WRITE_PTR (ob_wr_ptr << 3 == byte write position)*/ /*#define OTHER_WR_PTR - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2e) // 0x162e - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2e) // 0x162e*/ /*#define OTHER_WR_PTR_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2e) // 0x167e - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2e) // 0x167e*/ /*#define OTHER_WR_PTR_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2e) // 0x16ce - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2e) // 0x16ce*/ /* bit 19:0 -- OB_START (ob_start << 12 == byte address);*/ /*#define OB_START - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2f) // 0x162f - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2f) // 0x162f*/ /*#define OB_START_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2f) // 0x167f - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2f) // 0x167f*/ /*#define OB_START_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2f) // 0x16cf - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2f) // 0x16cf*/ /* bit 20:0 -- OB_SIZE (ob_size << 3 == byte size, 16M maximun)*/ /*#define OB_LAST_ADDR - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x30) // 0x1630 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x30) // 0x1630*/ /*#define OB_LAST_ADDR_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x30) // 0x1680 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x30) // 0x1680*/ /*#define OB_LAST_ADDR_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x30) // 0x16d0 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x30) // 0x16d0*/ /* bit 31:0 -- ob_wr_ptr for sub PES*/ /*#define OB_PES_WRITE_PTR - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x31) // 0x1631 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x31) // 0x1631*/ /*#define OB_PES_WRITE_PTR_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x31) // 0x1681 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x31) // 0x1681*/ /*#define OB_PES_WRITE_PTR_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x31) // 0x16d1 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x31) // 0x16d1*/ /* 15:0 DEMUX interrupt MASK*/ /* 11 -- PCR_READY*/ @@ -1017,14 +851,11 @@ /* 1 -- transport_error_indicator*/ /* 0 -- TS ERROR PIN*/ /*#define STB_INT_MASK - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x32) // 0x1632 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x32) // 0x1632*/ /*#define STB_INT_MASK_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x32) // 0x1682 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x32) // 0x1682*/ /*#define STB_INT_MASK_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x32) // 0x16d2 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x32) // 0x16d2*/ /* 31:16 VIDEO PID filter data*/ /*15 -- splicing VIDEO PID change enable*/ @@ -1033,14 +864,11 @@ /* 8 -- splicing active (Read Only)*/ /* 7:0 splicing countdown (Read Only)*/ /*#define VIDEO_SPLICING_CTL - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x33) // 0x1633 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x33) // 0x1633*/ /*#define VIDEO_SPLICING_CTL_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x33) // 0x1683 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x33) // 0x1683*/ /*#define VIDEO_SPLICING_CTL_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x33) // 0x16d3 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x33) // 0x16d3*/ /*----------- bit define -----------*/ #define VIDEO_PID_FILTER_DATA 16 #define VIDEO_SPLICING_PID_CHANGE_ENABLE 15 @@ -1056,14 +884,11 @@ /* 8 -- splicing active (Read Only)*/ /* 7:0 splicing countdown (Read Only)*/ /*#define AUDIO_SPLICING_CTL - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x34) // 0x1634 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x34) // 0x1634*/ /*#define AUDIO_SPLICING_CTL_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x34) // 0x1684 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x34) // 0x1684*/ /*#define AUDIO_SPLICING_CTL_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x34) // 0x16d4 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x34) // 0x16d4*/ /*----------- bit define -----------*/ #define AUDIO_PID_FILTER_DATA 16 #define AUDIO_SPLICING_PID_CHANGE_ENABLE 15 @@ -1075,54 +900,42 @@ /* 15:8 LAST TS PACKAGE BYTE COUNT (Read Only)*/ /* 7:0 PACKAGE BYTE COUNT (Read Only)*/ /*#define TS_PACKAGE_BYTE_COUNT - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x35) // 0x1635 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x35) // 0x1635*/ /*#define TS_PACKAGE_BYTE_COUNT_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x35) // 0x1685 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x35) // 0x1685*/ /*#define TS_PACKAGE_BYTE_COUNT_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x35) // 0x16d5 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x35) // 0x16d5*/ /*----------- bit define -----------*/ #define M2TS_SKIP_BYTES 16 #define LAST_TS_PACKAGE_BYTE_COUNT 8 /* 15:0 2 bytes strong sync add to PES*/ /*#define PES_STRONG_SYNC - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x36) // 0x1636 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x36) // 0x1636*/ /*#define PES_STRONG_SYNC_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x36) // 0x1686 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x36) // 0x1686*/ /*#define PES_STRONG_SYNC_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x36) // 0x16d6 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x36) // 0x16d6*/ /* bit 15 -- stb_om_ren*/ /* bit 14:11 -- reserved*/ /* bit 10:0 -- OM_DATA_RD_ADDR*/ /*#define OM_DATA_RD_ADDR - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x37) // 0x1637 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x37) // 0x1637*/ /*#define OM_DATA_RD_ADDR_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x37) // 0x1687 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x37) // 0x1687*/ /*#define OM_DATA_RD_ADDR_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x37) // 0x16d7 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x37) // 0x16d7*/ /*----------- bit define -----------*/ #define STB_OM_REN 15 /* bit 15:0 -- OM_DATA_RD*/ /*#define OM_DATA_RD - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x38) // 0x1638 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x38) // 0x1638*/ /*#define OM_DATA_RD_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x38) // 0x1688 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x38) // 0x1688*/ /*#define OM_DATA_RD_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x38) // 0x16d8 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x38) // 0x16d8*/ /* AUTO STOP SETTING for 32 channels*/ /* 4-bits per channel*/ @@ -1134,76 +947,55 @@ /* bit 2:0 -- count down to auto stop*/ /* section 31:24*/ /*#define SECTION_AUTO_STOP_3 - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x39) // 0x1639 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x39) // 0x1639*/ /*#define SECTION_AUTO_STOP_3_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x39) // 0x1689 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x39) // 0x1689*/ /*#define SECTION_AUTO_STOP_3_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x39) // 0x16d9 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x39) // 0x16d9*/ /* section 23:16*/ /*#define SECTION_AUTO_STOP_2 - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3a) // 0x163a - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3a) // 0x163a*/ /*#define SECTION_AUTO_STOP_2_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3a) // 0x168a - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3a) // 0x168a*/ /*#define SECTION_AUTO_STOP_2_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3a) // 0x16da - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3a) // 0x16da*/ /* section 15:8*/ /*#define SECTION_AUTO_STOP_1 - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3b) // 0x163b - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3b) // 0x163b*/ /*#define SECTION_AUTO_STOP_1_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3b) // 0x168b - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3b) // 0x168b*/ /*#define SECTION_AUTO_STOP_1_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3b) // 0x16db - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3b) // 0x16db*/ /* section 7:0*/ /*#define SECTION_AUTO_STOP_0 - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3c) // 0x163c - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3c) // 0x163c*/ /*#define SECTION_AUTO_STOP_0_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3c) // 0x168c - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3c) // 0x168c*/ /*#define SECTION_AUTO_STOP_0_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3c) // 0x16dc - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3c) // 0x16dc*/ /* bit 31:0 reset channel status - each bit reset each channel*/ /* read -- 32 channel status*/ /*#define DEMUX_CHANNEL_RESET - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3d) // 0x163d - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3d) // 0x163d*/ /*#define DEMUX_CHANNEL_RESET_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3d) // 0x168d - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3d) // 0x168d*/ /*#define DEMUX_CHANNEL_RESET_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3d) // 0x16dd - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3d) // 0x16dd*/ /*#define DEMUX_SCRAMBLING_STATE - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3e) // 0x163e - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3e) // 0x163e*/ /*#define DEMUX_SCRAMBLING_STATE_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3e) // 0x168e - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3e) // 0x168e*/ /*#define DEMUX_SCRAMBLING_STATE_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3e) // 0x16de - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3e) // 0x16de*/ /*#define DEMUX_CHANNEL_ACTIVITY - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3f) // 0x163f - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3f) // 0x163f*/ /*#define DEMUX_CHANNEL_ACTIVITY_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3f) // 0x168f - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3f) // 0x168f*/ /*#define DEMUX_CHANNEL_ACTIVITY_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3f) // 0x16df - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3f) // 0x16df*/ /* bit 4 -- video_stamp_use_dts*/ /* bit 3 -- audio_stamp_sync_1_en*/ @@ -1211,117 +1003,99 @@ /* bit 1 -- video_stamp_sync_1_en*/ /* bit 0 -- video_stamp_insert_en*/ /*#define DEMUX_STAMP_CTL - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x40) // 0x1640 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x40) // 0x1640*/ /*#define DEMUX_STAMP_CTL_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x40) // 0x1690 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x40) // 0x1690*/ /*#define DEMUX_STAMP_CTL_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x40) // 0x16e0 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x40) // 0x16e0*/ /*#define DEMUX_VIDEO_STAMP_SYNC_0 - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x41) // 0x1641 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x41) // 0x1641*/ /*#define DEMUX_VIDEO_STAMP_SYNC_0_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x41) // 0x1691 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x41) // 0x1691*/ /*#define DEMUX_VIDEO_STAMP_SYNC_0_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x41) // 0x16e1 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x41) // 0x16e1*/ /*#define DEMUX_VIDEO_STAMP_SYNC_1 - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x42) // 0x1642 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x42) // 0x1642*/ /*#define DEMUX_VIDEO_STAMP_SYNC_1_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x42) // 0x1692 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x42) // 0x1692*/ /*#define DEMUX_VIDEO_STAMP_SYNC_1_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x42) // 0x16e2 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x42) // 0x16e2*/ /*#define DEMUX_AUDIO_STAMP_SYNC_0 - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x43) // 0x1643 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x43) // 0x1643*/ /*#define DEMUX_AUDIO_STAMP_SYNC_0_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x43) // 0x1693 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x43) // 0x1693*/ /*#define DEMUX_AUDIO_STAMP_SYNC_0_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x43) // 0x16e3 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x43) // 0x16e3*/ /*#define DEMUX_AUDIO_STAMP_SYNC_1 - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x44) // 0x1644 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x44) // 0x1644*/ /*#define DEMUX_AUDIO_STAMP_SYNC_1_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x44) // 0x1694 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x44) // 0x1694*/ /*#define DEMUX_AUDIO_STAMP_SYNC_1_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x44) // 0x16e4 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x44) // 0x16e4*/ /* Write : Bit[4:0] secter filter number for reset*/ /* Read : select according to output_section_buffer_valid :*/ /* per bit per section buffer valid status*/ /* or section_buffer_ignore*/ /*#define DEMUX_SECTION_RESET - * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x45) // 0x1645 - */ + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x45) // 0x1645*/ /*#define DEMUX_SECTION_RESET_2 - * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x45) // 0x1695 - */ + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x45) // 0x1695*/ /*#define DEMUX_SECTION_RESET_3 - * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x45) // 0x16e5 - */ + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x45) // 0x16e5*/ /* bit[31:0] - channel_reset_timeout_disable*/ -#define DEMUX_INPUT_TIMEOUT_C \ - (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x46) /* 0x1646*/ -#define DEMUX_INPUT_TIMEOUT_C_2 \ - (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x46) /* 0x1696*/ -#define DEMUX_INPUT_TIMEOUT_C_3 \ - (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x46) /* 0x16e6*/ +/*#define DEMUX_INPUT_TIMEOUT_C \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x46) // 0x1646*/ +/*#define DEMUX_INPUT_TIMEOUT_C_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x46) // 0x1696*/ +/*#define DEMUX_INPUT_TIMEOUT_C_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x46) // 0x16e6*/ /* bit[31] - no_match_reset_timeout_disable*/ /* bit[30:0] input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-count*/ -#define DEMUX_INPUT_TIMEOUT \ - (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x47) /* 0x1647*/ -#define DEMUX_INPUT_TIMEOUT_2 \ - (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x47) /* 0x1697*/ -#define DEMUX_INPUT_TIMEOUT_3 \ - (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x47) /* 0x16e7*/ +/*#define DEMUX_INPUT_TIMEOUT \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x47) // 0x1647*/ +/*#define DEMUX_INPUT_TIMEOUT_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x47) // 0x1697*/ +/*#define DEMUX_INPUT_TIMEOUT_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x47) // 0x16e7*/ /* bit[31:0] - channel_packet_count_disable*/ -#define DEMUX_PACKET_COUNT_C \ - (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x48) /* 0x1648*/ -#define DEMUX_PACKET_COUNT_C_2 \ - (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x48) /* 0x1698*/ -#define DEMUX_PACKET_COUNT_C_3 \ - (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x48) /* 0x16e8*/ +/*#define DEMUX_PACKET_COUNT_C \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x48) // 0x1648*/ +/*#define DEMUX_PACKET_COUNT_C_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x48) // 0x1698*/ +/*#define DEMUX_PACKET_COUNT_C_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x48)*/ /* 0x16e8*/ /* bit[31] - no_match_packet_count_disable*/ /* bit[30:0] input_packet_count*/ -#define DEMUX_PACKET_COUNT \ - (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x49) /* 0x1649*/ -#define DEMUX_PACKET_COUNT_2 \ - (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x49) /* 0x1699*/ -#define DEMUX_PACKET_COUNT_3 \ - (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x49) /* 0x16e9*/ +/*#define DEMUX_PACKET_COUNT \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x49) // 0x1649*/ +/*#define DEMUX_PACKET_COUNT_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x49) // 0x1699*/ +/*#define DEMUX_PACKET_COUNT_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x49) // 0x16e9*/ /* bit[31:0] channel_record_enable*/ -#define DEMUX_CHAN_RECORD_EN \ - (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4a) /* 0x164a*/ -#define DEMUX_CHAN_RECORD_EN_2 \ - (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4a) /* 0x169a*/ -#define DEMUX_CHAN_RECORD_EN_3 \ - (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4a) /* 0x16ea*/ +/*#define DEMUX_CHAN_RECORD_EN \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4a) // 0x164a*/ +/*#define DEMUX_CHAN_RECORD_EN_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4a) // 0x169a*/ +/*#define DEMUX_CHAN_RECORD_EN_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4a) // 0x16ea*/ /* bit[31:0] channel_process_enable*/ -#define DEMUX_CHAN_PROCESS_EN \ - (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4b) /* 0x164b*/ -#define DEMUX_CHAN_PROCESS_EN_2 \ - (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4b) /* 0x169b*/ -#define DEMUX_CHAN_PROCESS_EN_3 \ - (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4b) /* 0x16eb*/ +/*#define DEMUX_CHAN_PROCESS_EN \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4b) // 0x164b*/ +/*#define DEMUX_CHAN_PROCESS_EN_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4b) */ /* 0x169b*/ +/*#define DEMUX_CHAN_PROCESS_EN_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4b) // 0x16eb*/ /* bit[31:24] small_sec_size ((n+1) * 256 Bytes)*/ /* bit[23:16] small_sec_rd_ptr */ @@ -1329,19 +1103,19 @@ /* bit[7:2] reserved*/ /* bit[1] small_sec_wr_ptr_wr_enable*/ /* bit[0] small_section_enable*/ -#define DEMUX_SMALL_SEC_CTL \ - (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4c) /* 0x164c*/ -#define DEMUX_SMALL_SEC_CTL_2 \ - (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4c) /* 0x169c*/ -#define DEMUX_SMALL_SEC_CTL_3 \ - (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4c) /* 0x16ec*/ +/*#define DEMUX_SMALL_SEC_CTL \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4c)*/ /* 0x164c*/ +/*#define DEMUX_SMALL_SEC_CTL_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4c) // 0x169c*/ +/*#define DEMUX_SMALL_SEC_CTL_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4c) // 0x16ec*/ /* bit[31:0] small_sec_start_addr*/ -#define DEMUX_SMALL_SEC_ADDR \ - (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4d) /* 0x164d*/ -#define DEMUX_SMALL_SEC_ADDR_2 \ - (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4d) /* 0x169d*/ -#define DEMUX_SMALL_SEC_ADDR_3 \ - (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4d) /* 0x16ed*/ +/*#define DEMUX_SMALL_SEC_ADDR \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4d) // 0x164d*/ +/*#define DEMUX_SMALL_SEC_ADDR_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4d) // 0x169d*/ +/*#define DEMUX_SMALL_SEC_ADDR_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4d) // 0x16ed*/ /*======================================================*/ diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_regs_define.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_regs_define.h index b0d4b791fd5d..5651ba7f5aa8 100644 --- a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_regs_define.h +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_regs_define.h @@ -1,8889 +1,769 @@ /* - * This file is automaticlly generated by genregs.awk. Please do not edit it + * This file is automaticly generated by genregs.awk. Please do not edit it * Base files are .. * .. * .. * Tue Oct 22 15:28:48 CST 2013 **/ + #ifndef __MACH_MESON8_REG_ADDR_H_ #define __MACH_MESON8_REG_ADDR_H_ #include #define CBUS_REG_ADDR(_r) aml_read_cbus(_r) -#define HHI_DEMOD_MEM_PD_REG (0xc883c000 + (0x43 << 2)) -#define STB_TOP_CONFIG 0x16f0 -#define P_STB_TOP_CONFIG CBUS_REG_ADDR(STB_TOP_CONFIG) -#define TS_TOP_CONFIG 0x16f1 -#define P_TS_TOP_CONFIG CBUS_REG_ADDR(TS_TOP_CONFIG) -#define TS_FILE_CONFIG 0x16f2 -#define P_TS_FILE_CONFIG CBUS_REG_ADDR(TS_FILE_CONFIG) -#define TS_PL_PID_INDEX 0x16f3 -#define P_TS_PL_PID_INDEX CBUS_REG_ADDR(TS_PL_PID_INDEX) -#define TS_PL_PID_DATA 0x16f4 -#define P_TS_PL_PID_DATA CBUS_REG_ADDR(TS_PL_PID_DATA) -#define COMM_DESC_KEY0 0x16f5 -#define P_COMM_DESC_KEY0 CBUS_REG_ADDR(COMM_DESC_KEY0) -#define COMM_DESC_KEY1 0x16f6 -#define P_COMM_DESC_KEY1 CBUS_REG_ADDR(COMM_DESC_KEY1) -#define COMM_DESC_KEY_RW 0x16f7 -#define P_COMM_DESC_KEY_RW CBUS_REG_ADDR(COMM_DESC_KEY_RW) -#define CIPLUS_KEY0 0x16f8 -#define P_CIPLUS_KEY0 CBUS_REG_ADDR(CIPLUS_KEY0) -#define CIPLUS_KEY1 0x16f9 -#define P_CIPLUS_KEY1 CBUS_REG_ADDR(CIPLUS_KEY1) -#define CIPLUS_KEY2 0x16fa -#define P_CIPLUS_KEY2 CBUS_REG_ADDR(CIPLUS_KEY2) -#define CIPLUS_KEY3 0x16fb -#define P_CIPLUS_KEY3 CBUS_REG_ADDR(CIPLUS_KEY3) -#define CIPLUS_KEY_WR 0x16fc -#define P_CIPLUS_KEY_WR CBUS_REG_ADDR(CIPLUS_KEY_WR) -#define CIPLUS_CONFIG 0x16fd -#define P_CIPLUS_CONFIG CBUS_REG_ADDR(CIPLUS_CONFIG) -#define CIPLUS_ENDIAN 0x16fe -#define P_CIPLUS_ENDIAN CBUS_REG_ADDR(CIPLUS_ENDIAN) -#define PREG_CTLREG0_ADDR 0x2000 -#define P_PREG_CTLREG0_ADDR CBUS_REG_ADDR(PREG_CTLREG0_ADDR) -#define PREG_PAD_GPIO6_EN_N 0x2008 -#define P_PREG_PAD_GPIO6_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO6_EN_N) -#define PREG_PAD_GPIO6_O 0x2009 -#define P_PREG_PAD_GPIO6_O CBUS_REG_ADDR(PREG_PAD_GPIO6_O) -#define PREG_PAD_GPIO6_I 0x200a -#define P_PREG_PAD_GPIO6_I CBUS_REG_ADDR(PREG_PAD_GPIO6_I) -#define PREG_JTAG_GPIO_ADDR 0x200b -#define P_PREG_JTAG_GPIO_ADDR CBUS_REG_ADDR(PREG_JTAG_GPIO_ADDR) -#define PREG_PAD_GPIO0_EN_N 0x200c -#define P_PREG_PAD_GPIO0_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO0_EN_N) -#define PREG_PAD_GPIO0_O 0x200d -#define P_PREG_PAD_GPIO0_O CBUS_REG_ADDR(PREG_PAD_GPIO0_O) -#define PREG_PAD_GPIO0_I 0x200e -#define P_PREG_PAD_GPIO0_I CBUS_REG_ADDR(PREG_PAD_GPIO0_I) -#define PREG_PAD_GPIO1_EN_N 0x200f -#define P_PREG_PAD_GPIO1_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO1_EN_N) -#define PREG_PAD_GPIO1_O 0x2010 -#define P_PREG_PAD_GPIO1_O CBUS_REG_ADDR(PREG_PAD_GPIO1_O) -#define PREG_PAD_GPIO1_I 0x2011 -#define P_PREG_PAD_GPIO1_I CBUS_REG_ADDR(PREG_PAD_GPIO1_I) -#define PREG_PAD_GPIO2_EN_N 0x2012 -#define P_PREG_PAD_GPIO2_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO2_EN_N) -#define PREG_PAD_GPIO2_O 0x2013 -#define P_PREG_PAD_GPIO2_O CBUS_REG_ADDR(PREG_PAD_GPIO2_O) -#define PREG_PAD_GPIO2_I 0x2014 -#define P_PREG_PAD_GPIO2_I CBUS_REG_ADDR(PREG_PAD_GPIO2_I) -#define PREG_PAD_GPIO3_EN_N 0x2015 -#define P_PREG_PAD_GPIO3_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO3_EN_N) -#define PREG_PAD_GPIO3_O 0x2016 -#define P_PREG_PAD_GPIO3_O CBUS_REG_ADDR(PREG_PAD_GPIO3_O) -#define PREG_PAD_GPIO3_I 0x2017 -#define P_PREG_PAD_GPIO3_I CBUS_REG_ADDR(PREG_PAD_GPIO3_I) -#define PREG_PAD_GPIO4_EN_N 0x2018 -#define P_PREG_PAD_GPIO4_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO4_EN_N) -#define PREG_PAD_GPIO4_O 0x2019 -#define P_PREG_PAD_GPIO4_O CBUS_REG_ADDR(PREG_PAD_GPIO4_O) -#define PREG_PAD_GPIO4_I 0x201a -#define P_PREG_PAD_GPIO4_I CBUS_REG_ADDR(PREG_PAD_GPIO4_I) -#define PREG_PAD_GPIO5_EN_N 0x201b -#define P_PREG_PAD_GPIO5_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO5_EN_N) -#define PREG_PAD_GPIO5_O 0x201c -#define P_PREG_PAD_GPIO5_O CBUS_REG_ADDR(PREG_PAD_GPIO5_O) -#define PREG_PAD_GPIO5_I 0x201d -#define P_PREG_PAD_GPIO5_I CBUS_REG_ADDR(PREG_PAD_GPIO5_I) -#define A9_STATUS1 0x201f -#define P_A9_STATUS1 CBUS_REG_ADDR(A9_STATUS1) -#define A9_CFG0 0x2020 -#define P_A9_CFG0 CBUS_REG_ADDR(A9_CFG0) -#define A9_CFG1 0x2021 -#define P_A9_CFG1 CBUS_REG_ADDR(A9_CFG1) -#define A9_CFG2 0x2022 -#define P_A9_CFG2 CBUS_REG_ADDR(A9_CFG2) -#define A9_PERIPH_BASE 0x2023 -#define P_A9_PERIPH_BASE CBUS_REG_ADDR(A9_PERIPH_BASE) -#define A9_L2_REG_BASE 0x2024 -#define P_A9_L2_REG_BASE CBUS_REG_ADDR(A9_L2_REG_BASE) -#define A9_L2_STATUS 0x2025 -#define P_A9_L2_STATUS CBUS_REG_ADDR(A9_L2_STATUS) -#define A9_POR_CFG 0x2026 -#define P_A9_POR_CFG CBUS_REG_ADDR(A9_POR_CFG) -#define A9_STATUS2 0x2027 -#define P_A9_STATUS2 CBUS_REG_ADDR(A9_STATUS2) -#define AXI_REG_EN 0x2028 -#define P_AXI_REG_EN CBUS_REG_ADDR(AXI_REG_EN) -#define A9_CFG3 0x2029 -#define P_A9_CFG3 CBUS_REG_ADDR(A9_CFG3) -#define A9_CFG4 0x202a -#define P_A9_CFG4 CBUS_REG_ADDR(A9_CFG4) -#define A9_STATUS3 0x202b -#define P_A9_STATUS3 CBUS_REG_ADDR(A9_STATUS3) -#define PERIPHS_PIN_MUX_0 0x202c -#define P_PERIPHS_PIN_MUX_0 CBUS_REG_ADDR(PERIPHS_PIN_MUX_0) -#define PERIPHS_PIN_MUX_1 0x202d -#define P_PERIPHS_PIN_MUX_1 CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) -#define PERIPHS_PIN_MUX_2 0x202e -#define P_PERIPHS_PIN_MUX_2 CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) -#define PERIPHS_PIN_MUX_3 0x202f -#define P_PERIPHS_PIN_MUX_3 CBUS_REG_ADDR(PERIPHS_PIN_MUX_3) -#define PERIPHS_PIN_MUX_4 0x2030 -#define P_PERIPHS_PIN_MUX_4 CBUS_REG_ADDR(PERIPHS_PIN_MUX_4) -#define PERIPHS_PIN_MUX_5 0x2031 -#define P_PERIPHS_PIN_MUX_5 CBUS_REG_ADDR(PERIPHS_PIN_MUX_5) -#define PERIPHS_PIN_MUX_6 0x2032 -#define P_PERIPHS_PIN_MUX_6 CBUS_REG_ADDR(PERIPHS_PIN_MUX_6) -#define PERIPHS_PIN_MUX_7 0x2033 -#define P_PERIPHS_PIN_MUX_7 CBUS_REG_ADDR(PERIPHS_PIN_MUX_7) -#define PERIPHS_PIN_MUX_8 0x2034 -#define P_PERIPHS_PIN_MUX_8 CBUS_REG_ADDR(PERIPHS_PIN_MUX_8) -#define PERIPHS_PIN_MUX_9 0x2035 -#define P_PERIPHS_PIN_MUX_9 CBUS_REG_ADDR(PERIPHS_PIN_MUX_9) -#define PERIPHS_PIN_MUX_10 0x2036 -#define P_PERIPHS_PIN_MUX_10 CBUS_REG_ADDR(PERIPHS_PIN_MUX_10) -#define PERIPHS_PIN_MUX_11 0x2037 -#define P_PERIPHS_PIN_MUX_11 CBUS_REG_ADDR(PERIPHS_PIN_MUX_11) -#define PERIPHS_PIN_MUX_12 0x2038 -#define P_PERIPHS_PIN_MUX_12 CBUS_REG_ADDR(PERIPHS_PIN_MUX_12) -#define PAD_PULL_UP_REG6 0x2039 -#define P_PAD_PULL_UP_REG6 CBUS_REG_ADDR(PAD_PULL_UP_REG6) -#define PAD_PULL_UP_REG0 0x203a -#define P_PAD_PULL_UP_REG0 CBUS_REG_ADDR(PAD_PULL_UP_REG0) -#define PAD_PULL_UP_REG1 0x203b -#define P_PAD_PULL_UP_REG1 CBUS_REG_ADDR(PAD_PULL_UP_REG1) -#define PAD_PULL_UP_REG2 0x203c -#define P_PAD_PULL_UP_REG2 CBUS_REG_ADDR(PAD_PULL_UP_REG2) -#define PAD_PULL_UP_REG3 0x203d -#define P_PAD_PULL_UP_REG3 CBUS_REG_ADDR(PAD_PULL_UP_REG3) -#define PAD_PULL_UP_REG4 0x203e -#define P_PAD_PULL_UP_REG4 CBUS_REG_ADDR(PAD_PULL_UP_REG4) -#define PAD_PULL_UP_REG5 0x203f -#define P_PAD_PULL_UP_REG5 CBUS_REG_ADDR(PAD_PULL_UP_REG5) -#define RAND64_ADDR0 0x2040 -#define P_RAND64_ADDR0 CBUS_REG_ADDR(RAND64_ADDR0) -#define RAND64_ADDR1 0x2041 -#define P_RAND64_ADDR1 CBUS_REG_ADDR(RAND64_ADDR1) -#define PREG_ETHERNET_ADDR0 0x2042 -#define P_PREG_ETHERNET_ADDR0 CBUS_REG_ADDR(PREG_ETHERNET_ADDR0) -#define PREG_AM_ANALOG_ADDR 0x2043 -#define P_PREG_AM_ANALOG_ADDR CBUS_REG_ADDR(PREG_AM_ANALOG_ADDR) -#define PREG_MALI_BYTE_CNTL 0x2044 -#define P_PREG_MALI_BYTE_CNTL CBUS_REG_ADDR(PREG_MALI_BYTE_CNTL) -#define PREG_WIFI_CNTL 0x2045 -#define P_PREG_WIFI_CNTL CBUS_REG_ADDR(PREG_WIFI_CNTL) -#define PAD_PULL_UP_EN_REG0 0x2048 -#define P_PAD_PULL_UP_EN_REG0 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG0) -#define PAD_PULL_UP_EN_REG1 0x2049 -#define P_PAD_PULL_UP_EN_REG1 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG1) -#define PAD_PULL_UP_EN_REG2 0x204a -#define P_PAD_PULL_UP_EN_REG2 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG2) -#define PAD_PULL_UP_EN_REG3 0x204b -#define P_PAD_PULL_UP_EN_REG3 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG3) -#define PAD_PULL_UP_EN_REG4 0x204c -#define P_PAD_PULL_UP_EN_REG4 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG4) -#define PAD_PULL_UP_EN_REG5 0x204d -#define P_PAD_PULL_UP_EN_REG5 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG5) -#define PAD_PULL_UP_EN_REG6 0x204e -#define P_PAD_PULL_UP_EN_REG6 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG6) -/* add from M8M2*/ -#define PREG_ETH_REG0 0x2050 -#define P_PREG_ETH_REG0 CBUS_REG_ADDR(PREG_ETH_REG0) -#define PREG_ETH_REG1 0x2051 -#define P_PREG_ETH_REG1 CBUS_REG_ADDR(PREG_ETH_REG1) -/***************/ -#define PROD_TEST_REG0 0x2068 -#define P_PROD_TEST_REG0 CBUS_REG_ADDR(PROD_TEST_REG0) -#define PROD_TEST_REG1 0x2067 -#define P_PROD_TEST_REG1 CBUS_REG_ADDR(PROD_TEST_REG1) -#define METAL_REVISION 0x206a -#define P_METAL_REVISION CBUS_REG_ADDR(METAL_REVISION) -#define ADC_TOP_MISC 0x206b -#define P_ADC_TOP_MISC CBUS_REG_ADDR(ADC_TOP_MISC) -#define DPLL_TOP_MISC 0x206c -#define P_DPLL_TOP_MISC CBUS_REG_ADDR(DPLL_TOP_MISC) -#define ANALOG_TOP_MISC 0x206d -#define P_ANALOG_TOP_MISC CBUS_REG_ADDR(ANALOG_TOP_MISC) -#define AM_ANALOG_TOP_REG0 0x206e -#define P_AM_ANALOG_TOP_REG0 CBUS_REG_ADDR(AM_ANALOG_TOP_REG0) -#define AM_ANALOG_TOP_REG1 0x206f -#define P_AM_ANALOG_TOP_REG1 CBUS_REG_ADDR(AM_ANALOG_TOP_REG1) -#define PREG_STICKY_REG0 0x207c -#define P_PREG_STICKY_REG0 CBUS_REG_ADDR(PREG_STICKY_REG0) -#define PREG_STICKY_REG1 0x207d -#define P_PREG_STICKY_REG1 CBUS_REG_ADDR(PREG_STICKY_REG1) -#define PREG_WRITE_ONCE_REG 0x207e -#define P_PREG_WRITE_ONCE_REG CBUS_REG_ADDR(PREG_WRITE_ONCE_REG) -#define AM_RING_OSC_REG0 0x207f -#define P_AM_RING_OSC_REG0 CBUS_REG_ADDR(AM_RING_OSC_REG0) -#define SMARTCARD_REG0 0x2110 -#define P_SMARTCARD_REG0 CBUS_REG_ADDR(SMARTCARD_REG0) -#define SMARTCARD_REG1 0x2111 -#define P_SMARTCARD_REG1 CBUS_REG_ADDR(SMARTCARD_REG1) -#define SMARTCARD_REG2 0x2112 -#define P_SMARTCARD_REG2 CBUS_REG_ADDR(SMARTCARD_REG2) -#define SMARTCARD_STATUS 0x2113 -#define P_SMARTCARD_STATUS CBUS_REG_ADDR(SMARTCARD_STATUS) -#define SMARTCARD_INTR 0x2114 -#define P_SMARTCARD_INTR CBUS_REG_ADDR(SMARTCARD_INTR) -#define SMARTCARD_REG5 0x2115 -#define P_SMARTCARD_REG5 CBUS_REG_ADDR(SMARTCARD_REG5) -#define SMARTCARD_REG6 0x2116 -#define P_SMARTCARD_REG6 CBUS_REG_ADDR(SMARTCARD_REG6) -#define SMARTCARD_FIFO 0x2117 -#define P_SMARTCARD_FIFO CBUS_REG_ADDR(SMARTCARD_FIFO) -#define SMARTCARD_REG8 0x2118 -#define P_SMARTCARD_REG8 CBUS_REG_ADDR(SMARTCARD_REG8) -#define IR_DEC_LDR_ACTIVE 0x2120 -#define P_IR_DEC_LDR_ACTIVE CBUS_REG_ADDR(IR_DEC_LDR_ACTIVE) -#define IR_DEC_LDR_IDLE 0x2121 -#define P_IR_DEC_LDR_IDLE CBUS_REG_ADDR(IR_DEC_LDR_IDLE) -#define IR_DEC_LDR_REPEAT 0x2122 -#define P_IR_DEC_LDR_REPEAT CBUS_REG_ADDR(IR_DEC_LDR_REPEAT) -#define IR_DEC_BIT_0 0x2123 -#define P_IR_DEC_BIT_0 CBUS_REG_ADDR(IR_DEC_BIT_0) -#define IR_DEC_REG0 0x2124 -#define P_IR_DEC_REG0 CBUS_REG_ADDR(IR_DEC_REG0) -#define IR_DEC_FRAME 0x2125 -#define P_IR_DEC_FRAME CBUS_REG_ADDR(IR_DEC_FRAME) -#define IR_DEC_STATUS 0x2126 -#define P_IR_DEC_STATUS CBUS_REG_ADDR(IR_DEC_STATUS) -#define IR_DEC_REG1 0x2127 -#define P_IR_DEC_REG1 CBUS_REG_ADDR(IR_DEC_REG1) -#define DEMOD_ADC_SAMPLING 0x212d -#define P_DEMOD_ADC_SAMPLING CBUS_REG_ADDR(DEMOD_ADC_SAMPLING) -#define UART0_WFIFO 0x2130 -#define P_UART0_WFIFO CBUS_REG_ADDR(UART0_WFIFO) -#define UART0_RFIFO 0x2131 -#define P_UART0_RFIFO CBUS_REG_ADDR(UART0_RFIFO) -#define UART0_CONTROL 0x2132 -#define P_UART0_CONTROL CBUS_REG_ADDR(UART0_CONTROL) -#define UART0_STATUS 0x2133 -#define P_UART0_STATUS CBUS_REG_ADDR(UART0_STATUS) -#define UART0_MISC 0x2134 -#define P_UART0_MISC CBUS_REG_ADDR(UART0_MISC) -#define UART0_REG5 0x2135 -#define P_UART0_REG5 CBUS_REG_ADDR(UART0_REG5) -#define UART1_WFIFO 0x2137 -#define P_UART1_WFIFO CBUS_REG_ADDR(UART1_WFIFO) -#define UART1_RFIFO 0x2138 -#define P_UART1_RFIFO CBUS_REG_ADDR(UART1_RFIFO) -#define UART1_CONTROL 0x2139 -#define P_UART1_CONTROL CBUS_REG_ADDR(UART1_CONTROL) -#define UART1_STATUS 0x213a -#define P_UART1_STATUS CBUS_REG_ADDR(UART1_STATUS) -#define UART1_MISC 0x213b -#define P_UART1_MISC CBUS_REG_ADDR(UART1_MISC) -#define UART1_REG5 0x213c -#define P_UART1_REG5 CBUS_REG_ADDR(UART1_REG5) -#define I2C_M_0_CONTROL_REG 0x2140 -#define P_I2C_M_0_CONTROL_REG CBUS_REG_ADDR(I2C_M_0_CONTROL_REG) -#define I2C_M_0_SLAVE_ADDR 0x2141 -#define P_I2C_M_0_SLAVE_ADDR CBUS_REG_ADDR(I2C_M_0_SLAVE_ADDR) -#define I2C_M_0_TOKEN_LIST0 0x2142 -#define P_I2C_M_0_TOKEN_LIST0 CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST0) -#define I2C_M_0_TOKEN_LIST1 0x2143 -#define P_I2C_M_0_TOKEN_LIST1 CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST1) -#define I2C_M_0_WDATA_REG0 0x2144 -#define P_I2C_M_0_WDATA_REG0 CBUS_REG_ADDR(I2C_M_0_WDATA_REG0) -#define I2C_M_0_WDATA_REG1 0x2145 -#define P_I2C_M_0_WDATA_REG1 CBUS_REG_ADDR(I2C_M_0_WDATA_REG1) -#define I2C_M_0_RDATA_REG0 0x2146 -#define P_I2C_M_0_RDATA_REG0 CBUS_REG_ADDR(I2C_M_0_RDATA_REG0) -#define I2C_M_0_RDATA_REG1 0x2147 -#define P_I2C_M_0_RDATA_REG1 CBUS_REG_ADDR(I2C_M_0_RDATA_REG1) -#define I2C_S_CONTROL_REG 0x2150 -#define P_I2C_S_CONTROL_REG CBUS_REG_ADDR(I2C_S_CONTROL_REG) -#define I2C_S_SEND_REG 0x2151 -#define P_I2C_S_SEND_REG CBUS_REG_ADDR(I2C_S_SEND_REG) -#define I2C_S_RECV_REG 0x2152 -#define P_I2C_S_RECV_REG CBUS_REG_ADDR(I2C_S_RECV_REG) -#define I2C_S_CNTL1_REG 0x2153 -#define P_I2C_S_CNTL1_REG CBUS_REG_ADDR(I2C_S_CNTL1_REG) -#define PWM_PWM_A 0x2154 -#define P_PWM_PWM_A CBUS_REG_ADDR(PWM_PWM_A) -#define PWM_PWM_B 0x2155 -#define P_PWM_PWM_B CBUS_REG_ADDR(PWM_PWM_B) -#define PWM_MISC_REG_AB 0x2156 -#define P_PWM_MISC_REG_AB CBUS_REG_ADDR(PWM_MISC_REG_AB) -#define PWM_DELTA_SIGMA_AB 0x2157 -#define P_PWM_DELTA_SIGMA_AB CBUS_REG_ADDR(PWM_DELTA_SIGMA_AB) -#define ATAPI_IDEREG0 0x2160 -#define P_ATAPI_IDEREG0 CBUS_REG_ADDR(ATAPI_IDEREG0) -#define ATAPI_IDEREG1 0x2161 -#define P_ATAPI_IDEREG1 CBUS_REG_ADDR(ATAPI_IDEREG1) -#define ATAPI_IDEREG2 0x2162 -#define P_ATAPI_IDEREG2 CBUS_REG_ADDR(ATAPI_IDEREG2) -#define ATAPI_CYCTIME 0x2163 -#define P_ATAPI_CYCTIME CBUS_REG_ADDR(ATAPI_CYCTIME) -#define ATAPI_IDETIME 0x2164 -#define P_ATAPI_IDETIME CBUS_REG_ADDR(ATAPI_IDETIME) -#define ATAPI_PIO_TIMING 0x2165 -#define P_ATAPI_PIO_TIMING CBUS_REG_ADDR(ATAPI_PIO_TIMING) -#define ATAPI_TABLE_ADD_REG 0x2166 -#define P_ATAPI_TABLE_ADD_REG CBUS_REG_ADDR(ATAPI_TABLE_ADD_REG) -#define ATAPI_IDEREG3 0x2167 -#define P_ATAPI_IDEREG3 CBUS_REG_ADDR(ATAPI_IDEREG3) -#define ATAPI_UDMA_REG0 0x2168 -#define P_ATAPI_UDMA_REG0 CBUS_REG_ADDR(ATAPI_UDMA_REG0) -#define ATAPI_UDMA_REG1 0x2169 -#define P_ATAPI_UDMA_REG1 CBUS_REG_ADDR(ATAPI_UDMA_REG1) -#define TRANS_PWMA_REG0 0x2170 -#define P_TRANS_PWMA_REG0 CBUS_REG_ADDR(TRANS_PWMA_REG0) -#define TRANS_PWMA_REG1 0x2171 -#define P_TRANS_PWMA_REG1 CBUS_REG_ADDR(TRANS_PWMA_REG1) -#define TRANS_PWMA_MUX0 0x2172 -#define P_TRANS_PWMA_MUX0 CBUS_REG_ADDR(TRANS_PWMA_MUX0) -#define TRANS_PWMA_MUX1 0x2173 -#define P_TRANS_PWMA_MUX1 CBUS_REG_ADDR(TRANS_PWMA_MUX1) -#define TRANS_PWMA_MUX2 0x2174 -#define P_TRANS_PWMA_MUX2 CBUS_REG_ADDR(TRANS_PWMA_MUX2) -#define TRANS_PWMA_MUX3 0x2175 -#define P_TRANS_PWMA_MUX3 CBUS_REG_ADDR(TRANS_PWMA_MUX3) -#define TRANS_PWMA_MUX4 0x2176 -#define P_TRANS_PWMA_MUX4 CBUS_REG_ADDR(TRANS_PWMA_MUX4) -#define TRANS_PWMA_MUX5 0x2177 -#define P_TRANS_PWMA_MUX5 CBUS_REG_ADDR(TRANS_PWMA_MUX5) -#define TRANS_PWMB_REG0 0x2178 -#define P_TRANS_PWMB_REG0 CBUS_REG_ADDR(TRANS_PWMB_REG0) -#define TRANS_PWMB_REG1 0x2179 -#define P_TRANS_PWMB_REG1 CBUS_REG_ADDR(TRANS_PWMB_REG1) -#define TRANS_PWMB_MUX0 0x217a -#define P_TRANS_PWMB_MUX0 CBUS_REG_ADDR(TRANS_PWMB_MUX0) -#define TRANS_PWMB_MUX1 0x217b -#define P_TRANS_PWMB_MUX1 CBUS_REG_ADDR(TRANS_PWMB_MUX1) -#define TRANS_PWMB_MUX2 0x217c -#define P_TRANS_PWMB_MUX2 CBUS_REG_ADDR(TRANS_PWMB_MUX2) -#define TRANS_PWMB_MUX3 0x217d -#define P_TRANS_PWMB_MUX3 CBUS_REG_ADDR(TRANS_PWMB_MUX3) -#define TRANS_PWMB_MUX4 0x217e -#define P_TRANS_PWMB_MUX4 CBUS_REG_ADDR(TRANS_PWMB_MUX4) -#define TRANS_PWMB_MUX5 0x217f -#define P_TRANS_PWMB_MUX5 CBUS_REG_ADDR(TRANS_PWMB_MUX5) -#define NAND_START 0x2180 -#define P_NAND_START CBUS_REG_ADDR(NAND_START) -#define NAND_ADR_CMD 0x218a -#define P_NAND_ADR_CMD CBUS_REG_ADDR(NAND_ADR_CMD) -#define NAND_ADR_STS 0x218b -#define P_NAND_ADR_STS CBUS_REG_ADDR(NAND_ADR_STS) -#define NAND_END 0x218f -#define P_NAND_END CBUS_REG_ADDR(NAND_END) -#define PWM_PWM_C 0x2194 -#define P_PWM_PWM_C CBUS_REG_ADDR(PWM_PWM_C) -#define PWM_PWM_D 0x2195 -#define P_PWM_PWM_D CBUS_REG_ADDR(PWM_PWM_D) -#define PWM_MISC_REG_CD 0x2196 -#define P_PWM_MISC_REG_CD CBUS_REG_ADDR(PWM_MISC_REG_CD) -#define PWM_DELTA_SIGMA_CD 0x2197 -#define P_PWM_DELTA_SIGMA_CD CBUS_REG_ADDR(PWM_DELTA_SIGMA_CD) -#define ISP_LED_CTRL 0x2198 -#define P_ISP_LED_CTRL CBUS_REG_ADDR(ISP_LED_CTRL) -#define ISP_LED_TIMING1 0x2199 -#define P_ISP_LED_TIMING1 CBUS_REG_ADDR(ISP_LED_TIMING1) -#define ISP_LED_TIMING2 0x219a -#define P_ISP_LED_TIMING2 CBUS_REG_ADDR(ISP_LED_TIMING2) -#define ISP_LED_TIMING3 0x219b -#define P_ISP_LED_TIMING3 CBUS_REG_ADDR(ISP_LED_TIMING3) -#define ISP_LED_TIMING4 0x219c -#define P_ISP_LED_TIMING4 CBUS_REG_ADDR(ISP_LED_TIMING4) -#define ISP_LED_TIMING5 0x219d -#define P_ISP_LED_TIMING5 CBUS_REG_ADDR(ISP_LED_TIMING5) -#define ISP_LED_TIMING6 0x219e -#define P_ISP_LED_TIMING6 CBUS_REG_ADDR(ISP_LED_TIMING6) -#define SAR_ADC_REG0 0x21a0 -#define P_SAR_ADC_REG0 CBUS_REG_ADDR(SAR_ADC_REG0) -#define SAR_ADC_CHAN_LIST 0x21a1 -#define P_SAR_ADC_CHAN_LIST CBUS_REG_ADDR(SAR_ADC_CHAN_LIST) -#define SAR_ADC_AVG_CNTL 0x21a2 -#define P_SAR_ADC_AVG_CNTL CBUS_REG_ADDR(SAR_ADC_AVG_CNTL) -#define SAR_ADC_REG3 0x21a3 -#define P_SAR_ADC_REG3 CBUS_REG_ADDR(SAR_ADC_REG3) -#define SAR_ADC_DELAY 0x21a4 -#define P_SAR_ADC_DELAY CBUS_REG_ADDR(SAR_ADC_DELAY) -#define SAR_ADC_LAST_RD 0x21a5 -#define P_SAR_ADC_LAST_RD CBUS_REG_ADDR(SAR_ADC_LAST_RD) -#define SAR_ADC_FIFO_RD 0x21a6 -#define P_SAR_ADC_FIFO_RD CBUS_REG_ADDR(SAR_ADC_FIFO_RD) -#define SAR_ADC_AUX_SW 0x21a7 -#define P_SAR_ADC_AUX_SW CBUS_REG_ADDR(SAR_ADC_AUX_SW) -#define SAR_ADC_CHAN_10_SW 0x21a8 -#define P_SAR_ADC_CHAN_10_SW CBUS_REG_ADDR(SAR_ADC_CHAN_10_SW) -#define SAR_ADC_DETECT_IDLE_SW 0x21a9 -#define P_SAR_ADC_DETECT_IDLE_SW \ - CBUS_REG_ADDR(SAR_ADC_DETECT_IDLE_SW) -#define SAR_ADC_DELTA_10 0x21aa -#define P_SAR_ADC_DELTA_10 CBUS_REG_ADDR(SAR_ADC_DELTA_10) -#define PWM_PWM_E 0x21b0 -#define P_PWM_PWM_E CBUS_REG_ADDR(PWM_PWM_E) -#define PWM_PWM_F 0x21b1 -#define P_PWM_PWM_F CBUS_REG_ADDR(PWM_PWM_F) -#define PWM_MISC_REG_EF 0x21b2 -#define P_PWM_MISC_REG_EF CBUS_REG_ADDR(PWM_MISC_REG_EF) -#define PWM_DELTA_SIGMA_EF 0x21b3 -#define P_PWM_DELTA_SIGMA_EF CBUS_REG_ADDR(PWM_DELTA_SIGMA_EF) -#define UART2_WFIFO 0x21c0 -#define P_UART2_WFIFO CBUS_REG_ADDR(UART2_WFIFO) -#define UART2_RFIFO 0x21c1 -#define P_UART2_RFIFO CBUS_REG_ADDR(UART2_RFIFO) -#define UART2_CONTROL 0x21c2 -#define P_UART2_CONTROL CBUS_REG_ADDR(UART2_CONTROL) -#define UART2_STATUS 0x21c3 -#define P_UART2_STATUS CBUS_REG_ADDR(UART2_STATUS) -#define UART2_MISC 0x21c4 -#define P_UART2_MISC CBUS_REG_ADDR(UART2_MISC) -#define UART2_REG5 0x21c5 -#define P_UART2_REG5 CBUS_REG_ADDR(UART2_REG5) -#define UART3_WFIFO 0x21c8 -#define P_UART3_WFIFO CBUS_REG_ADDR(UART3_WFIFO) -#define UART3_RFIFO 0x21c9 -#define P_UART3_RFIFO CBUS_REG_ADDR(UART3_RFIFO) -#define UART3_CONTROL 0x21ca -#define P_UART3_CONTROL CBUS_REG_ADDR(UART3_CONTROL) -#define UART3_STATUS 0x21cb -#define P_UART3_STATUS CBUS_REG_ADDR(UART3_STATUS) -#define UART3_MISC 0x21cc -#define P_UART3_MISC CBUS_REG_ADDR(UART3_MISC) -#define UART3_REG5 0x21cd -#define P_UART3_REG5 CBUS_REG_ADDR(UART3_REG5) -#define RTC_ADDR0 0x21d0 -#define P_RTC_ADDR0 CBUS_REG_ADDR(RTC_ADDR0) -#define RTC_ADDR1 0x21d1 -#define P_RTC_ADDR1 CBUS_REG_ADDR(RTC_ADDR1) -#define RTC_ADDR2 0x21d2 -#define P_RTC_ADDR2 CBUS_REG_ADDR(RTC_ADDR2) -#define RTC_ADDR3 0x21d3 -#define P_RTC_ADDR3 CBUS_REG_ADDR(RTC_ADDR3) -#define RTC_ADDR4 0x21d4 -#define P_RTC_ADDR4 CBUS_REG_ADDR(RTC_ADDR4) -#define MSR_CLK_DUTY 0x21d6 -#define P_MSR_CLK_DUTY CBUS_REG_ADDR(MSR_CLK_DUTY) -#define MSR_CLK_REG0 0x21d7 -#define P_MSR_CLK_REG0 CBUS_REG_ADDR(MSR_CLK_REG0) -#define MSR_CLK_REG1 0x21d8 -#define P_MSR_CLK_REG1 CBUS_REG_ADDR(MSR_CLK_REG1) -#define MSR_CLK_REG2 0x21d9 -#define P_MSR_CLK_REG2 CBUS_REG_ADDR(MSR_CLK_REG2) -/*add from M8M2*/ -#define MSR_CLK_REG3 0x21da -#define P_MSR_CLK_REG3 CBUS_REG_ADDR(MSR_CLK_REG3) -#define MSR_CLK_REG4 0x21db -#define P_MSR_CLK_REG4 CBUS_REG_ADDR(MSR_CLK_REG4) -#define MSR_CLK_REG5 0x21de -#define P_MSR_CLK_REG5 CBUS_REG_ADDR(MSR_CLK_REG5) -/**/ -/* - * #define LED_PWM_REG0 0x21da - * #define P_LED_PWM_REG0 CBUS_REG_ADDR(LED_PWM_REG0) - * #define LED_PWM_REG1 0x21db - * #define P_LED_PWM_REG1 CBUS_REG_ADDR(LED_PWM_REG1) - * #define LED_PWM_REG2 0x21dc - * #define P_LED_PWM_REG2 CBUS_REG_ADDR(LED_PWM_REG2) - * #define LED_PWM_REG3 0x21dd - * #define P_LED_PWM_REG3 CBUS_REG_ADDR(LED_PWM_REG3) - * #define LED_PWM_REG4 0x21de - * #define P_LED_PWM_REG4 CBUS_REG_ADDR(LED_PWM_REG4) - * #define LED_PWM_REG5 0x21df - * #define P_LED_PWM_REG5 CBUS_REG_ADDR(LED_PWM_REG5) - * #define LED_PWM_REG6 0x21e0 - * #define P_LED_PWM_REG6 CBUS_REG_ADDR(LED_PWM_REG6) - */ -#define VGHL_PWM_REG0 0x21e1 -#define P_VGHL_PWM_REG0 CBUS_REG_ADDR(VGHL_PWM_REG0) -#define VGHL_PWM_REG1 0x21e2 -#define P_VGHL_PWM_REG1 CBUS_REG_ADDR(VGHL_PWM_REG1) -#define VGHL_PWM_REG2 0x21e3 -#define P_VGHL_PWM_REG2 CBUS_REG_ADDR(VGHL_PWM_REG2) -#define VGHL_PWM_REG3 0x21e4 -#define P_VGHL_PWM_REG3 CBUS_REG_ADDR(VGHL_PWM_REG3) -#define VGHL_PWM_REG4 0x21e5 -#define P_VGHL_PWM_REG4 CBUS_REG_ADDR(VGHL_PWM_REG4) -#define VGHL_PWM_REG5 0x21e6 -#define P_VGHL_PWM_REG5 CBUS_REG_ADDR(VGHL_PWM_REG5) -#define VGHL_PWM_REG6 0x21e7 -#define P_VGHL_PWM_REG6 CBUS_REG_ADDR(VGHL_PWM_REG6) -#define I2C_M_1_CONTROL_REG 0x21f0 -#define P_I2C_M_1_CONTROL_REG CBUS_REG_ADDR(I2C_M_1_CONTROL_REG) -#define I2C_M_1_SLAVE_ADDR 0x21f1 -#define P_I2C_M_1_SLAVE_ADDR CBUS_REG_ADDR(I2C_M_1_SLAVE_ADDR) -#define I2C_M_1_TOKEN_LIST0 0x21f2 -#define P_I2C_M_1_TOKEN_LIST0 CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST0) -#define I2C_M_1_TOKEN_LIST1 0x21f3 -#define P_I2C_M_1_TOKEN_LIST1 CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST1) -#define I2C_M_1_WDATA_REG0 0x21f4 -#define P_I2C_M_1_WDATA_REG0 CBUS_REG_ADDR(I2C_M_1_WDATA_REG0) -#define I2C_M_1_WDATA_REG1 0x21f5 -#define P_I2C_M_1_WDATA_REG1 CBUS_REG_ADDR(I2C_M_1_WDATA_REG1) -#define I2C_M_1_RDATA_REG0 0x21f6 -#define P_I2C_M_1_RDATA_REG0 CBUS_REG_ADDR(I2C_M_1_RDATA_REG0) -#define I2C_M_1_RDATA_REG1 0x21f7 -#define P_I2C_M_1_RDATA_REG1 CBUS_REG_ADDR(I2C_M_1_RDATA_REG1) -#define I2C_M_2_CONTROL_REG 0x21f8 -#define P_I2C_M_2_CONTROL_REG CBUS_REG_ADDR(I2C_M_2_CONTROL_REG) -#define I2C_M_2_SLAVE_ADDR 0x21f9 -#define P_I2C_M_2_SLAVE_ADDR CBUS_REG_ADDR(I2C_M_2_SLAVE_ADDR) -#define I2C_M_2_TOKEN_LIST0 0x21fa -#define P_I2C_M_2_TOKEN_LIST0 CBUS_REG_ADDR(I2C_M_2_TOKEN_LIST0) -#define I2C_M_2_TOKEN_LIST1 0x21fb -#define P_I2C_M_2_TOKEN_LIST1 CBUS_REG_ADDR(I2C_M_2_TOKEN_LIST1) -#define I2C_M_2_WDATA_REG0 0x21fc -#define P_I2C_M_2_WDATA_REG0 CBUS_REG_ADDR(I2C_M_2_WDATA_REG0) -#define I2C_M_2_WDATA_REG1 0x21fd -#define P_I2C_M_2_WDATA_REG1 CBUS_REG_ADDR(I2C_M_2_WDATA_REG1) -#define I2C_M_2_RDATA_REG0 0x21fe -#define P_I2C_M_2_RDATA_REG0 CBUS_REG_ADDR(I2C_M_2_RDATA_REG0) -#define I2C_M_2_RDATA_REG1 0x21ff -#define P_I2C_M_2_RDATA_REG1 CBUS_REG_ADDR(I2C_M_2_RDATA_REG1) -#define USB_ADDR0 0x2200 -#define P_USB_ADDR0 CBUS_REG_ADDR(USB_ADDR0) -#define USB_ADDR1 0x2201 -#define P_USB_ADDR1 CBUS_REG_ADDR(USB_ADDR1) -#define USB_ADDR2 0x2202 -#define P_USB_ADDR2 CBUS_REG_ADDR(USB_ADDR2) -#define USB_ADDR3 0x2203 -#define P_USB_ADDR3 CBUS_REG_ADDR(USB_ADDR3) -#define USB_ADDR4 0x2204 -#define P_USB_ADDR4 CBUS_REG_ADDR(USB_ADDR4) -#define USB_ADDR5 0x2205 -#define P_USB_ADDR5 CBUS_REG_ADDR(USB_ADDR5) -#define USB_ADDR6 0x2206 -#define P_USB_ADDR6 CBUS_REG_ADDR(USB_ADDR6) -#define USB_ADDR7 0x2207 -#define P_USB_ADDR7 CBUS_REG_ADDR(USB_ADDR7) -#define USB_ADDR8 0x2208 -#define P_USB_ADDR8 CBUS_REG_ADDR(USB_ADDR8) -#define USB_ADDR9 0x2209 -#define P_USB_ADDR9 CBUS_REG_ADDR(USB_ADDR9) -#define USB_ADDR10 0x220a -#define P_USB_ADDR10 CBUS_REG_ADDR(USB_ADDR10) -#define USB_ADDR11 0x220b -#define P_USB_ADDR11 CBUS_REG_ADDR(USB_ADDR11) -#define USB_ADDR12 0x220c -#define P_USB_ADDR12 CBUS_REG_ADDR(USB_ADDR12) -#define USB_ADDR13 0x220d -#define P_USB_ADDR13 CBUS_REG_ADDR(USB_ADDR13) -#define USB_ADDR14 0x220e -#define P_USB_ADDR14 CBUS_REG_ADDR(USB_ADDR14) -#define USB_ADDR15 0x220f -#define P_USB_ADDR15 CBUS_REG_ADDR(USB_ADDR15) -#define USB_ADDR16 0x2210 -#define P_USB_ADDR16 CBUS_REG_ADDR(USB_ADDR16) -#define USB_ADDR17 0x2211 -#define P_USB_ADDR17 CBUS_REG_ADDR(USB_ADDR17) -#define USB_ADDR18 0x2212 -#define P_USB_ADDR18 CBUS_REG_ADDR(USB_ADDR18) -#define USB_ADDR19 0x2213 -#define P_USB_ADDR19 CBUS_REG_ADDR(USB_ADDR19) -#define USB_ADDR20 0x2214 -#define P_USB_ADDR20 CBUS_REG_ADDR(USB_ADDR20) -#define USB_ADDR21 0x2215 -#define P_USB_ADDR21 CBUS_REG_ADDR(USB_ADDR21) -#define USB_ADDR22 0x2216 -#define P_USB_ADDR22 CBUS_REG_ADDR(USB_ADDR22) -#define USB_ADDR23 0x2217 -#define P_USB_ADDR23 CBUS_REG_ADDR(USB_ADDR23) -#define USB_ADDR24 0x2218 -#define P_USB_ADDR24 CBUS_REG_ADDR(USB_ADDR24) -#define USB_ADDR25 0x2219 -#define P_USB_ADDR25 CBUS_REG_ADDR(USB_ADDR25) -#define USB_ADDR26 0x221a -#define P_USB_ADDR26 CBUS_REG_ADDR(USB_ADDR26) -#define USB_ADDR27 0x221b -#define P_USB_ADDR27 CBUS_REG_ADDR(USB_ADDR27) -#define USB_ADDR28 0x221c -#define P_USB_ADDR28 CBUS_REG_ADDR(USB_ADDR28) -#define USB_ADDR29 0x221d -#define P_USB_ADDR29 CBUS_REG_ADDR(USB_ADDR29) -#define USB_ADDR30 0x221e -#define P_USB_ADDR30 CBUS_REG_ADDR(USB_ADDR30) -#define USB_ADDR31 0x221f -#define P_USB_ADDR31 CBUS_REG_ADDR(USB_ADDR31) -/*add from M8M2*/ -#define SANA_STREAM_CONTROL 0x2220 -#define P_SANA_STREAM_CONTROL CBUS_REG_ADDR(SANA_STREAM_CONTROL) -#define SANA_STREAM_START_ADDR 0x2221 -#define P_SANA_STREAM_START_ADDR \ - CBUS_REG_ADDR(SANA_STREAM_START_ADDR) -#define SANA_STREAM_END_ADDR 0x2222 -#define P_SANA_STREAM_END_ADDR CBUS_REG_ADDR(SANA_STREAM_END_ADDR) -#define SANA_STREAM_WR_PTR 0x2223 -#define P_SANA_STREAM_WR_PTR CBUS_REG_ADDR(SANA_STREAM_WR_PTR) -#define SANA_STREAM_RD_PTR 0x2224 -#define P_SANA_STREAM_RD_PTR CBUS_REG_ADDR(SANA_STREAM_RD_PTR) -#define SANA_STREAM_LEVEL 0x2225 -#define P_SANA_STREAM_LEVEL CBUS_REG_ADDR(SANA_STREAM_LEVEL) -#define SANA_STREAM_FIFO_CTL 0x2226 -#define P_SANA_STREAM_FIFO_CTL CBUS_REG_ADDR(SANA_STREAM_FIFO_CTL) -#define SANA_SHIFT_CONTROL 0x2227 -#define P_SANA_SHIFT_CONTROL CBUS_REG_ADDR(SANA_SHIFT_CONTROL) -#define SANA_SHIFT_STARTCODE 0x2228 -#define P_SANA_SHIFT_STARTCODE CBUS_REG_ADDR(SANA_SHIFT_STARTCODE) -#define SANA_SHIFT_EMULATECODE 0x2229 -#define P_SANA_SHIFT_EMULATECODE \ - CBUS_REG_ADDR(SANA_SHIFT_EMULATECODE) -#define SANA_SHIFT_STATUS 0x222a -#define P_SANA_SHIFT_STATUS CBUS_REG_ADDR(SANA_SHIFT_STATUS) -#define SANA_SHIFTED_DATA 0x222b -#define P_SANA_SHIFTED_DATA CBUS_REG_ADDR(SANA_SHIFTED_DATA) -#define SANA_SHIFT_BYTE_COUNT 0x222c -#define P_SANA_SHIFT_BYTE_COUNT \ - CBUS_REG_ADDR(SANA_SHIFT_BYTE_COUNT) -#define SANA_SHIFT_COMMAND 0x222d -#define P_SANA_SHIFT_COMMAND CBUS_REG_ADDR(SANA_SHIFT_COMMAND) -#define SANA_ELEMENT_RESULT 0x222e -#define P_SANA_ELEMENT_RESULT CBUS_REG_ADDR(SANA_ELEMENT_RESULT) -#define ATOM_LOCK 0x222f -#define P_ATOM_LOCK CBUS_REG_ADDR(ATOM_LOCK) -/**/ -#define NDMA_CNTL_REG0 0x2270 -#define P_NDMA_CNTL_REG0 CBUS_REG_ADDR(NDMA_CNTL_REG0) -#define NDMA_TABLE_ADD_REG 0x2272 -#define P_NDMA_TABLE_ADD_REG CBUS_REG_ADDR(NDMA_TABLE_ADD_REG) -#define NDMA_TDES_KEY_LO 0x2273 -#define P_NDMA_TDES_KEY_LO CBUS_REG_ADDR(NDMA_TDES_KEY_LO) -#define NDMA_TDES_KEY_HI 0x2274 -#define P_NDMA_TDES_KEY_HI CBUS_REG_ADDR(NDMA_TDES_KEY_HI) -#define NDMA_TDES_CONTROL 0x2275 -#define P_NDMA_TDES_CONTROL CBUS_REG_ADDR(NDMA_TDES_CONTROL) -#define NDMA_RIJNDAEL_CONTROL 0x2276 -#define P_NDMA_RIJNDAEL_CONTROL \ - CBUS_REG_ADDR(NDMA_RIJNDAEL_CONTROL) -#define NDMA_RIJNDAEL_RK_FIFO 0x2277 -#define P_NDMA_RIJNDAEL_RK_FIFO \ - CBUS_REG_ADDR(NDMA_RIJNDAEL_RK_FIFO) -#define NDMA_CRC_OUT 0x2278 -#define P_NDMA_CRC_OUT CBUS_REG_ADDR(NDMA_CRC_OUT) -#define NDMA_THREAD_REG 0x2279 -#define P_NDMA_THREAD_REG CBUS_REG_ADDR(NDMA_THREAD_REG) -#define NDMA_THREAD_TABLE_START0 0x2280 -#define P_NDMA_THREAD_TABLE_START0 \ - CBUS_REG_ADDR(NDMA_THREAD_TABLE_START0) -#define NDMA_THREAD_TABLE_CURR0 0x2281 -#define NDMA_CNTL_REG1 0x228c -#define P_NDMA_CNTL_REG1 CBUS_REG_ADDR(NDMA_CNTL_REG1) -#define NDMA_AES_KEY_0 0x2290 -#define P_NDMA_AES_KEY_0 CBUS_REG_ADDR(NDMA_AES_KEY_0) -#define NDMA_AES_KEY_1 0x2291 -#define P_NDMA_AES_KEY_1 CBUS_REG_ADDR(NDMA_AES_KEY_1) -#define NDMA_AES_KEY_2 0x2292 -#define P_NDMA_AES_KEY_2 CBUS_REG_ADDR(NDMA_AES_KEY_2) -#define NDMA_AES_KEY_3 0x2293 -#define P_NDMA_AES_KEY_3 CBUS_REG_ADDR(NDMA_AES_KEY_3) -#define NDMA_AES_KEY_4 0x2294 -#define P_NDMA_AES_KEY_4 CBUS_REG_ADDR(NDMA_AES_KEY_4) -#define NDMA_AES_KEY_5 0x2295 -#define P_NDMA_AES_KEY_5 CBUS_REG_ADDR(NDMA_AES_KEY_5) -#define NDMA_AES_KEY_6 0x2296 -#define P_NDMA_AES_KEY_6 CBUS_REG_ADDR(NDMA_AES_KEY_6) -#define NDMA_AES_KEY_7 0x2297 -#define P_NDMA_AES_KEY_7 CBUS_REG_ADDR(NDMA_AES_KEY_7) -#define NDMA_AES_IV_0 0x2298 -#define P_NDMA_AES_IV_0 CBUS_REG_ADDR(NDMA_AES_IV_0) -#define NDMA_AES_IV_1 0x2299 -#define P_NDMA_AES_IV_1 CBUS_REG_ADDR(NDMA_AES_IV_1) -#define NDMA_AES_IV_2 0x229a -#define P_NDMA_AES_IV_2 CBUS_REG_ADDR(NDMA_AES_IV_2) -#define NDMA_AES_IV_3 0x229b -#define P_NDMA_AES_IV_3 CBUS_REG_ADDR(NDMA_AES_IV_3) -#define NDMA_AES_REG0 0x229c -#define P_NDMA_AES_REG0 CBUS_REG_ADDR(NDMA_AES_REG0) -#define STREAM_EVENT_INFO 0x2300 -#define P_STREAM_EVENT_INFO CBUS_REG_ADDR(STREAM_EVENT_INFO) -#define STREAM_OUTPUT_CONFIG 0x2301 -#define P_STREAM_OUTPUT_CONFIG CBUS_REG_ADDR(STREAM_OUTPUT_CONFIG) -#define C_D_BUS_CONTROL 0x2302 -#define P_C_D_BUS_CONTROL CBUS_REG_ADDR(C_D_BUS_CONTROL) -#define C_DATA 0x2303 -#define P_C_DATA CBUS_REG_ADDR(C_DATA) -#define STREAM_BUS_CONFIG 0x2304 -#define P_STREAM_BUS_CONFIG CBUS_REG_ADDR(STREAM_BUS_CONFIG) -#define STREAM_EVENT_CTL 0x2307 -#define P_STREAM_EVENT_CTL CBUS_REG_ADDR(STREAM_EVENT_CTL) -#define CMD_ARGUMENT 0x2308 -#define P_CMD_ARGUMENT CBUS_REG_ADDR(CMD_ARGUMENT) -#define CMD_SEND 0x2309 -#define P_CMD_SEND CBUS_REG_ADDR(CMD_SEND) -#define SDIO_CONFIG 0x230a -#define P_SDIO_CONFIG CBUS_REG_ADDR(SDIO_CONFIG) -#define SDIO_STATUS_IRQ 0x230b -#define P_SDIO_STATUS_IRQ CBUS_REG_ADDR(SDIO_STATUS_IRQ) -#define SDIO_IRQ_CONFIG 0x230c -#define P_SDIO_IRQ_CONFIG CBUS_REG_ADDR(SDIO_IRQ_CONFIG) -#define SDIO_MULT_CONFIG 0x230d -#define P_SDIO_MULT_CONFIG CBUS_REG_ADDR(SDIO_MULT_CONFIG) -#define SDIO_M_ADDR 0x230e -#define P_SDIO_M_ADDR CBUS_REG_ADDR(SDIO_M_ADDR) -#define SDIO_EXTENSION 0x230f -#define P_SDIO_EXTENSION CBUS_REG_ADDR(SDIO_EXTENSION) -#define ASYNC_FIFO_REG0 0x2310 + +#define STB_CBUS_BASE aml_stb_get_base(ID_STB_CBUS_BASE) +#define SMARTCARD_REG_BASE aml_stb_get_base(ID_SMARTCARD_REG_BASE) +#define ASYNC_FIFO_REG_BASE aml_stb_get_base(ID_ASYNC_FIFO_REG_BASE) +#define ASYNC_FIFO2_REG_BASE aml_stb_get_base(ID_ASYNC_FIFO2_REG_BASE) +#define RESET_BASE aml_stb_get_base(ID_RESET_BASE) +#define PARSER_SUB_START_PTR_BASE \ + aml_stb_get_base(ID_PARSER_SUB_START_PTR_BASE) + +#define HHI_CSI_PHY_CNTL_BASE 0x1000 + +#define DEMUX_1_OFFSET 0x00 +#define DEMUX_2_OFFSET 0x50 +#define DEMUX_3_OFFSET 0xa0 + + +#define STB_TOP_CONFIG (STB_CBUS_BASE + 0xf0) +#define P_STB_TOP_CONFIG CBUS_REG_ADDR(STB_TOP_CONFIG) +#define TS_TOP_CONFIG (STB_CBUS_BASE + 0xf1) +#define P_TS_TOP_CONFIG CBUS_REG_ADDR(TS_TOP_CONFIG) +#define TS_FILE_CONFIG (STB_CBUS_BASE + 0xf2) +#define P_TS_FILE_CONFIG CBUS_REG_ADDR(TS_FILE_CONFIG) +#define TS_PL_PID_INDEX (STB_CBUS_BASE + 0xf3) +#define P_TS_PL_PID_INDEX CBUS_REG_ADDR(TS_PL_PID_INDEX) +#define TS_PL_PID_DATA (STB_CBUS_BASE + 0xf4) +#define P_TS_PL_PID_DATA CBUS_REG_ADDR(TS_PL_PID_DATA) +#define COMM_DESC_KEY0 (STB_CBUS_BASE + 0xf5) +#define P_COMM_DESC_KEY0 CBUS_REG_ADDR(COMM_DESC_KEY0) +#define COMM_DESC_KEY1 (STB_CBUS_BASE + 0xf6) +#define P_COMM_DESC_KEY1 CBUS_REG_ADDR(COMM_DESC_KEY1) +#define COMM_DESC_KEY_RW (STB_CBUS_BASE + 0xf7) +#define P_COMM_DESC_KEY_RW CBUS_REG_ADDR(COMM_DESC_KEY_RW) +#define CIPLUS_KEY0 (STB_CBUS_BASE + 0xf8) +#define P_CIPLUS_KEY0 CBUS_REG_ADDR(CIPLUS_KEY0) +#define CIPLUS_KEY1 (STB_CBUS_BASE + 0xf9) +#define P_CIPLUS_KEY1 CBUS_REG_ADDR(CIPLUS_KEY1) +#define CIPLUS_KEY2 (STB_CBUS_BASE + 0xfa) +#define P_CIPLUS_KEY2 CBUS_REG_ADDR(CIPLUS_KEY2) +#define CIPLUS_KEY3 (STB_CBUS_BASE + 0xfb) +#define P_CIPLUS_KEY3 CBUS_REG_ADDR(CIPLUS_KEY3) +#define CIPLUS_KEY_WR (STB_CBUS_BASE + 0xfc) +#define P_CIPLUS_KEY_WR CBUS_REG_ADDR(CIPLUS_KEY_WR) +#define CIPLUS_CONFIG (STB_CBUS_BASE + 0xfd) +#define P_CIPLUS_CONFIG CBUS_REG_ADDR(CIPLUS_CONFIG) +#define CIPLUS_ENDIAN (STB_CBUS_BASE + 0xfe) +#define P_CIPLUS_ENDIAN CBUS_REG_ADDR(CIPLUS_ENDIAN) + +#define SMARTCARD_REG0 (SMARTCARD_REG_BASE + 0x0) +#define P_SMARTCARD_REG0 CBUS_REG_ADDR(SMARTCARD_REG0) +#define SMARTCARD_REG1 (SMARTCARD_REG_BASE + 0x1) +#define P_SMARTCARD_REG1 CBUS_REG_ADDR(SMARTCARD_REG1) +#define SMARTCARD_REG2 (SMARTCARD_REG_BASE + 0x2) +#define P_SMARTCARD_REG2 CBUS_REG_ADDR(SMARTCARD_REG2) +#define SMARTCARD_STATUS (SMARTCARD_REG_BASE + 0x3) +#define P_SMARTCARD_STATUS CBUS_REG_ADDR(SMARTCARD_STATUS) +#define SMARTCARD_INTR (SMARTCARD_REG_BASE + 0x4) +#define P_SMARTCARD_INTR CBUS_REG_ADDR(SMARTCARD_INTR) +#define SMARTCARD_REG5 (SMARTCARD_REG_BASE + 0x5) +#define P_SMARTCARD_REG5 CBUS_REG_ADDR(SMARTCARD_REG5) +#define SMARTCARD_REG6 (SMARTCARD_REG_BASE + 0x6) +#define P_SMARTCARD_REG6 CBUS_REG_ADDR(SMARTCARD_REG6) +#define SMARTCARD_FIFO (SMARTCARD_REG_BASE + 0x7) +#define P_SMARTCARD_FIFO CBUS_REG_ADDR(SMARTCARD_FIFO) +#define SMARTCARD_REG8 (SMARTCARD_REG_BASE + 0x8) +#define P_SMARTCARD_REG8 CBUS_REG_ADDR(SMARTCARD_REG8) + +#define ASYNC_FIFO_REG0 (ASYNC_FIFO_REG_BASE + 0x0) #define P_ASYNC_FIFO_REG0 CBUS_REG_ADDR(ASYNC_FIFO_REG0) -#define ASYNC_FIFO_REG1 0x2311 +#define ASYNC_FIFO_REG1 (ASYNC_FIFO_REG_BASE + 0x1) #define P_ASYNC_FIFO_REG1 CBUS_REG_ADDR(ASYNC_FIFO_REG1) -#define ASYNC_FIFO_REG2 0x2312 +#define ASYNC_FIFO_REG2 (ASYNC_FIFO_REG_BASE + 0x2) #define P_ASYNC_FIFO_REG2 CBUS_REG_ADDR(ASYNC_FIFO_REG2) -#define ASYNC_FIFO_REG3 0x2313 +#define ASYNC_FIFO_REG3 (ASYNC_FIFO_REG_BASE + 0x3) #define P_ASYNC_FIFO_REG3 CBUS_REG_ADDR(ASYNC_FIFO_REG3) -#define ASYNC_FIFO2_REG0 0x2314 +#define ASYNC_FIFO_REG4 (ASYNC_FIFO_REG_BASE + 0x4) +#define P_ASYNC_FIFO_REG4 CBUS_REG_ADDR(ASYNC_FIFO_REG4) +#define ASYNC_FIFO_REG5 (ASYNC_FIFO_REG_BASE + 0x5) +#define P_ASYNC_FIFO_REG5 CBUS_REG_ADDR(ASYNC_FIFO_REG5) + + +#define ASYNC_FIFO2_REG0 (ASYNC_FIFO2_REG_BASE + 0x0) #define P_ASYNC_FIFO2_REG0 CBUS_REG_ADDR(ASYNC_FIFO2_REG0) -#define ASYNC_FIFO2_REG1 0x2315 +#define ASYNC_FIFO2_REG1 (ASYNC_FIFO2_REG_BASE + 0x1) #define P_ASYNC_FIFO2_REG1 CBUS_REG_ADDR(ASYNC_FIFO2_REG1) -#define ASYNC_FIFO2_REG2 0x2316 +#define ASYNC_FIFO2_REG2 (ASYNC_FIFO2_REG_BASE + 0x2) #define P_ASYNC_FIFO2_REG2 CBUS_REG_ADDR(ASYNC_FIFO2_REG2) -#define ASYNC_FIFO2_REG3 0x2317 +#define ASYNC_FIFO2_REG3 (ASYNC_FIFO2_REG_BASE + 0x3) #define P_ASYNC_FIFO2_REG3 CBUS_REG_ADDR(ASYNC_FIFO2_REG3) -#define SDIO_AHB_CBUS_CTRL 0x2318 -#define P_SDIO_AHB_CBUS_CTRL CBUS_REG_ADDR(SDIO_AHB_CBUS_CTRL) -#define SDIO_AHB_CBUS_M_DATA 0x2319 -#define P_SDIO_AHB_CBUS_M_DATA CBUS_REG_ADDR(SDIO_AHB_CBUS_M_DATA) -#define SPI_FLASH_CMD 0x2320 -#define P_SPI_FLASH_CMD CBUS_REG_ADDR(SPI_FLASH_CMD) -#define SPI_FLASH_ADDR 0x2321 -#define P_SPI_FLASH_ADDR CBUS_REG_ADDR(SPI_FLASH_ADDR) -#define SPI_FLASH_CTRL 0x2322 -#define P_SPI_FLASH_CTRL CBUS_REG_ADDR(SPI_FLASH_CTRL) -#define SPI_FLASH_CTRL1 0x2323 -#define P_SPI_FLASH_CTRL1 CBUS_REG_ADDR(SPI_FLASH_CTRL1) -#define SPI_FLASH_STATUS 0x2324 -#define P_SPI_FLASH_STATUS CBUS_REG_ADDR(SPI_FLASH_STATUS) -#define SPI_FLASH_CTRL2 0x2325 -#define P_SPI_FLASH_CTRL2 CBUS_REG_ADDR(SPI_FLASH_CTRL2) -#define SPI_FLASH_CLOCK 0x2326 -#define P_SPI_FLASH_CLOCK CBUS_REG_ADDR(SPI_FLASH_CLOCK) -#define SPI_FLASH_USER 0x2327 -#define P_SPI_FLASH_USER CBUS_REG_ADDR(SPI_FLASH_USER) -#define SPI_FLASH_USER1 0x2328 -#define P_SPI_FLASH_USER1 CBUS_REG_ADDR(SPI_FLASH_USER1) -#define SPI_FLASH_USER2 0x2329 -#define P_SPI_FLASH_USER2 CBUS_REG_ADDR(SPI_FLASH_USER2) -#define SPI_FLASH_USER3 0x232a -#define P_SPI_FLASH_USER3 CBUS_REG_ADDR(SPI_FLASH_USER3) -#define SPI_FLASH_USER4 0x232b -#define P_SPI_FLASH_USER4 CBUS_REG_ADDR(SPI_FLASH_USER4) -#define SPI_FLASH_SLAVE 0x232c -#define P_SPI_FLASH_SLAVE CBUS_REG_ADDR(SPI_FLASH_SLAVE) -#define SPI_FLASH_SLAVE1 0x232d -#define P_SPI_FLASH_SLAVE1 CBUS_REG_ADDR(SPI_FLASH_SLAVE1) -#define SPI_FLASH_SLAVE2 0x232e -#define P_SPI_FLASH_SLAVE2 CBUS_REG_ADDR(SPI_FLASH_SLAVE2) -#define SPI_FLASH_SLAVE3 0x232f -#define P_SPI_FLASH_SLAVE3 CBUS_REG_ADDR(SPI_FLASH_SLAVE3) -#define SPI_FLASH_C0 0x2330 -#define P_SPI_FLASH_C0 CBUS_REG_ADDR(SPI_FLASH_C0) -#define SPI_FLASH_C1 0x2331 -#define P_SPI_FLASH_C1 CBUS_REG_ADDR(SPI_FLASH_C1) -#define SPI_FLASH_C2 0x2332 -#define P_SPI_FLASH_C2 CBUS_REG_ADDR(SPI_FLASH_C2) -#define SPI_FLASH_C3 0x2333 -#define P_SPI_FLASH_C3 CBUS_REG_ADDR(SPI_FLASH_C3) -#define SPI_FLASH_C4 0x2334 -#define P_SPI_FLASH_C4 CBUS_REG_ADDR(SPI_FLASH_C4) -#define SPI_FLASH_C5 0x2335 -#define P_SPI_FLASH_C5 CBUS_REG_ADDR(SPI_FLASH_C5) -#define SPI_FLASH_C6 0x2336 -#define P_SPI_FLASH_C6 CBUS_REG_ADDR(SPI_FLASH_C6) -#define SPI_FLASH_C7 0x2337 -#define P_SPI_FLASH_C7 CBUS_REG_ADDR(SPI_FLASH_C7) -#define SPI_FLASH_B8 0x2338 -#define P_SPI_FLASH_B8 CBUS_REG_ADDR(SPI_FLASH_B8) -#define SPI_FLASH_B9 0x2339 -#define P_SPI_FLASH_B9 CBUS_REG_ADDR(SPI_FLASH_B9) -#define SPI_FLASH_B10 0x233a -#define P_SPI_FLASH_B10 CBUS_REG_ADDR(SPI_FLASH_B10) -#define SPI_FLASH_B11 0x233b -#define P_SPI_FLASH_B11 CBUS_REG_ADDR(SPI_FLASH_B11) -#define SPI_FLASH_B12 0x233c -#define P_SPI_FLASH_B12 CBUS_REG_ADDR(SPI_FLASH_B12) -#define SPI_FLASH_B13 0x233d -#define P_SPI_FLASH_B13 CBUS_REG_ADDR(SPI_FLASH_B13) -#define SPI_FLASH_B14 0x233e -#define P_SPI_FLASH_B14 CBUS_REG_ADDR(SPI_FLASH_B14) -#define SPI_FLASH_B15 0x233f -#define P_SPI_FLASH_B15 CBUS_REG_ADDR(SPI_FLASH_B15) -#define I2C_M_3_CONTROL_REG 0x2348 -#define P_I2C_M_3_CONTROL_REG CBUS_REG_ADDR(I2C_M_3_CONTROL_REG) -#define I2C_M_3_SLAVE_ADDR 0x2349 -#define P_I2C_M_3_SLAVE_ADDR CBUS_REG_ADDR(I2C_M_3_SLAVE_ADDR) -#define I2C_M_3_TOKEN_LIST0 0x234a -#define P_I2C_M_3_TOKEN_LIST0 CBUS_REG_ADDR(I2C_M_3_TOKEN_LIST0) -#define I2C_M_3_TOKEN_LIST1 0x234b -#define P_I2C_M_3_TOKEN_LIST1 CBUS_REG_ADDR(I2C_M_3_TOKEN_LIST1) -#define I2C_M_3_WDATA_REG0 0x234c -#define P_I2C_M_3_WDATA_REG0 CBUS_REG_ADDR(I2C_M_3_WDATA_REG0) -#define I2C_M_3_WDATA_REG1 0x234d -#define P_I2C_M_3_WDATA_REG1 CBUS_REG_ADDR(I2C_M_3_WDATA_REG1) -#define I2C_M_3_RDATA_REG0 0x234e -#define P_I2C_M_3_RDATA_REG0 CBUS_REG_ADDR(I2C_M_3_RDATA_REG0) -#define I2C_M_3_RDATA_REG1 0x234f -#define P_I2C_M_3_RDATA_REG1 CBUS_REG_ADDR(I2C_M_3_RDATA_REG1) -#define SPICC_RXDATA 0x2360 -#define P_SPICC_RXDATA CBUS_REG_ADDR(SPICC_RXDATA) -#define SPICC_TXDATA 0x2361 -#define P_SPICC_TXDATA CBUS_REG_ADDR(SPICC_TXDATA) -#define SPICC_CONREG 0x2362 -#define P_SPICC_CONREG CBUS_REG_ADDR(SPICC_CONREG) -#define SPICC_INTREG 0x2363 -#define P_SPICC_INTREG CBUS_REG_ADDR(SPICC_INTREG) -#define SPICC_DMAREG 0x2364 -#define P_SPICC_DMAREG CBUS_REG_ADDR(SPICC_DMAREG) -#define SPICC_STATREG 0x2365 -#define P_SPICC_STATREG CBUS_REG_ADDR(SPICC_STATREG) -#define SPICC_PERIODREG 0x2366 -#define P_SPICC_PERIODREG CBUS_REG_ADDR(SPICC_PERIODREG) -#define SPICC_TESTREG 0x2367 -#define P_SPICC_TESTREG CBUS_REG_ADDR(SPICC_TESTREG) -#define SPICC_DRADDR 0x2368 -#define P_SPICC_DRADDR CBUS_REG_ADDR(SPICC_DRADDR) -#define SPICC_DWADDR 0x2369 -#define P_SPICC_DWADDR CBUS_REG_ADDR(SPICC_DWADDR) -#define SD_REG0_ARGU 0x2380 -#define P_SD_REG0_ARGU CBUS_REG_ADDR(SD_REG0_ARGU) -#define SD_REG1_SEND 0x2381 -#define P_SD_REG1_SEND CBUS_REG_ADDR(SD_REG1_SEND) -#define SD_REG2_CNTL 0x2382 -#define P_SD_REG2_CNTL CBUS_REG_ADDR(SD_REG2_CNTL) -#define SD_REG3_STAT 0x2383 -#define P_SD_REG3_STAT CBUS_REG_ADDR(SD_REG3_STAT) -#define SD_REG4_CLKC 0x2384 -#define P_SD_REG4_CLKC CBUS_REG_ADDR(SD_REG4_CLKC) -#define SD_REG5_ADDR 0x2385 -#define P_SD_REG5_ADDR CBUS_REG_ADDR(SD_REG5_ADDR) -#define SD_REG6_PDMA 0x2386 -#define P_SD_REG6_PDMA CBUS_REG_ADDR(SD_REG6_PDMA) -#define SD_REG7_MISC 0x2387 -#define P_SD_REG7_MISC CBUS_REG_ADDR(SD_REG7_MISC) -#define SD_REG8_DATA 0x2388 -#define P_SD_REG8_DATA CBUS_REG_ADDR(SD_REG8_DATA) -#define SD_REG9_ICTL 0x2389 -#define P_SD_REG9_ICTL CBUS_REG_ADDR(SD_REG9_ICTL) -#define SD_REGA_ISTA 0x238a -#define P_SD_REGA_ISTA CBUS_REG_ADDR(SD_REGA_ISTA) -#define SD_REGB_SRST 0x238b -#define P_SD_REGB_SRST CBUS_REG_ADDR(SD_REGB_SRST) -#define SD_REGC_ESTA 0x238c -#define P_SD_REGC_ESTA CBUS_REG_ADDR(SD_REGC_ESTA) -#define SD_REGD_ENHC 0x238d -#define P_SD_REGD_ENHC CBUS_REG_ADDR(SD_REGD_ENHC) -#define SD_REGE_CLK2 0x238e -#define P_SD_REGE_CLK2 CBUS_REG_ADDR(SD_REGE_CLK2) -#define ISA_DEBUG_REG0 0x2600 -#define P_ISA_DEBUG_REG0 CBUS_REG_ADDR(ISA_DEBUG_REG0) -#define ISA_DEBUG_REG1 0x2601 -#define P_ISA_DEBUG_REG1 CBUS_REG_ADDR(ISA_DEBUG_REG1) -#define ISA_DEBUG_REG2 0x2602 -#define P_ISA_DEBUG_REG2 CBUS_REG_ADDR(ISA_DEBUG_REG2) -#define ISA_DEBUG_REG3 0x2603 -#define P_ISA_DEBUG_REG3 CBUS_REG_ADDR(ISA_DEBUG_REG3) -#define ISA_PLL_CLK_SIM0 0x2608 -#define P_ISA_PLL_CLK_SIM0 CBUS_REG_ADDR(ISA_PLL_CLK_SIM0) -#define ISA_CNTL_REG0 0x2609 -#define P_ISA_CNTL_REG0 CBUS_REG_ADDR(ISA_CNTL_REG0) -#define AO_CPU_IRQ_IN0_INTR_STAT 0x2610 -#define P_AO_CPU_IRQ_IN0_INTR_STAT \ - CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_STAT) -#define AO_CPU_IRQ_IN0_INTR_STAT_CLR 0x2611 -#define P_AO_CPU_IRQ_IN0_INTR_STAT_CLR \ - CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_STAT_CLR) -#define AO_CPU_IRQ_IN0_INTR_MASK 0x2612 -#define P_AO_CPU_IRQ_IN0_INTR_MASK \ - CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_MASK) -#define AO_CPU_IRQ_IN0_INTR_FIRQ_SEL 0x2613 -#define P_AO_CPU_IRQ_IN0_INTR_FIRQ_SEL \ - CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_FIRQ_SEL) -#define GPIO_INTR_EDGE_POL 0x2620 -#define P_GPIO_INTR_EDGE_POL CBUS_REG_ADDR(GPIO_INTR_EDGE_POL) -#define GPIO_INTR_GPIO_SEL0 0x2621 -#define P_GPIO_INTR_GPIO_SEL0 CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL0) -#define GPIO_INTR_GPIO_SEL1 0x2622 -#define P_GPIO_INTR_GPIO_SEL1 CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL1) -#define GPIO_INTR_FILTER_SEL0 0x2623 -#define P_GPIO_INTR_FILTER_SEL0 \ - CBUS_REG_ADDR(GPIO_INTR_FILTER_SEL0) -#define MEDIA_CPU_INTR_STAT 0x2628 -#define P_MEDIA_CPU_INTR_STAT CBUS_REG_ADDR(MEDIA_CPU_INTR_STAT) -#define ISA_BIST_REG1 0x2631 -#define P_ISA_BIST_REG1 CBUS_REG_ADDR(ISA_BIST_REG1) -#define WATCHDOG_TC 0x2640 -#define P_WATCHDOG_TC CBUS_REG_ADDR(WATCHDOG_TC) -#define WATCHDOG_RESET 0x2641 -#define P_WATCHDOG_RESET CBUS_REG_ADDR(WATCHDOG_RESET) -#define AHB_ARBITER_REG 0x2642 -#define P_AHB_ARBITER_REG CBUS_REG_ADDR(AHB_ARBITER_REG) -#define AHB_ARBDEC_REG 0x2643 -#define P_AHB_ARBDEC_REG CBUS_REG_ADDR(AHB_ARBDEC_REG) -#define AHB_ARBITER2_REG 0x264a -#define P_AHB_ARBITER2_REG CBUS_REG_ADDR(AHB_ARBITER2_REG) -#define DEVICE_MMCP_CNTL 0x264b -#define P_DEVICE_MMCP_CNTL CBUS_REG_ADDR(DEVICE_MMCP_CNTL) -#define AUDIO_MMCP_CNTL 0x264c -#define P_AUDIO_MMCP_CNTL CBUS_REG_ADDR(AUDIO_MMCP_CNTL) -#define ISA_TIMER_MUX 0x2650 -#define P_ISA_TIMER_MUX CBUS_REG_ADDR(ISA_TIMER_MUX) -#define ISA_TIMERA 0x2651 -#define P_ISA_TIMERA CBUS_REG_ADDR(ISA_TIMERA) -#define ISA_TIMERB 0x2652 -#define P_ISA_TIMERB CBUS_REG_ADDR(ISA_TIMERB) -#define ISA_TIMERC 0x2653 -#define P_ISA_TIMERC CBUS_REG_ADDR(ISA_TIMERC) -#define ISA_TIMERD 0x2654 -#define P_ISA_TIMERD CBUS_REG_ADDR(ISA_TIMERD) -#define ISA_TIMERE 0x2655 -#define P_ISA_TIMERE CBUS_REG_ADDR(ISA_TIMERE) -#define FBUF_ADDR 0x2656 -#define P_FBUF_ADDR CBUS_REG_ADDR(FBUF_ADDR) -#define SDRAM_CTL0 0x2657 -#define P_SDRAM_CTL0 CBUS_REG_ADDR(SDRAM_CTL0) -#define SDRAM_CTL2 0x2658 -#define P_SDRAM_CTL2 CBUS_REG_ADDR(SDRAM_CTL2) -#define SDRAM_CTL4 0x265a -#define P_SDRAM_CTL4 CBUS_REG_ADDR(SDRAM_CTL4) -#define SDRAM_CTL5 0x265b -#define P_SDRAM_CTL5 CBUS_REG_ADDR(SDRAM_CTL5) -#define SDRAM_CTL6 0x265c -#define P_SDRAM_CTL6 CBUS_REG_ADDR(SDRAM_CTL6) -#define SDRAM_CTL7 0x265d -#define P_SDRAM_CTL7 CBUS_REG_ADDR(SDRAM_CTL7) -#define SDRAM_CTL8 0x265e -#define P_SDRAM_CTL8 CBUS_REG_ADDR(SDRAM_CTL8) -#define AHB_MP4_MC_CTL 0x265f -#define P_AHB_MP4_MC_CTL CBUS_REG_ADDR(AHB_MP4_MC_CTL) -#define MEDIA_CPU_PCR 0x2660 -#define P_MEDIA_CPU_PCR CBUS_REG_ADDR(MEDIA_CPU_PCR) -#define MEDIA_CPU_CTL 0x2661 -#define P_MEDIA_CPU_CTL CBUS_REG_ADDR(MEDIA_CPU_CTL) -#define ISA_TIMER_MUX1 0x2664 -#define P_ISA_TIMER_MUX1 CBUS_REG_ADDR(ISA_TIMER_MUX1) -#define ISA_TIMERF 0x2665 -#define P_ISA_TIMERF CBUS_REG_ADDR(ISA_TIMERF) -#define ISA_TIMERG 0x2666 -#define P_ISA_TIMERG CBUS_REG_ADDR(ISA_TIMERG) -#define ISA_TIMERH 0x2667 -#define P_ISA_TIMERH CBUS_REG_ADDR(ISA_TIMERH) -#define ISA_TIMERI 0x2668 -#define P_ISA_TIMERI CBUS_REG_ADDR(ISA_TIMERI) -#define ABUF_WR_CTL0 0x2670 -#define P_ABUF_WR_CTL0 CBUS_REG_ADDR(ABUF_WR_CTL0) -#define ABUF_WR_CTL1 0x2671 -#define P_ABUF_WR_CTL1 CBUS_REG_ADDR(ABUF_WR_CTL1) -#define ABUF_WR_CTL2 0x2672 -#define P_ABUF_WR_CTL2 CBUS_REG_ADDR(ABUF_WR_CTL2) -#define ABUF_WR_CTL3 0x2673 -#define P_ABUF_WR_CTL3 CBUS_REG_ADDR(ABUF_WR_CTL3) -#define ABUF_RD_CTL0 0x2674 -#define P_ABUF_RD_CTL0 CBUS_REG_ADDR(ABUF_RD_CTL0) -#define ABUF_RD_CTL1 0x2675 -#define P_ABUF_RD_CTL1 CBUS_REG_ADDR(ABUF_RD_CTL1) -#define ABUF_RD_CTL2 0x2676 -#define P_ABUF_RD_CTL2 CBUS_REG_ADDR(ABUF_RD_CTL2) -#define ABUF_RD_CTL3 0x2677 -#define P_ABUF_RD_CTL3 CBUS_REG_ADDR(ABUF_RD_CTL3) -#define ABUF_ARB_CTL0 0x2678 -#define P_ABUF_ARB_CTL0 CBUS_REG_ADDR(ABUF_ARB_CTL0) -#define ABUF_FIFO_CTL0 0x2679 -#define P_ABUF_FIFO_CTL0 CBUS_REG_ADDR(ABUF_FIFO_CTL0) -#define AHB_BRIDGE_CNTL_WR 0x2680 -#define P_AHB_BRIDGE_CNTL_WR CBUS_REG_ADDR(AHB_BRIDGE_CNTL_WR) -#define AHB_BRIDGE_REMAP0 0x2681 -#define P_AHB_BRIDGE_REMAP0 CBUS_REG_ADDR(AHB_BRIDGE_REMAP0) -#define AHB_BRIDGE_REMAP1 0x2682 -#define P_AHB_BRIDGE_REMAP1 CBUS_REG_ADDR(AHB_BRIDGE_REMAP1) -#define AHB_BRIDGE_REMAP2 0x2683 -#define P_AHB_BRIDGE_REMAP2 CBUS_REG_ADDR(AHB_BRIDGE_REMAP2) -#define AHB_BRIDGE_REMAP3 0x2684 -#define P_AHB_BRIDGE_REMAP3 CBUS_REG_ADDR(AHB_BRIDGE_REMAP3) -#define AHB_BRIDGE_CNTL_REG1 0x2685 -#define P_AHB_BRIDGE_CNTL_REG1 CBUS_REG_ADDR(AHB_BRIDGE_CNTL_REG1) -#define AHB_BRIDGE_CNTL_REG2 0x2686 -#define P_AHB_BRIDGE_CNTL_REG2 CBUS_REG_ADDR(AHB_BRIDGE_CNTL_REG2) -#define IQ_OM_WIDTH 0x2510 -#define P_IQ_OM_WIDTH CBUS_REG_ADDR(IQ_OM_WIDTH) -#define DBG_ADDR_START 0x2ff0 -#define P_DBG_ADDR_START CBUS_REG_ADDR(DBG_ADDR_START) -#define DBG_ADDR_END 0x2fff -#define P_DBG_ADDR_END CBUS_REG_ADDR(DBG_ADDR_END) -#define DBG_CTRL 0x2ff1 -#define P_DBG_CTRL CBUS_REG_ADDR(DBG_CTRL) -#define DBG_LED 0x2ff2 -#define P_DBG_LED CBUS_REG_ADDR(DBG_LED) -#define DBG_SWITCH 0x2ff3 -#define P_DBG_SWITCH CBUS_REG_ADDR(DBG_SWITCH) -#define DBG_VERSION 0x2ff4 -#define P_DBG_VERSION CBUS_REG_ADDR(DBG_VERSION) -#define VERSION_CTRL 0x1100 -#define P_VERSION_CTRL CBUS_REG_ADDR(VERSION_CTRL) -#define RESET0_REGISTER 0x1101 +#define ASYNC_FIFO2_REG4 (ASYNC_FIFO2_REG_BASE + 0x4) +#define P_ASYNC_FIFO2_REG4 CBUS_REG_ADDR(ASYNC_FIFO2_REG4) +#define ASYNC_FIFO2_REG5 (ASYNC_FIFO2_REG_BASE + 0x5) +#define P_ASYNC_FIFO2_REG5 CBUS_REG_ADDR(ASYNC_FIFO2_REG5) + + +#define RESET0_REGISTER (RESET_BASE + 0x1) #define P_RESET0_REGISTER CBUS_REG_ADDR(RESET0_REGISTER) -#define RESET1_REGISTER 0x1102 +#define RESET1_REGISTER (RESET_BASE + 0x2) #define P_RESET1_REGISTER CBUS_REG_ADDR(RESET1_REGISTER) -#define RESET2_REGISTER 0x1103 +#define RESET2_REGISTER (RESET_BASE + 0x3) #define P_RESET2_REGISTER CBUS_REG_ADDR(RESET2_REGISTER) -#define RESET3_REGISTER 0x1104 +#define RESET3_REGISTER (RESET_BASE + 0x4) #define P_RESET3_REGISTER CBUS_REG_ADDR(RESET3_REGISTER) -#define RESET4_REGISTER 0x1105 +#define RESET4_REGISTER (RESET_BASE + 0x5) #define P_RESET4_REGISTER CBUS_REG_ADDR(RESET4_REGISTER) -#define RESET5_REGISTER 0x1106 +#define RESET5_REGISTER (RESET_BASE + 0x6) #define P_RESET5_REGISTER CBUS_REG_ADDR(RESET5_REGISTER) -#define RESET6_REGISTER 0x1107 +#define RESET6_REGISTER (RESET_BASE + 0x7) #define P_RESET6_REGISTER CBUS_REG_ADDR(RESET6_REGISTER) -#define RESET7_REGISTER 0x1108 +#define RESET7_REGISTER (RESET_BASE + 0x8) #define P_RESET7_REGISTER CBUS_REG_ADDR(RESET7_REGISTER) -#define RESET0_MASK 0x1110 +#define RESET0_MASK (RESET_BASE + 0x10) #define P_RESET0_MASK CBUS_REG_ADDR(RESET0_MASK) -#define RESET1_MASK 0x1111 +#define RESET1_MASK (RESET_BASE + 0x11) #define P_RESET1_MASK CBUS_REG_ADDR(RESET1_MASK) -#define RESET2_MASK 0x1112 +#define RESET2_MASK (RESET_BASE + 0x12) #define P_RESET2_MASK CBUS_REG_ADDR(RESET2_MASK) -#define RESET3_MASK 0x1113 +#define RESET3_MASK (RESET_BASE + 0x13) #define P_RESET3_MASK CBUS_REG_ADDR(RESET3_MASK) -#define RESET4_MASK 0x1114 +#define RESET4_MASK (RESET_BASE + 0x14) #define P_RESET4_MASK CBUS_REG_ADDR(RESET4_MASK) -#define RESET5_MASK 0x1115 +#define RESET5_MASK (RESET_BASE + 0x15) #define P_RESET5_MASK CBUS_REG_ADDR(RESET5_MASK) -#define RESET6_MASK 0x1116 +#define RESET6_MASK (RESET_BASE + 0x16) #define P_RESET6_MASK CBUS_REG_ADDR(RESET6_MASK) -#define CRT_MASK 0x1117 +#define CRT_MASK (RESET_BASE + 0x17) #define P_CRT_MASK CBUS_REG_ADDR(CRT_MASK) -#define RESET7_MASK 0x1118 +#define RESET7_MASK (RESET_BASE + 0x18) #define P_RESET7_MASK CBUS_REG_ADDR(RESET7_MASK) /*add from M8M2*/ -#define RESET0_LEVEL 0xc1104480 -#define RESET1_LEVEL 0x1121 +#define P_RESET0_LEVEL CBUS_REG_ADDR(RESET0_LEVEL) +#define RESET1_LEVEL (RESET_BASE + 0x21) #define P_RESET1_LEVEL CBUS_REG_ADDR(RESET1_LEVEL) -#define RESET2_LEVEL 0x1122 +#define RESET2_LEVEL (RESET_BASE + 0x22) #define P_RESET2_LEVEL CBUS_REG_ADDR(RESET2_LEVEL) -#define RESET3_LEVEL 0x1123 +#define RESET3_LEVEL (RESET_BASE + 0x23) #define P_RESET3_LEVEL CBUS_REG_ADDR(RESET3_LEVEL) -#define RESET4_LEVEL 0x1124 +#define RESET4_LEVEL (RESET_BASE + 0x24) #define P_RESET4_LEVEL CBUS_REG_ADDR(RESET4_LEVEL) -#define RESET5_LEVEL 0x1125 +#define RESET5_LEVEL (RESET_BASE + 0x25) #define P_RESET5_LEVEL CBUS_REG_ADDR(RESET5_LEVEL) -#define RESET6_LEVEL 0x1126 +#define RESET6_LEVEL (RESET_BASE + 0x26) #define P_RESET6_LEVEL CBUS_REG_ADDR(RESET6_LEVEL) -#define RESET7_LEVEL 0x1127 +#define RESET7_LEVEL (RESET_BASE + 0x27) #define P_RESET7_LEVEL CBUS_REG_ADDR(RESET7_LEVEL) -/**/ -#define SCR_HIU 0x100b -#define P_SCR_HIU CBUS_REG_ADDR(SCR_HIU) -#define HPG_TIMER 0x100f -#define P_HPG_TIMER CBUS_REG_ADDR(HPG_TIMER) -/*add from M8M2*/ -#define HHI_GP_PLL_CNTL 0x1010 -#define P_HHI_GP_PLL_CNTL CBUS_REG_ADDR(HHI_GP_PLL_CNTL) -#define HHI_GP_PLL_CNTL2 0x1011 -#define P_HHI_GP_PLL_CNTL2 CBUS_REG_ADDR(HHI_GP_PLL_CNTL2) -#define HHI_GP_PLL_CNTL3 0x1012 -#define P_HHI_GP_PLL_CNTL3 CBUS_REG_ADDR(HHI_GP_PLL_CNTL3) -#define HHI_GP_PLL_CNTL4 0x1013 -#define P_HHI_GP_PLL_CNTL4 CBUS_REG_ADDR(HHI_GP_PLL_CNTL4) -#define HHI_GP_PLL_CNTL5 0x1014 -#define P_HHI_GP_PLL_CNTL5 CBUS_REG_ADDR(HHI_GP_PLL_CNTL5) -/**/ -#define HHI_DADC_CNTL 0x1027 -#define P_HHI_DADC_CNTL CBUS_REG_ADDR(HHI_DADC_CNTL) -#define HHI_DADC_CNTL2 0x1028 -#define P_HHI_DADC_CNTL2 CBUS_REG_ADDR(HHI_DADC_CNTL2) -#define HHI_DADC_RDBK0_I 0x1029 -#define P_HHI_DADC_RDBK0_I CBUS_REG_ADDR(HHI_DADC_RDBK0_I) -#define HHI_DADC_CNTL3 0x102a -#define P_HHI_DADC_CNTL3 CBUS_REG_ADDR(HHI_DADC_CNTL3) -#define HHI_DADC_CNTL4 0x102b -#define P_HHI_DADC_CNTL4 CBUS_REG_ADDR(HHI_DADC_CNTL4) - - -#define HARM_ASB_MB0 0x1030 -#define P_HARM_ASB_MB0 CBUS_REG_ADDR(HARM_ASB_MB0) -#define HARM_ASB_MB1 0x1031 -#define P_HARM_ASB_MB1 CBUS_REG_ADDR(HARM_ASB_MB1) -#define HARM_ASB_MB2 0x1032 -#define P_HARM_ASB_MB2 CBUS_REG_ADDR(HARM_ASB_MB2) -#define HARM_ASB_MB3 0x1033 -#define P_HARM_ASB_MB3 CBUS_REG_ADDR(HARM_ASB_MB3) -#define HASB_ARM_MB0 0x1034 -#define P_HASB_ARM_MB0 CBUS_REG_ADDR(HASB_ARM_MB0) -#define HASB_ARM_MB1 0x1035 -#define P_HASB_ARM_MB1 CBUS_REG_ADDR(HASB_ARM_MB1) -#define HASB_ARM_MB2 0x1036 -#define P_HASB_ARM_MB2 CBUS_REG_ADDR(HASB_ARM_MB2) -#define HASB_ARM_MB3 0x1037 -#define P_HASB_ARM_MB3 CBUS_REG_ADDR(HASB_ARM_MB3) -#define HHI_TIMER90K 0x103b -#define P_HHI_TIMER90K CBUS_REG_ADDR(HHI_TIMER90K) -#define HHI_MEM_PD_REG0 0x1040 -#define P_HHI_MEM_PD_REG0 CBUS_REG_ADDR(HHI_MEM_PD_REG0) -#define HHI_VPU_MEM_PD_REG0 0x1041 -#define P_HHI_VPU_MEM_PD_REG0 CBUS_REG_ADDR(HHI_VPU_MEM_PD_REG0) -#define HHI_VPU_MEM_PD_REG1 0x1042 -#define P_HHI_VPU_MEM_PD_REG1 CBUS_REG_ADDR(HHI_VPU_MEM_PD_REG1) -#define HHI_AUD_DAC_CTRL 0x1044 -#define P_HHI_AUD_DAC_CTRL CBUS_REG_ADDR(HHI_AUD_DAC_CTRL) -#define HHI_VIID_CLK_DIV 0x104a -#define P_HHI_VIID_CLK_DIV CBUS_REG_ADDR(HHI_VIID_CLK_DIV) -#define HHI_VIID_CLK_CNTL 0x104b -#define P_HHI_VIID_CLK_CNTL CBUS_REG_ADDR(HHI_VIID_CLK_CNTL) -#define HHI_VIID_DIVIDER_CNTL 0x104c -#define P_HHI_VIID_DIVIDER_CNTL \ - CBUS_REG_ADDR(HHI_VIID_DIVIDER_CNTL) -#define HHI_GCLK_MPEG0 0x1050 -#define P_HHI_GCLK_MPEG0 CBUS_REG_ADDR(HHI_GCLK_MPEG0) -#define HHI_GCLK_MPEG1 0x1051 -#define P_HHI_GCLK_MPEG1 CBUS_REG_ADDR(HHI_GCLK_MPEG1) -#define HHI_GCLK_MPEG2 0x1052 -#define P_HHI_GCLK_MPEG2 CBUS_REG_ADDR(HHI_GCLK_MPEG2) -#define HHI_GCLK_OTHER 0x1054 -#define P_HHI_GCLK_OTHER CBUS_REG_ADDR(HHI_GCLK_OTHER) -#define HHI_GCLK_AO 0x1055 -#define P_HHI_GCLK_AO CBUS_REG_ADDR(HHI_GCLK_AO) -#define HHI_SYS_CPU_CLK_CNTL1 0x1057 -#define P_HHI_SYS_CPU_CLK_CNTL1 \ - CBUS_REG_ADDR(HHI_SYS_CPU_CLK_CNTL1) -#define HHI_VID_CLK_DIV 0x1059 -#define P_HHI_VID_CLK_DIV CBUS_REG_ADDR(HHI_VID_CLK_DIV) -#define HHI_MPEG_CLK_CNTL 0x105d -#define P_HHI_MPEG_CLK_CNTL CBUS_REG_ADDR(HHI_MPEG_CLK_CNTL) -#define HHI_AUD_CLK_CNTL 0x105e -#define P_HHI_AUD_CLK_CNTL CBUS_REG_ADDR(HHI_AUD_CLK_CNTL) -#define HHI_VID_CLK_CNTL 0x105f -#define P_HHI_VID_CLK_CNTL CBUS_REG_ADDR(HHI_VID_CLK_CNTL) -#define HHI_WIFI_CLK_CNTL 0x1060 -#define P_HHI_WIFI_CLK_CNTL CBUS_REG_ADDR(HHI_WIFI_CLK_CNTL) -#define HHI_WIFI_PLL_CNTL 0x1061 -#define P_HHI_WIFI_PLL_CNTL CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL) -#define HHI_WIFI_PLL_CNTL2 0x1062 -#define P_HHI_WIFI_PLL_CNTL2 CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL2) -#define HHI_WIFI_PLL_CNTL3 0x1063 -#define P_HHI_WIFI_PLL_CNTL3 CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL3) -#define HHI_AUD_CLK_CNTL2 0x1064 -#define P_HHI_AUD_CLK_CNTL2 CBUS_REG_ADDR(HHI_AUD_CLK_CNTL2) -/*add from M8m2*/ -#define HHI_VID_CLK_CNTL2 0x1065 -#define P_HHI_VID_CLK_CNTL2 CBUS_REG_ADDR(HHI_VID_CLK_CNTL2) -/**/ -#define HHI_VID_DIVIDER_CNTL 0x1066 -#define P_HHI_VID_DIVIDER_CNTL CBUS_REG_ADDR(HHI_VID_DIVIDER_CNTL) -#define HHI_SYS_CPU_CLK_CNTL 0x1067 -#define P_HHI_SYS_CPU_CLK_CNTL CBUS_REG_ADDR(HHI_SYS_CPU_CLK_CNTL) -#define HHI_MALI_CLK_CNTL 0x106c -#define P_HHI_MALI_CLK_CNTL CBUS_REG_ADDR(HHI_MALI_CLK_CNTL) -#define HHI_MIPI_PHY_CLK_CNTL 0x106e -#define P_HHI_MIPI_PHY_CLK_CNTL \ - CBUS_REG_ADDR(HHI_MIPI_PHY_CLK_CNTL) -#define HHI_VPU_CLK_CNTL 0x106f -#define P_HHI_VPU_CLK_CNTL CBUS_REG_ADDR(HHI_VPU_CLK_CNTL) -#define HHI_OTHER_PLL_CNTL 0x1070 -#define P_HHI_OTHER_PLL_CNTL CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL) -#define HHI_OTHER_PLL_CNTL2 0x1071 -#define P_HHI_OTHER_PLL_CNTL2 CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL2) -#define HHI_OTHER_PLL_CNTL3 0x1072 -#define P_HHI_OTHER_PLL_CNTL3 CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL3) -#define HHI_HDMI_CLK_CNTL 0x1073 -#define P_HHI_HDMI_CLK_CNTL CBUS_REG_ADDR(HHI_HDMI_CLK_CNTL) -#define HHI_DEMOD_CLK_CNTL 0x1074 -#define P_HHI_DEMOD_CLK_CNTL CBUS_REG_ADDR(HHI_DEMOD_CLK_CNTL) -#define HHI_SATA_CLK_CNTL 0x1075 -#define P_HHI_SATA_CLK_CNTL CBUS_REG_ADDR(HHI_SATA_CLK_CNTL) -#define HHI_ETH_CLK_CNTL 0x1076 -#define P_HHI_ETH_CLK_CNTL CBUS_REG_ADDR(HHI_ETH_CLK_CNTL) -#define HHI_CLK_DOUBLE_CNTL 0x1077 -#define P_HHI_CLK_DOUBLE_CNTL CBUS_REG_ADDR(HHI_CLK_DOUBLE_CNTL) -#define HHI_VDEC_CLK_CNTL 0x1078 -#define P_HHI_VDEC_CLK_CNTL CBUS_REG_ADDR(HHI_VDEC_CLK_CNTL) -#define HHI_VDEC2_CLK_CNTL 0x1079 -#define P_HHI_VDEC2_CLK_CNTL CBUS_REG_ADDR(HHI_VDEC2_CLK_CNTL) -/*add from M8M2*/ -#define HHI_VDEC3_CLK_CNTL 0x107a -#define P_HHI_VDEC3_CLK_CNTL CBUS_REG_ADDR(HHI_VDEC3_CLK_CNTL) -#define HHI_VDEC4_CLK_CNTL 0x107b -#define P_HHI_VDEC4_CLK_CNTL CBUS_REG_ADDR(HHI_VDEC4_CLK_CNTL) -/**/ -#define HHI_HDMI_PLL_CNTL 0x107c -#define P_HHI_HDMI_PLL_CNTL CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL) -#define HHI_HDMI_PLL_CNTL1 0x107d -#define P_HHI_HDMI_PLL_CNTL1 CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL1) -#define HHI_HDMI_PLL_CNTL2 0x107e -#define P_HHI_HDMI_PLL_CNTL2 CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL2) -#define HHI_HDMI_AFC_CNTL 0x107f -#define P_HHI_HDMI_AFC_CNTL CBUS_REG_ADDR(HHI_HDMI_AFC_CNTL) -#define HHI_HDMIRX_CLK_CNTL 0x1080 -#define P_HHI_HDMIRX_CLK_CNTL CBUS_REG_ADDR(HHI_HDMIRX_CLK_CNTL) -#define HHI_HDMIRX_AUD_CLK_CNTL 0x1081 -#define P_HHI_HDMIRX_AUD_CLK_CNTL \ - CBUS_REG_ADDR(HHI_HDMIRX_AUD_CLK_CNTL) -/*M8 M8M2 diff*/ -#define HHI_EDP_APB_CLK_CNTL_M8M2 0x1082 -#define HHI_EDP_APB_CLK_CNTL 0x107b -#define P_HHI_EDP_APB_CLK_CNTL CBUS_REG_ADDR(HHI_EDP_APB_CLK_CNTL) -#define P_HHI_EDP_APB_CLK_CNTL_M8M2 \ - CBUS_REG_ADDR(HHI_EDP_APB_CLK_CNTL_M8M2) -/**/ -#define HHI_VID_PLL_MOD_CNTL0 0x1084 -#define P_HHI_VID_PLL_MOD_CNTL0 \ - CBUS_REG_ADDR(HHI_VID_PLL_MOD_CNTL0) -#define HHI_VID_PLL_MOD_LOW_TCNT 0x1085 -#define P_HHI_VID_PLL_MOD_LOW_TCNT \ - CBUS_REG_ADDR(HHI_VID_PLL_MOD_LOW_TCNT) -#define HHI_VID_PLL_MOD_HIGH_TCNT 0x1086 -#define P_HHI_VID_PLL_MOD_HIGH_TCNT \ - CBUS_REG_ADDR(HHI_VID_PLL_MOD_HIGH_TCNT) -#define HHI_VID_PLL_MOD_NOM_TCNT 0x1087 -#define P_HHI_VID_PLL_MOD_NOM_TCNT \ - CBUS_REG_ADDR(HHI_VID_PLL_MOD_NOM_TCNT) -#define HHI_USB_CLK_CNTL 0x1089 -#define P_HHI_USB_CLK_CNTL CBUS_REG_ADDR(HHI_USB_CLK_CNTL) -#define HHI_GEN_CLK_CNTL 0x108a -#define P_HHI_GEN_CLK_CNTL CBUS_REG_ADDR(HHI_GEN_CLK_CNTL) -#define HHI_GEN_CLK_CNTL2 0x108b -#define P_HHI_GEN_CLK_CNTL2 CBUS_REG_ADDR(HHI_GEN_CLK_CNTL2) -#define HHI_JTAG_CONFIG 0x108e -#define P_HHI_JTAG_CONFIG CBUS_REG_ADDR(HHI_JTAG_CONFIG) -#define HHI_VAFE_CLKXTALIN_CNTL 0x108f -#define P_HHI_VAFE_CLKXTALIN_CNTL \ - CBUS_REG_ADDR(HHI_VAFE_CLKXTALIN_CNTL) -#define HHI_VAFE_CLKOSCIN_CNTL 0x1090 -#define P_HHI_VAFE_CLKOSCIN_CNTL \ - CBUS_REG_ADDR(HHI_VAFE_CLKOSCIN_CNTL) -#define HHI_VAFE_CLKIN_CNTL 0x1091 -#define P_HHI_VAFE_CLKIN_CNTL CBUS_REG_ADDR(HHI_VAFE_CLKIN_CNTL) -#define HHI_TVFE_AUTOMODE_CLK_CNTL 0x1092 -#define P_HHI_TVFE_AUTOMODE_CLK_CNTL \ - CBUS_REG_ADDR(HHI_TVFE_AUTOMODE_CLK_CNTL) -#define HHI_VAFE_CLKPI_CNTL 0x1093 -#define P_HHI_VAFE_CLKPI_CNTL CBUS_REG_ADDR(HHI_VAFE_CLKPI_CNTL) -#define HHI_VDIN_MEAS_CLK_CNTL 0x1094 -#define HHI_PCM2_CLK_CNTL 0x1095 -#define P_HHI_PCM2_CLK_CNTL CBUS_REG_ADDR(HHI_PCM2_CLK_CNTL) -#define HHI_PCM_CLK_CNTL 0x1096 -#define P_HHI_PCM_CLK_CNTL CBUS_REG_ADDR(HHI_PCM_CLK_CNTL) -#define HHI_NAND_CLK_CNTL 0x1097 -#define P_HHI_NAND_CLK_CNTL CBUS_REG_ADDR(HHI_NAND_CLK_CNTL) -#define HHI_ISP_LED_CLK_CNTL 0x1098 -#define P_HHI_ISP_LED_CLK_CNTL CBUS_REG_ADDR(HHI_ISP_LED_CLK_CNTL) -#define HHI_EDP_TX_PHY_CNTL0 0x109c -#define P_HHI_EDP_TX_PHY_CNTL0 CBUS_REG_ADDR(HHI_EDP_TX_PHY_CNTL0) -#define HHI_EDP_TX_PHY_CNTL1 0x109d -#define P_HHI_EDP_TX_PHY_CNTL1 CBUS_REG_ADDR(HHI_EDP_TX_PHY_CNTL1) -#define HHI_MPLL_CNTL 0x10a0 -#define P_HHI_MPLL_CNTL CBUS_REG_ADDR(HHI_MPLL_CNTL) -#define HHI_MPLL_CNTL2 0x10a1 -#define P_HHI_MPLL_CNTL2 CBUS_REG_ADDR(HHI_MPLL_CNTL2) -#define HHI_MPLL_CNTL3 0x10a2 -#define P_HHI_MPLL_CNTL3 CBUS_REG_ADDR(HHI_MPLL_CNTL3) -#define HHI_MPLL_CNTL4 0x10a3 -#define P_HHI_MPLL_CNTL4 CBUS_REG_ADDR(HHI_MPLL_CNTL4) -#define HHI_MPLL_CNTL5 0x10a4 -#define P_HHI_MPLL_CNTL5 CBUS_REG_ADDR(HHI_MPLL_CNTL5) -#define HHI_MPLL_CNTL6 0x10a5 -#define P_HHI_MPLL_CNTL6 CBUS_REG_ADDR(HHI_MPLL_CNTL6) -#define HHI_MPLL_CNTL7 0x10a6 -#define P_HHI_MPLL_CNTL7 CBUS_REG_ADDR(HHI_MPLL_CNTL7) -#define HHI_MPLL_CNTL8 0x10a7 -#define P_HHI_MPLL_CNTL8 CBUS_REG_ADDR(HHI_MPLL_CNTL8) -#define HHI_MPLL_CNTL9 0x10a8 -#define P_HHI_MPLL_CNTL9 CBUS_REG_ADDR(HHI_MPLL_CNTL9) -#define HHI_MPLL_CNTL10 0x10a9 -#define P_HHI_MPLL_CNTL10 CBUS_REG_ADDR(HHI_MPLL_CNTL10) - - -#define HHI_ADC_PLL_CNTL 0x10aa -#define P_HHI_ADC_PLL_CNTL CBUS_REG_ADDR(HHI_ADC_PLL_CNTL) -#define HHI_ADC_PLL_CNTL2 0x10ab -#define P_HHI_ADC_PLL_CNTL2 CBUS_REG_ADDR(HHI_ADC_PLL_CNTL2) -#define HHI_ADC_PLL_CNTL3 0x10ac -#define P_HHI_ADC_PLL_CNTL3 CBUS_REG_ADDR(HHI_ADC_PLL_CNTL3) -#define HHI_ADC_PLL_CNTL4 0x10ad -#define P_HHI_ADC_PLL_CNTL4 CBUS_REG_ADDR(HHI_ADC_PLL_CNTL4) -#define HHI_ADC_PLL_CNTL5 0x109e -#define P_HHI_ADC_PLL_CNTL5 CBUS_REG_ADDR(HHI_ADC_PLL_CNTL5) -#define HHI_ADC_PLL_CNTL6 0x109f -#define P_HHI_ADC_PLL_CNTL6 CBUS_REG_ADDR(HHI_ADC_PLL_CNTL6) -#define HHI_ADC_PLL_CNTL1 0x10af -#define P_HHI_ADC_PLL_CNTL1 CBUS_REG_ADDR(HHI_ADC_PLL_CNTL1) - - -#define HHI_AUDCLK_PLL_CNTL 0x10b0 -#define P_HHI_AUDCLK_PLL_CNTL CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL) -#define HHI_AUDCLK_PLL_CNTL2 0x10b1 -#define P_HHI_AUDCLK_PLL_CNTL2 CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL2) -#define HHI_AUDCLK_PLL_CNTL3 0x10b2 -#define P_HHI_AUDCLK_PLL_CNTL3 CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL3) -#define HHI_AUDCLK_PLL_CNTL4 0x10b3 -#define P_HHI_AUDCLK_PLL_CNTL4 CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL4) -#define HHI_AUDCLK_PLL_CNTL5 0x10b4 -#define P_HHI_AUDCLK_PLL_CNTL5 CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL5) -#define HHI_AUDCLK_PLL_CNTL6 0x10b5 -#define P_HHI_AUDCLK_PLL_CNTL6 CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL6) -#define HHI_L2_DDR_CLK_CNTL 0x10b6 -#define P_HHI_L2_DDR_CLK_CNTL CBUS_REG_ADDR(HHI_L2_DDR_CLK_CNTL) -#define HHI_VDAC_CNTL0 0x10bd -#define P_HHI_VDAC_CNTL0 CBUS_REG_ADDR(HHI_VDAC_CNTL0) -#define HHI_VDAC_CNTL1 0x10be -#define P_HHI_VDAC_CNTL1 CBUS_REG_ADDR(HHI_VDAC_CNTL1) -#define HHI_SYS_PLL_CNTL 0x10c0 -#define P_HHI_SYS_PLL_CNTL CBUS_REG_ADDR(HHI_SYS_PLL_CNTL) -#define HHI_SYS_PLL_CNTL2 0x10c1 -#define P_HHI_SYS_PLL_CNTL2 CBUS_REG_ADDR(HHI_SYS_PLL_CNTL2) -#define HHI_SYS_PLL_CNTL3 0x10c2 -#define P_HHI_SYS_PLL_CNTL3 CBUS_REG_ADDR(HHI_SYS_PLL_CNTL3) -#define HHI_SYS_PLL_CNTL4 0x10c3 -#define P_HHI_SYS_PLL_CNTL4 CBUS_REG_ADDR(HHI_SYS_PLL_CNTL4) -#define HHI_SYS_PLL_CNTL5 0x10c4 -#define P_HHI_SYS_PLL_CNTL5 CBUS_REG_ADDR(HHI_SYS_PLL_CNTL5) -#define HHI_DPLL_TOP_0 0x10c6 -#define P_HHI_DPLL_TOP_0 CBUS_REG_ADDR(HHI_DPLL_TOP_0) -#define HHI_DPLL_TOP_1 0x10c7 -#define P_HHI_DPLL_TOP_1 CBUS_REG_ADDR(HHI_DPLL_TOP_1) -#define HHI_VID_PLL_CNTL 0x10c8 -#define P_HHI_VID_PLL_CNTL CBUS_REG_ADDR(HHI_VID_PLL_CNTL) -#define HHI_VID_PLL_CNTL2 0x10c9 -#define P_HHI_VID_PLL_CNTL2 CBUS_REG_ADDR(HHI_VID_PLL_CNTL2) -#define HHI_VID_PLL_CNTL3 0x10ca -#define P_HHI_VID_PLL_CNTL3 CBUS_REG_ADDR(HHI_VID_PLL_CNTL3) -#define HHI_VID_PLL_CNTL4 0x10cb -#define P_HHI_VID_PLL_CNTL4 CBUS_REG_ADDR(HHI_VID_PLL_CNTL4) -#define HHI_VID_PLL_CNTL5 0x10cc -#define P_HHI_VID_PLL_CNTL5 CBUS_REG_ADDR(HHI_VID_PLL_CNTL5) -#define HHI_VID_PLL_CNTL6 0x10cd -#define P_HHI_VID_PLL_CNTL6 CBUS_REG_ADDR(HHI_VID_PLL_CNTL6) -#define HHI_CSI_PHY_CNTL0 0x10d3 +/*no set*/ +#ifdef MESON_M8_CPU +#define HHI_CSI_PHY_CNTL0 (HHI_CSI_PHY_CNTL_BASE + 0xd3) #define P_HHI_CSI_PHY_CNTL0 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL0) -#define HHI_CSI_PHY_CNTL1 0x10d4 +#define HHI_CSI_PHY_CNTL1 (HHI_CSI_PHY_CNTL_BASE + 0xd4) #define P_HHI_CSI_PHY_CNTL1 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL1) -#define HHI_CSI_PHY_CNTL2 0x10d5 +#define HHI_CSI_PHY_CNTL2 (HHI_CSI_PHY_CNTL_BASE + 0xd5) #define P_HHI_CSI_PHY_CNTL2 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL2) -#define HHI_CSI_PHY_CNTL3 0x10d6 +#define HHI_CSI_PHY_CNTL3 (HHI_CSI_PHY_CNTL_BASE + 0xd6) #define P_HHI_CSI_PHY_CNTL3 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL3) -#define HHI_CSI_PHY_CNTL4 0x10d7 +#define HHI_CSI_PHY_CNTL4 (HHI_CSI_PHY_CNTL_BASE + 0xd7) #define P_HHI_CSI_PHY_CNTL4 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL4) -#define HHI_DIF_CSI_PHY_CNTL0 0x10d8 -#define P_HHI_DIF_CSI_PHY_CNTL0 \ - CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL0) -#define HHI_DIF_CSI_PHY_CNTL1 0x10d9 -#define P_HHI_DIF_CSI_PHY_CNTL1 \ - CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL1) -#define HHI_DIF_CSI_PHY_CNTL2 0x10da -#define P_HHI_DIF_CSI_PHY_CNTL2 \ - CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL2) -#define HHI_DIF_CSI_PHY_CNTL3 0x10db -#define P_HHI_DIF_CSI_PHY_CNTL3 \ - CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL3) -#define HHI_DIF_CSI_PHY_CNTL4 0x10dc -#define P_HHI_DIF_CSI_PHY_CNTL4 \ - CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL4) -#define HHI_DIF_CSI_PHY_CNTL5 0x10dd -#define P_HHI_DIF_CSI_PHY_CNTL5 \ - CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL5) -#define HHI_LVDS_TX_PHY_CNTL0 0x10de -#define P_HHI_LVDS_TX_PHY_CNTL0 \ - CBUS_REG_ADDR(HHI_LVDS_TX_PHY_CNTL0) -#define HHI_LVDS_TX_PHY_CNTL1 0x10df -#define P_HHI_LVDS_TX_PHY_CNTL1 \ - CBUS_REG_ADDR(HHI_LVDS_TX_PHY_CNTL1) -#define HHI_VID2_PLL_CNTL 0x10e0 -#define P_HHI_VID2_PLL_CNTL CBUS_REG_ADDR(HHI_VID2_PLL_CNTL) -#define HHI_VID2_PLL_CNTL2 0x10e1 -#define P_HHI_VID2_PLL_CNTL2 CBUS_REG_ADDR(HHI_VID2_PLL_CNTL2) -#define HHI_VID2_PLL_CNTL3 0x10e2 -#define P_HHI_VID2_PLL_CNTL3 CBUS_REG_ADDR(HHI_VID2_PLL_CNTL3) -#define HHI_VID2_PLL_CNTL4 0x10e3 -#define P_HHI_VID2_PLL_CNTL4 CBUS_REG_ADDR(HHI_VID2_PLL_CNTL4) -#define HHI_VID2_PLL_CNTL5 0x10e4 -#define P_HHI_VID2_PLL_CNTL5 CBUS_REG_ADDR(HHI_VID2_PLL_CNTL5) -#define HHI_VID2_PLL_CNTL6 0x10e5 -#define P_HHI_VID2_PLL_CNTL6 CBUS_REG_ADDR(HHI_VID2_PLL_CNTL6) -#define HHI_HDMI_PHY_CNTL0 0x10e8 -#define P_HHI_HDMI_PHY_CNTL0 CBUS_REG_ADDR(HHI_HDMI_PHY_CNTL0) -#define HHI_HDMI_PHY_CNTL1 0x10e9 -#define P_HHI_HDMI_PHY_CNTL1 CBUS_REG_ADDR(HHI_HDMI_PHY_CNTL1) -#define HHI_HDMI_PHY_CNTL2 0x10ea -#define P_HHI_HDMI_PHY_CNTL2 CBUS_REG_ADDR(HHI_HDMI_PHY_CNTL2) -#define PARSER_CONTROL 0x2960 -#define P_PARSER_CONTROL CBUS_REG_ADDR(PARSER_CONTROL) -#define PARSER_FETCH_ADDR 0x2961 -#define P_PARSER_FETCH_ADDR CBUS_REG_ADDR(PARSER_FETCH_ADDR) -#define PARSER_FETCH_CMD 0x2962 -#define P_PARSER_FETCH_CMD CBUS_REG_ADDR(PARSER_FETCH_CMD) -#define PARSER_FETCH_LEVEL 0x2964 -#define P_PARSER_FETCH_LEVEL CBUS_REG_ADDR(PARSER_FETCH_LEVEL) -#define PARSER_CONFIG 0x2965 -#define P_PARSER_CONFIG CBUS_REG_ADDR(PARSER_CONFIG) -#define PFIFO_WR_PTR 0x2966 -#define P_PFIFO_WR_PTR CBUS_REG_ADDR(PFIFO_WR_PTR) -#define PFIFO_RD_PTR 0x2967 -#define P_PFIFO_RD_PTR CBUS_REG_ADDR(PFIFO_RD_PTR) -#define PFIFO_DATA 0x2968 -#define P_PFIFO_DATA CBUS_REG_ADDR(PFIFO_DATA) -#define PARSER_SEARCH_PATTERN 0x2969 -#define P_PARSER_SEARCH_PATTERN \ - CBUS_REG_ADDR(PARSER_SEARCH_PATTERN) -#define PARSER_SEARCH_MASK 0x296a -#define P_PARSER_SEARCH_MASK CBUS_REG_ADDR(PARSER_SEARCH_MASK) -#define PARSER_INT_ENABLE 0x296b -#define P_PARSER_INT_ENABLE CBUS_REG_ADDR(PARSER_INT_ENABLE) -#define PARSER_INT_STATUS 0x296c -#define P_PARSER_INT_STATUS CBUS_REG_ADDR(PARSER_INT_STATUS) -#define PARSER_SCR_CTL 0x296d -#define P_PARSER_SCR_CTL CBUS_REG_ADDR(PARSER_SCR_CTL) -#define PARSER_SCR 0x296e -#define P_PARSER_SCR CBUS_REG_ADDR(PARSER_SCR) -#define PARSER_PARAMETER 0x296f -#define P_PARSER_PARAMETER CBUS_REG_ADDR(PARSER_PARAMETER) -#define PARSER_INSERT_DATA 0x2970 -#define P_PARSER_INSERT_DATA CBUS_REG_ADDR(PARSER_INSERT_DATA) -#define VAS_STREAM_ID 0x2971 -#define P_VAS_STREAM_ID CBUS_REG_ADDR(VAS_STREAM_ID) -#define VIDEO_DTS 0x2972 -#define P_VIDEO_DTS CBUS_REG_ADDR(VIDEO_DTS) -#define VIDEO_PTS 0x2973 -#define P_VIDEO_PTS CBUS_REG_ADDR(VIDEO_PTS) -#define VIDEO_PTS_DTS_WR_PTR 0x2974 -#define P_VIDEO_PTS_DTS_WR_PTR CBUS_REG_ADDR(VIDEO_PTS_DTS_WR_PTR) -#define AUDIO_PTS 0x2975 -#define P_AUDIO_PTS CBUS_REG_ADDR(AUDIO_PTS) -#define AUDIO_PTS_WR_PTR 0x2976 -#define P_AUDIO_PTS_WR_PTR CBUS_REG_ADDR(AUDIO_PTS_WR_PTR) -#define PARSER_ES_CONTROL 0x2977 -#define P_PARSER_ES_CONTROL CBUS_REG_ADDR(PARSER_ES_CONTROL) -#define PFIFO_MONITOR 0x2978 -#define P_PFIFO_MONITOR CBUS_REG_ADDR(PFIFO_MONITOR) -#define PARSER_VIDEO_START_PTR 0x2980 -#define P_PARSER_VIDEO_START_PTR \ - CBUS_REG_ADDR(PARSER_VIDEO_START_PTR) -#define PARSER_VIDEO_END_PTR 0x2981 -#define P_PARSER_VIDEO_END_PTR CBUS_REG_ADDR(PARSER_VIDEO_END_PTR) -#define PARSER_VIDEO_WP 0x2982 -#define P_PARSER_VIDEO_WP CBUS_REG_ADDR(PARSER_VIDEO_WP) -#define PARSER_VIDEO_RP 0x2983 -#define P_PARSER_VIDEO_RP CBUS_REG_ADDR(PARSER_VIDEO_RP) -#define PARSER_VIDEO_HOLE 0x2984 -#define P_PARSER_VIDEO_HOLE CBUS_REG_ADDR(PARSER_VIDEO_HOLE) -#define PARSER_AUDIO_START_PTR 0x2985 -#define P_PARSER_AUDIO_START_PTR \ - CBUS_REG_ADDR(PARSER_AUDIO_START_PTR) -#define PARSER_AUDIO_END_PTR 0x2986 -#define P_PARSER_AUDIO_END_PTR CBUS_REG_ADDR(PARSER_AUDIO_END_PTR) -#define PARSER_AUDIO_WP 0x2987 -#define P_PARSER_AUDIO_WP CBUS_REG_ADDR(PARSER_AUDIO_WP) -#define PARSER_AUDIO_RP 0x2988 -#define P_PARSER_AUDIO_RP CBUS_REG_ADDR(PARSER_AUDIO_RP) -#define PARSER_AUDIO_HOLE 0x2989 -#define P_PARSER_AUDIO_HOLE CBUS_REG_ADDR(PARSER_AUDIO_HOLE) -#define PARSER_SUB_START_PTR 0x298a +#endif + +#define PARSER_SUB_START_PTR (PARSER_SUB_START_PTR_BASE + 0x8a) #define P_PARSER_SUB_START_PTR CBUS_REG_ADDR(PARSER_SUB_START_PTR) -#define PARSER_SUB_END_PTR 0x298b +#define PARSER_SUB_END_PTR (PARSER_SUB_START_PTR_BASE + 0x8b) #define P_PARSER_SUB_END_PTR CBUS_REG_ADDR(PARSER_SUB_END_PTR) -#define PARSER_SUB_WP 0x298c +#define PARSER_SUB_WP (PARSER_SUB_START_PTR_BASE + 0x8c) #define P_PARSER_SUB_WP CBUS_REG_ADDR(PARSER_SUB_WP) -#define PARSER_SUB_RP 0x298d +#define PARSER_SUB_RP (PARSER_SUB_START_PTR_BASE + 0x8d) #define P_PARSER_SUB_RP CBUS_REG_ADDR(PARSER_SUB_RP) -#define PARSER_SUB_HOLE 0x298e -#define P_PARSER_SUB_HOLE CBUS_REG_ADDR(PARSER_SUB_HOLE) -#define PARSER_FETCH_INFO 0x298f -#define P_PARSER_FETCH_INFO CBUS_REG_ADDR(PARSER_FETCH_INFO) -#define PARSER_STATUS 0x2990 -#define P_PARSER_STATUS CBUS_REG_ADDR(PARSER_STATUS) -#define PARSER_AV_WRAP_COUNT 0x2991 -#define P_PARSER_AV_WRAP_COUNT CBUS_REG_ADDR(PARSER_AV_WRAP_COUNT) -#define WRRSP_PARSER 0x2992 -#define P_WRRSP_PARSER CBUS_REG_ADDR(WRRSP_PARSER) -#define PARSER_VIDEO2_START_PTR 0x2993 -#define P_PARSER_VIDEO2_START_PTR \ - CBUS_REG_ADDR(PARSER_VIDEO2_START_PTR) -#define PARSER_VIDEO2_END_PTR 0x2994 -#define P_PARSER_VIDEO2_END_PTR \ - CBUS_REG_ADDR(PARSER_VIDEO2_END_PTR) -#define PARSER_VIDEO2_WP 0x2995 -#define P_PARSER_VIDEO2_WP CBUS_REG_ADDR(PARSER_VIDEO2_WP) -#define PARSER_VIDEO2_RP 0x2996 -#define P_PARSER_VIDEO2_RP CBUS_REG_ADDR(PARSER_VIDEO2_RP) -#define PARSER_VIDEO2_HOLE 0x2997 -#define P_PARSER_VIDEO2_HOLE CBUS_REG_ADDR(PARSER_VIDEO2_HOLE) -#define PARSER_AV2_WRAP_COUNT 0x2998 -#define P_PARSER_AV2_WRAP_COUNT \ - CBUS_REG_ADDR(PARSER_AV2_WRAP_COUNT) -#define DVIN_FRONT_END_CTRL 0x12e0 -#define P_DVIN_FRONT_END_CTRL CBUS_REG_ADDR(DVIN_FRONT_END_CTRL) -#define DVIN_HS_LEAD_VS_ODD 0x12e1 -#define P_DVIN_HS_LEAD_VS_ODD CBUS_REG_ADDR(DVIN_HS_LEAD_VS_ODD) -#define DVIN_ACTIVE_START_PIX 0x12e2 -#define P_DVIN_ACTIVE_START_PIX \ - CBUS_REG_ADDR(DVIN_ACTIVE_START_PIX) -#define DVIN_ACTIVE_START_LINE 0x12e3 -#define P_DVIN_ACTIVE_START_LINE \ - CBUS_REG_ADDR(DVIN_ACTIVE_START_LINE) -#define DVIN_DISPLAY_SIZE 0x12e4 -#define P_DVIN_DISPLAY_SIZE CBUS_REG_ADDR(DVIN_DISPLAY_SIZE) -#define DVIN_CTRL_STAT 0x12e5 -#define P_DVIN_CTRL_STAT CBUS_REG_ADDR(DVIN_CTRL_STAT) -#define AIU_958_BPF 0x1500 -#define P_AIU_958_BPF CBUS_REG_ADDR(AIU_958_BPF) -#define AIU_958_BRST 0x1501 -#define P_AIU_958_BRST CBUS_REG_ADDR(AIU_958_BRST) -#define AIU_958_LENGTH 0x1502 -#define P_AIU_958_LENGTH CBUS_REG_ADDR(AIU_958_LENGTH) -#define AIU_958_PADDSIZE 0x1503 -#define P_AIU_958_PADDSIZE CBUS_REG_ADDR(AIU_958_PADDSIZE) -#define AIU_958_MISC 0x1504 -#define P_AIU_958_MISC CBUS_REG_ADDR(AIU_958_MISC) -#define AIU_958_FORCE_LEFT 0x1505 -#define P_AIU_958_FORCE_LEFT CBUS_REG_ADDR(AIU_958_FORCE_LEFT) -#define AIU_958_DISCARD_NUM 0x1506 -#define P_AIU_958_DISCARD_NUM CBUS_REG_ADDR(AIU_958_DISCARD_NUM) -#define AIU_958_DCU_FF_CTRL 0x1507 -#define P_AIU_958_DCU_FF_CTRL CBUS_REG_ADDR(AIU_958_DCU_FF_CTRL) -#define AIU_958_CHSTAT_L0 0x1508 -#define P_AIU_958_CHSTAT_L0 CBUS_REG_ADDR(AIU_958_CHSTAT_L0) -#define AIU_958_CHSTAT_L1 0x1509 -#define P_AIU_958_CHSTAT_L1 CBUS_REG_ADDR(AIU_958_CHSTAT_L1) -#define AIU_958_CTRL 0x150a -#define P_AIU_958_CTRL CBUS_REG_ADDR(AIU_958_CTRL) -#define AIU_958_RPT 0x150b -#define P_AIU_958_RPT CBUS_REG_ADDR(AIU_958_RPT) -#define AIU_I2S_MUTE_SWAP 0x150c -#define P_AIU_I2S_MUTE_SWAP CBUS_REG_ADDR(AIU_I2S_MUTE_SWAP) -#define AIU_I2S_SOURCE_DESC 0x150d -#define P_AIU_I2S_SOURCE_DESC CBUS_REG_ADDR(AIU_I2S_SOURCE_DESC) -#define AIU_I2S_MED_CTRL 0x150e -#define P_AIU_I2S_MED_CTRL CBUS_REG_ADDR(AIU_I2S_MED_CTRL) -#define AIU_I2S_MED_THRESH 0x150f -#define P_AIU_I2S_MED_THRESH CBUS_REG_ADDR(AIU_I2S_MED_THRESH) -#define AIU_I2S_DAC_CFG 0x1510 -#define P_AIU_I2S_DAC_CFG CBUS_REG_ADDR(AIU_I2S_DAC_CFG) -#define AIU_I2S_SYNC 0x1511 -#define P_AIU_I2S_SYNC CBUS_REG_ADDR(AIU_I2S_SYNC) -#define AIU_I2S_MISC 0x1512 -#define P_AIU_I2S_MISC CBUS_REG_ADDR(AIU_I2S_MISC) -#define AIU_I2S_OUT_CFG 0x1513 -#define P_AIU_I2S_OUT_CFG CBUS_REG_ADDR(AIU_I2S_OUT_CFG) -#define AIU_I2S_FF_CTRL 0x1514 -#define P_AIU_I2S_FF_CTRL CBUS_REG_ADDR(AIU_I2S_FF_CTRL) -#define AIU_RST_SOFT 0x1515 -#define P_AIU_RST_SOFT CBUS_REG_ADDR(AIU_RST_SOFT) -#define AIU_CLK_CTRL 0x1516 -#define P_AIU_CLK_CTRL CBUS_REG_ADDR(AIU_CLK_CTRL) -#define AIU_MIX_ADCCFG 0x1517 -#define P_AIU_MIX_ADCCFG CBUS_REG_ADDR(AIU_MIX_ADCCFG) -#define AIU_MIX_CTRL 0x1518 -#define P_AIU_MIX_CTRL CBUS_REG_ADDR(AIU_MIX_CTRL) -#define AIU_CLK_CTRL_MORE 0x1519 -#define P_AIU_CLK_CTRL_MORE CBUS_REG_ADDR(AIU_CLK_CTRL_MORE) -#define AIU_958_POP 0x151a -#define P_AIU_958_POP CBUS_REG_ADDR(AIU_958_POP) -#define AIU_MIX_GAIN 0x151b -#define P_AIU_MIX_GAIN CBUS_REG_ADDR(AIU_MIX_GAIN) -#define AIU_958_SYNWORD1 0x151c -#define P_AIU_958_SYNWORD1 CBUS_REG_ADDR(AIU_958_SYNWORD1) -#define AIU_958_SYNWORD2 0x151d -#define P_AIU_958_SYNWORD2 CBUS_REG_ADDR(AIU_958_SYNWORD2) -#define AIU_958_SYNWORD3 0x151e -#define P_AIU_958_SYNWORD3 CBUS_REG_ADDR(AIU_958_SYNWORD3) -#define AIU_958_SYNWORD1_MASK 0x151f -#define P_AIU_958_SYNWORD1_MASK \ - CBUS_REG_ADDR(AIU_958_SYNWORD1_MASK) -#define AIU_958_SYNWORD2_MASK 0x1520 -#define P_AIU_958_SYNWORD2_MASK \ - CBUS_REG_ADDR(AIU_958_SYNWORD2_MASK) -#define AIU_958_SYNWORD3_MASK 0x1521 -#define P_AIU_958_SYNWORD3_MASK \ - CBUS_REG_ADDR(AIU_958_SYNWORD3_MASK) -#define AIU_958_FFRDOUT_THD 0x1522 -#define P_AIU_958_FFRDOUT_THD CBUS_REG_ADDR(AIU_958_FFRDOUT_THD) -#define AIU_958_LENGTH_PER_PAUSE 0x1523 -#define P_AIU_958_LENGTH_PER_PAUSE \ - CBUS_REG_ADDR(AIU_958_LENGTH_PER_PAUSE) -#define AIU_958_PAUSE_NUM 0x1524 -#define P_AIU_958_PAUSE_NUM CBUS_REG_ADDR(AIU_958_PAUSE_NUM) -#define AIU_958_PAUSE_PAYLOAD 0x1525 -#define P_AIU_958_PAUSE_PAYLOAD \ - CBUS_REG_ADDR(AIU_958_PAUSE_PAYLOAD) -#define AIU_958_AUTO_PAUSE 0x1526 -#define P_AIU_958_AUTO_PAUSE CBUS_REG_ADDR(AIU_958_AUTO_PAUSE) -#define AIU_958_PAUSE_PD_LENGTH 0x1527 -#define P_AIU_958_PAUSE_PD_LENGTH \ - CBUS_REG_ADDR(AIU_958_PAUSE_PD_LENGTH) -#define AIU_CODEC_DAC_LRCLK_CTRL 0x1528 -#define P_AIU_CODEC_DAC_LRCLK_CTRL \ - CBUS_REG_ADDR(AIU_CODEC_DAC_LRCLK_CTRL) -#define AIU_CODEC_ADC_LRCLK_CTRL 0x1529 -#define P_AIU_CODEC_ADC_LRCLK_CTRL \ - CBUS_REG_ADDR(AIU_CODEC_ADC_LRCLK_CTRL) -#define AIU_CODEC_CLK_DATA_CTRL 0x152b -#define P_AIU_CODEC_CLK_DATA_CTRL \ - CBUS_REG_ADDR(AIU_CODEC_CLK_DATA_CTRL) -#define AIU_958_CHSTAT_R0 0x1530 -#define P_AIU_958_CHSTAT_R0 CBUS_REG_ADDR(AIU_958_CHSTAT_R0) -#define AIU_958_CHSTAT_R1 0x1531 -#define P_AIU_958_CHSTAT_R1 CBUS_REG_ADDR(AIU_958_CHSTAT_R1) -#define AIU_958_VALID_CTRL 0x1532 -#define P_AIU_958_VALID_CTRL CBUS_REG_ADDR(AIU_958_VALID_CTRL) -#define AIU_AUDIO_AMP_REG0 0x153c -#define P_AIU_AUDIO_AMP_REG0 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG0) -#define AIU_AUDIO_AMP_REG1 0x153d -#define P_AIU_AUDIO_AMP_REG1 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG1) -#define AIU_AUDIO_AMP_REG2 0x153e -#define P_AIU_AUDIO_AMP_REG2 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG2) -#define AIU_AUDIO_AMP_REG3 0x153f -#define P_AIU_AUDIO_AMP_REG3 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG3) -#define AIU_AIFIFO2_CTRL 0x1540 -#define P_AIU_AIFIFO2_CTRL CBUS_REG_ADDR(AIU_AIFIFO2_CTRL) -#define AIU_AIFIFO2_STATUS 0x1541 -#define P_AIU_AIFIFO2_STATUS CBUS_REG_ADDR(AIU_AIFIFO2_STATUS) -#define AIU_AIFIFO2_GBIT 0x1542 -#define P_AIU_AIFIFO2_GBIT CBUS_REG_ADDR(AIU_AIFIFO2_GBIT) -#define AIU_AIFIFO2_CLB 0x1543 -#define P_AIU_AIFIFO2_CLB CBUS_REG_ADDR(AIU_AIFIFO2_CLB) -#define AIU_CRC_CTRL 0x1544 -#define P_AIU_CRC_CTRL CBUS_REG_ADDR(AIU_CRC_CTRL) -#define AIU_CRC_STATUS 0x1545 -#define P_AIU_CRC_STATUS CBUS_REG_ADDR(AIU_CRC_STATUS) -#define AIU_CRC_SHIFT_REG 0x1546 -#define P_AIU_CRC_SHIFT_REG CBUS_REG_ADDR(AIU_CRC_SHIFT_REG) -#define AIU_CRC_IREG 0x1547 -#define P_AIU_CRC_IREG CBUS_REG_ADDR(AIU_CRC_IREG) -#define AIU_CRC_CAL_REG1 0x1548 -#define P_AIU_CRC_CAL_REG1 CBUS_REG_ADDR(AIU_CRC_CAL_REG1) -#define AIU_CRC_CAL_REG0 0x1549 -#define P_AIU_CRC_CAL_REG0 CBUS_REG_ADDR(AIU_CRC_CAL_REG0) -#define AIU_CRC_POLY_COEF1 0x154a -#define P_AIU_CRC_POLY_COEF1 CBUS_REG_ADDR(AIU_CRC_POLY_COEF1) -#define AIU_CRC_POLY_COEF0 0x154b -#define P_AIU_CRC_POLY_COEF0 CBUS_REG_ADDR(AIU_CRC_POLY_COEF0) -#define AIU_CRC_BIT_SIZE1 0x154c -#define P_AIU_CRC_BIT_SIZE1 CBUS_REG_ADDR(AIU_CRC_BIT_SIZE1) -#define AIU_CRC_BIT_SIZE0 0x154d -#define P_AIU_CRC_BIT_SIZE0 CBUS_REG_ADDR(AIU_CRC_BIT_SIZE0) -#define AIU_CRC_BIT_CNT1 0x154e -#define P_AIU_CRC_BIT_CNT1 CBUS_REG_ADDR(AIU_CRC_BIT_CNT1) -#define AIU_CRC_BIT_CNT0 0x154f -#define P_AIU_CRC_BIT_CNT0 CBUS_REG_ADDR(AIU_CRC_BIT_CNT0) -#define AIU_AMCLK_GATE_HI 0x1550 -#define P_AIU_AMCLK_GATE_HI CBUS_REG_ADDR(AIU_AMCLK_GATE_HI) -#define AIU_AMCLK_GATE_LO 0x1551 -#define P_AIU_AMCLK_GATE_LO CBUS_REG_ADDR(AIU_AMCLK_GATE_LO) -#define AIU_AMCLK_MSR 0x1552 -#define P_AIU_AMCLK_MSR CBUS_REG_ADDR(AIU_AMCLK_MSR) -#define AIU_AUDAC_CTRL0 0x1553 -#define P_AIU_AUDAC_CTRL0 CBUS_REG_ADDR(AIU_AUDAC_CTRL0) -#define AIU_DELTA_SIGMA0 0x1555 -#define P_AIU_DELTA_SIGMA0 CBUS_REG_ADDR(AIU_DELTA_SIGMA0) -#define AIU_DELTA_SIGMA1 0x1556 -#define P_AIU_DELTA_SIGMA1 CBUS_REG_ADDR(AIU_DELTA_SIGMA1) -#define AIU_DELTA_SIGMA2 0x1557 -#define P_AIU_DELTA_SIGMA2 CBUS_REG_ADDR(AIU_DELTA_SIGMA2) -#define AIU_DELTA_SIGMA3 0x1558 -#define P_AIU_DELTA_SIGMA3 CBUS_REG_ADDR(AIU_DELTA_SIGMA3) -#define AIU_DELTA_SIGMA4 0x1559 -#define P_AIU_DELTA_SIGMA4 CBUS_REG_ADDR(AIU_DELTA_SIGMA4) -#define AIU_DELTA_SIGMA5 0x155a -#define P_AIU_DELTA_SIGMA5 CBUS_REG_ADDR(AIU_DELTA_SIGMA5) -#define AIU_DELTA_SIGMA6 0x155b -#define P_AIU_DELTA_SIGMA6 CBUS_REG_ADDR(AIU_DELTA_SIGMA6) -#define AIU_DELTA_SIGMA7 0x155c -#define P_AIU_DELTA_SIGMA7 CBUS_REG_ADDR(AIU_DELTA_SIGMA7) -#define AIU_DELTA_SIGMA_LCNTS 0x155d -#define P_AIU_DELTA_SIGMA_LCNTS \ - CBUS_REG_ADDR(AIU_DELTA_SIGMA_LCNTS) -#define AIU_DELTA_SIGMA_RCNTS 0x155e -#define P_AIU_DELTA_SIGMA_RCNTS \ - CBUS_REG_ADDR(AIU_DELTA_SIGMA_RCNTS) -#define AIU_MEM_I2S_START_PTR 0x1560 -#define P_AIU_MEM_I2S_START_PTR \ - CBUS_REG_ADDR(AIU_MEM_I2S_START_PTR) -#define AIU_MEM_I2S_RD_PTR 0x1561 -#define P_AIU_MEM_I2S_RD_PTR CBUS_REG_ADDR(AIU_MEM_I2S_RD_PTR) -#define AIU_MEM_I2S_END_PTR 0x1562 -#define P_AIU_MEM_I2S_END_PTR CBUS_REG_ADDR(AIU_MEM_I2S_END_PTR) -#define AIU_MEM_I2S_MASKS 0x1563 -#define P_AIU_MEM_I2S_MASKS CBUS_REG_ADDR(AIU_MEM_I2S_MASKS) -#define AIU_MEM_I2S_CONTROL 0x1564 -#define P_AIU_MEM_I2S_CONTROL CBUS_REG_ADDR(AIU_MEM_I2S_CONTROL) -#define AIU_MEM_IEC958_START_PTR 0x1565 -#define P_AIU_MEM_IEC958_START_PTR \ - CBUS_REG_ADDR(AIU_MEM_IEC958_START_PTR) -#define AIU_MEM_IEC958_RD_PTR 0x1566 -#define P_AIU_MEM_IEC958_RD_PTR \ - CBUS_REG_ADDR(AIU_MEM_IEC958_RD_PTR) -#define AIU_MEM_IEC958_END_PTR 0x1567 -#define AIU_MEM_AIFIFO2_START_PTR 0x156a -#define P_AIU_MEM_AIFIFO2_START_PTR \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO2_START_PTR) -#define AIU_MEM_AIFIFO2_CURR_PTR 0x156b -#define P_AIU_MEM_AIFIFO2_CURR_PTR \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CURR_PTR) -#define AIU_MEM_AIFIFO2_BYTES_AVAIL 0x156d -#define P_AIU_MEM_AIFIFO2_BYTES_AVAIL \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BYTES_AVAIL) -#define AIU_MEM_AIFIFO2_CONTROL 0x156e -#define P_AIU_MEM_AIFIFO2_CONTROL \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CONTROL) -#define AIU_MEM_AIFIFO2_LEVEL 0x1571 -#define P_AIU_MEM_AIFIFO2_LEVEL \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO2_LEVEL) -#define AIU_MEM_AIFIFO2_BUF_CNTL 0x1572 -#define P_AIU_MEM_AIFIFO2_BUF_CNTL \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_CNTL) -#define AIU_MEM_I2S_MAN_WP 0x1573 -#define P_AIU_MEM_I2S_MAN_WP CBUS_REG_ADDR(AIU_MEM_I2S_MAN_WP) -#define AIU_MEM_I2S_MAN_RP 0x1574 -#define P_AIU_MEM_I2S_MAN_RP CBUS_REG_ADDR(AIU_MEM_I2S_MAN_RP) -#define AIU_MEM_I2S_LEVEL 0x1575 -#define P_AIU_MEM_I2S_LEVEL CBUS_REG_ADDR(AIU_MEM_I2S_LEVEL) -#define AIU_MEM_I2S_BUF_CNTL 0x1576 -#define P_AIU_MEM_I2S_BUF_CNTL CBUS_REG_ADDR(AIU_MEM_I2S_BUF_CNTL) -#define AIU_MEM_I2S_BUF_WRAP_COUNT 0x1577 -#define P_AIU_MEM_I2S_BUF_WRAP_COUNT \ - CBUS_REG_ADDR(AIU_MEM_I2S_BUF_WRAP_COUNT) -#define AIU_MEM_I2S_MEM_CTL 0x1578 -#define P_AIU_MEM_I2S_MEM_CTL CBUS_REG_ADDR(AIU_MEM_I2S_MEM_CTL) -#define AIU_MEM_IEC958_WRAP_COUNT 0x157a -#define P_AIU_MEM_IEC958_WRAP_COUNT \ - CBUS_REG_ADDR(AIU_MEM_IEC958_WRAP_COUNT) -#define AIU_MEM_IEC958_IRQ_LEVEL 0x157b -#define P_AIU_MEM_IEC958_IRQ_LEVEL \ - CBUS_REG_ADDR(AIU_MEM_IEC958_IRQ_LEVEL) -#define AIU_MEM_IEC958_MAN_WP 0x157c -#define P_AIU_MEM_IEC958_MAN_WP \ - CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_WP) -#define AIU_MEM_IEC958_MAN_RP 0x157d -#define P_AIU_MEM_IEC958_MAN_RP \ - CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_RP) -#define AIU_MEM_IEC958_LEVEL 0x157e -#define P_AIU_MEM_IEC958_LEVEL \ - CBUS_REG_ADDR(AIU_MEM_IEC958_LEVEL) -#define AIU_AIFIFO_CTRL 0x1580 -#define P_AIU_AIFIFO_CTRL CBUS_REG_ADDR(AIU_AIFIFO_CTRL) -#define AIU_AIFIFO_STATUS 0x1581 -#define P_AIU_AIFIFO_STATUS CBUS_REG_ADDR(AIU_AIFIFO_STATUS) -#define AIU_AIFIFO_GBIT 0x1582 -#define P_AIU_AIFIFO_GBIT CBUS_REG_ADDR(AIU_AIFIFO_GBIT) -#define AIU_AIFIFO_CLB 0x1583 -#define P_AIU_AIFIFO_CLB CBUS_REG_ADDR(AIU_AIFIFO_CLB) -#define AIU_MEM_AIFIFO_START_PTR 0x1584 -#define P_AIU_MEM_AIFIFO_START_PTR \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO_START_PTR) -#define AIU_MEM_AIFIFO_BYTES_AVAIL 0x1587 -#define P_AIU_MEM_AIFIFO_BYTES_AVAIL \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO_BYTES_AVAIL) -#define AIU_MEM_AIFIFO_MAN_WP 0x1589 -#define P_AIU_MEM_AIFIFO_MAN_WP \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_WP) -#define AIU_MEM_AIFIFO_MAN_RP 0x158a -#define P_AIU_MEM_AIFIFO_MAN_RP \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_RP) -#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT 0x158d -#define P_AIU_MEM_AIFIFO_BUF_WRAP_COUNT \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO_BUF_WRAP_COUNT) -#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 0x158e -#define P_AIU_MEM_AIFIFO2_BUF_WRAP_COUNT \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_WRAP_COUNT) -#define AIFIFO_TIME_STAMP_SYNC_0 0x1591 -#define P_AIFIFO_TIME_STAMP_SYNC_0 \ - CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_0) -#define AIFIFO_TIME_STAMP_SYNC_1 0x1592 -#define P_AIFIFO_TIME_STAMP_SYNC_1 \ - CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_1) -#define AIFIFO_TIME_STAMP_0 0x1593 -#define P_AIFIFO_TIME_STAMP_0 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_0) -#define AIFIFO_TIME_STAMP_1 0x1594 -#define P_AIFIFO_TIME_STAMP_1 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_1) -#define AIFIFO_TIME_STAMP_2 0x1595 -#define P_AIFIFO_TIME_STAMP_2 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_2) -#define AIFIFO_TIME_STAMP_3 0x1596 -#define P_AIFIFO_TIME_STAMP_3 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_3) -#define AIFIFO_TIME_STAMP_LENGTH 0x1597 -#define P_AIFIFO_TIME_STAMP_LENGTH \ - CBUS_REG_ADDR(AIFIFO_TIME_STAMP_LENGTH) -#define AIFIFO2_TIME_STAMP_CNTL 0x1598 -#define P_AIFIFO2_TIME_STAMP_CNTL \ - CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_CNTL) -#define AIFIFO2_TIME_STAMP_SYNC_0 0x1599 -#define P_AIFIFO2_TIME_STAMP_SYNC_0 \ - CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_0) -#define AIFIFO2_TIME_STAMP_SYNC_1 0x159a -#define P_AIFIFO2_TIME_STAMP_SYNC_1 \ - CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_1) -#define AIFIFO2_TIME_STAMP_0 0x159b -#define P_AIFIFO2_TIME_STAMP_0 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_0) -#define AIFIFO2_TIME_STAMP_1 0x159c -#define P_AIFIFO2_TIME_STAMP_1 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_1) -#define AIFIFO2_TIME_STAMP_2 0x159d -#define P_AIFIFO2_TIME_STAMP_2 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_2) -#define AIFIFO2_TIME_STAMP_3 0x159e -#define P_AIFIFO2_TIME_STAMP_3 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_3) -#define AIFIFO2_TIME_STAMP_LENGTH 0x159f -#define P_AIFIFO2_TIME_STAMP_LENGTH \ - CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_LENGTH) -#define IEC958_TIME_STAMP_SYNC_0 0x15a1 -#define P_IEC958_TIME_STAMP_SYNC_0 \ - CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_0) -#define IEC958_TIME_STAMP_SYNC_1 0x15a2 -#define P_IEC958_TIME_STAMP_SYNC_1 \ - CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_1) -#define IEC958_TIME_STAMP_0 0x15a3 -#define P_IEC958_TIME_STAMP_0 CBUS_REG_ADDR(IEC958_TIME_STAMP_0) -#define IEC958_TIME_STAMP_1 0x15a4 -#define P_IEC958_TIME_STAMP_1 CBUS_REG_ADDR(IEC958_TIME_STAMP_1) -#define IEC958_TIME_STAMP_2 0x15a5 -#define P_IEC958_TIME_STAMP_2 CBUS_REG_ADDR(IEC958_TIME_STAMP_2) -#define IEC958_TIME_STAMP_3 0x15a6 -#define P_IEC958_TIME_STAMP_3 CBUS_REG_ADDR(IEC958_TIME_STAMP_3) -#define IEC958_TIME_STAMP_LENGTH 0x15a7 -#define P_IEC958_TIME_STAMP_LENGTH \ - CBUS_REG_ADDR(IEC958_TIME_STAMP_LENGTH) -#define AIU_MEM_AIFIFO2_MEM_CTL 0x15a8 -#define P_AIU_MEM_AIFIFO2_MEM_CTL \ - CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MEM_CTL) -#define AIU_I2S_CBUS_DDR_CNTL 0x15a9 -#define P_AIU_I2S_CBUS_DDR_CNTL \ - CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_CNTL) -#define AIU_I2S_CBUS_DDR_WDATA 0x15aa -#define P_AIU_I2S_CBUS_DDR_WDATA \ - CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_WDATA) -#define AIU_I2S_CBUS_DDR_ADDR 0x15ab -#define P_AIU_I2S_CBUS_DDR_ADDR \ - CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_ADDR) -#define GE2D_GEN_CTRL0 0x18a0 -#define P_GE2D_GEN_CTRL0 CBUS_REG_ADDR(GE2D_GEN_CTRL0) -#define GE2D_GEN_CTRL1 0x18a1 -#define P_GE2D_GEN_CTRL1 CBUS_REG_ADDR(GE2D_GEN_CTRL1) -#define GE2D_GEN_CTRL2 0x18a2 -#define P_GE2D_GEN_CTRL2 CBUS_REG_ADDR(GE2D_GEN_CTRL2) -#define GE2D_CMD_CTRL 0x18a3 -#define P_GE2D_CMD_CTRL CBUS_REG_ADDR(GE2D_CMD_CTRL) -#define GE2D_STATUS0 0x18a4 -#define P_GE2D_STATUS0 CBUS_REG_ADDR(GE2D_STATUS0) -#define GE2D_STATUS1 0x18a5 -#define P_GE2D_STATUS1 CBUS_REG_ADDR(GE2D_STATUS1) -#define GE2D_SRC1_DEF_COLOR 0x18a6 -#define P_GE2D_SRC1_DEF_COLOR CBUS_REG_ADDR(GE2D_SRC1_DEF_COLOR) -#define GE2D_SRC1_CLIPX_START_END 0x18a7 -#define P_GE2D_SRC1_CLIPX_START_END \ - CBUS_REG_ADDR(GE2D_SRC1_CLIPX_START_END) -#define GE2D_SRC1_CLIPY_START_END 0x18a8 -#define P_GE2D_SRC1_CLIPY_START_END \ - CBUS_REG_ADDR(GE2D_SRC1_CLIPY_START_END) -#define GE2D_SRC1_CANVAS 0x18a9 -#define P_GE2D_SRC1_CANVAS CBUS_REG_ADDR(GE2D_SRC1_CANVAS) -#define GE2D_SRC1_X_START_END 0x18aa -#define P_GE2D_SRC1_X_START_END \ - CBUS_REG_ADDR(GE2D_SRC1_X_START_END) -#define GE2D_SRC1_Y_START_END 0x18ab -#define P_GE2D_SRC1_Y_START_END \ - CBUS_REG_ADDR(GE2D_SRC1_Y_START_END) -#define GE2D_SRC1_LUT_ADDR 0x18ac -#define P_GE2D_SRC1_LUT_ADDR \ - CBUS_REG_ADDR(GE2D_SRC1_LUT_ADDR) -#define GE2D_SRC1_LUT_DAT 0x18ad -#define P_GE2D_SRC1_LUT_DAT \ - CBUS_REG_ADDR(GE2D_SRC1_LUT_DAT) -#define GE2D_SRC1_FMT_CTRL 0x18ae -#define P_GE2D_SRC1_FMT_CTRL \ - CBUS_REG_ADDR(GE2D_SRC1_FMT_CTRL) -#define GE2D_SRC2_DEF_COLOR 0x18af -#define P_GE2D_SRC2_DEF_COLOR CBUS_REG_ADDR(GE2D_SRC2_DEF_COLOR) -#define GE2D_SRC2_CLIPX_START_END 0x18b0 -#define P_GE2D_SRC2_CLIPX_START_END \ - CBUS_REG_ADDR(GE2D_SRC2_CLIPX_START_END) -#define GE2D_SRC2_CLIPY_START_END 0x18b1 -#define P_GE2D_SRC2_CLIPY_START_END \ - CBUS_REG_ADDR(GE2D_SRC2_CLIPY_START_END) -#define GE2D_SRC2_X_START_END 0x18b2 -#define P_GE2D_SRC2_X_START_END \ - CBUS_REG_ADDR(GE2D_SRC2_X_START_END) -#define GE2D_SRC2_Y_START_END 0x18b3 -#define P_GE2D_SRC2_Y_START_END \ - CBUS_REG_ADDR(GE2D_SRC2_Y_START_END) -#define GE2D_DST_CLIPX_START_END 0x18b4 -#define P_GE2D_DST_CLIPX_START_END \ - CBUS_REG_ADDR(GE2D_DST_CLIPX_START_END) -#define GE2D_DST_CLIPY_START_END 0x18b5 -#define P_GE2D_DST_CLIPY_START_END \ - CBUS_REG_ADDR(GE2D_DST_CLIPY_START_END) -#define GE2D_DST_X_START_END 0x18b6 -#define P_GE2D_DST_X_START_END CBUS_REG_ADDR(GE2D_DST_X_START_END) -#define GE2D_DST_Y_START_END 0x18b7 -#define P_GE2D_DST_Y_START_END CBUS_REG_ADDR(GE2D_DST_Y_START_END) -#define GE2D_SRC2_DST_CANVAS 0x18b8 -#define P_GE2D_SRC2_DST_CANVAS CBUS_REG_ADDR(GE2D_SRC2_DST_CANVAS) -#define GE2D_VSC_PHASE_SLOPE 0x18ba -#define P_GE2D_VSC_PHASE_SLOPE CBUS_REG_ADDR(GE2D_VSC_PHASE_SLOPE) -#define GE2D_VSC_INI_CTRL 0x18bb -#define P_GE2D_VSC_INI_CTRL CBUS_REG_ADDR(GE2D_VSC_INI_CTRL) -#define GE2D_HSC_PHASE_SLOPE 0x18bd -#define P_GE2D_HSC_PHASE_SLOPE CBUS_REG_ADDR(GE2D_HSC_PHASE_SLOPE) -#define GE2D_HSC_INI_CTRL 0x18be -#define P_GE2D_HSC_INI_CTRL CBUS_REG_ADDR(GE2D_HSC_INI_CTRL) -#define GE2D_HSC_ADV_CTRL 0x18bf -#define P_GE2D_HSC_ADV_CTRL CBUS_REG_ADDR(GE2D_HSC_ADV_CTRL) -#define GE2D_SC_MISC_CTRL 0x18c0 -#define P_GE2D_SC_MISC_CTRL CBUS_REG_ADDR(GE2D_SC_MISC_CTRL) -#define GE2D_VSC_NRND_POINT 0x18c1 -#define P_GE2D_VSC_NRND_POINT CBUS_REG_ADDR(GE2D_VSC_NRND_POINT) -#define GE2D_VSC_NRND_PHASE 0x18c2 -#define P_GE2D_VSC_NRND_PHASE CBUS_REG_ADDR(GE2D_VSC_NRND_PHASE) -#define GE2D_HSC_NRND_POINT 0x18c3 -#define P_GE2D_HSC_NRND_POINT CBUS_REG_ADDR(GE2D_HSC_NRND_POINT) -#define GE2D_HSC_NRND_PHASE 0x18c4 -#define P_GE2D_HSC_NRND_PHASE CBUS_REG_ADDR(GE2D_HSC_NRND_PHASE) -#define GE2D_MATRIX_COEF00_01 0x18c6 -#define P_GE2D_MATRIX_COEF00_01 \ - CBUS_REG_ADDR(GE2D_MATRIX_COEF00_01) -#define GE2D_MATRIX_COEF02_10 0x18c7 -#define P_GE2D_MATRIX_COEF02_10 \ - CBUS_REG_ADDR(GE2D_MATRIX_COEF02_10) -#define GE2D_MATRIX_COEF11_12 0x18c8 -#define P_GE2D_MATRIX_COEF11_12 \ - CBUS_REG_ADDR(GE2D_MATRIX_COEF11_12) -#define GE2D_MATRIX_COEF20_21 0x18c9 -#define P_GE2D_MATRIX_COEF20_21 \ - CBUS_REG_ADDR(GE2D_MATRIX_COEF20_21) -#define GE2D_MATRIX_COEF22_CTRL 0x18ca -#define P_GE2D_MATRIX_COEF22_CTRL \ - CBUS_REG_ADDR(GE2D_MATRIX_COEF22_CTRL) -#define GE2D_MATRIX_OFFSET 0x18cb -#define P_GE2D_MATRIX_OFFSET CBUS_REG_ADDR(GE2D_MATRIX_OFFSET) -#define GE2D_ALU_OP_CTRL 0x18cc -#define P_GE2D_ALU_OP_CTRL CBUS_REG_ADDR(GE2D_ALU_OP_CTRL) -#define GE2D_ALU_CONST_COLOR 0x18cd -#define P_GE2D_ALU_CONST_COLOR CBUS_REG_ADDR(GE2D_ALU_CONST_COLOR) -#define GE2D_SRC1_KEY 0x18ce -#define P_GE2D_SRC1_KEY CBUS_REG_ADDR(GE2D_SRC1_KEY) -#define GE2D_SRC1_KEY_MASK 0x18cf -#define P_GE2D_SRC1_KEY_MASK CBUS_REG_ADDR(GE2D_SRC1_KEY_MASK) -#define GE2D_SRC2_KEY 0x18d0 -#define P_GE2D_SRC2_KEY CBUS_REG_ADDR(GE2D_SRC2_KEY) -#define GE2D_SRC2_KEY_MASK 0x18d1 -#define P_GE2D_SRC2_KEY_MASK CBUS_REG_ADDR(GE2D_SRC2_KEY_MASK) -#define GE2D_DST_BITMASK 0x18d2 -#define P_GE2D_DST_BITMASK CBUS_REG_ADDR(GE2D_DST_BITMASK) -#define GE2D_DP_ONOFF_CTRL 0x18d3 -#define P_GE2D_DP_ONOFF_CTRL CBUS_REG_ADDR(GE2D_DP_ONOFF_CTRL) -#define GE2D_SCALE_COEF_IDX 0x18d4 -#define P_GE2D_SCALE_COEF_IDX CBUS_REG_ADDR(GE2D_SCALE_COEF_IDX) -#define GE2D_SCALE_COEF 0x18d5 -#define P_GE2D_SCALE_COEF CBUS_REG_ADDR(GE2D_SCALE_COEF) -#define GE2D_ANTIFLICK_CTRL0 0x18d8 -#define P_GE2D_ANTIFLICK_CTRL0 CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL0) -#define GE2D_ANTIFLICK_CTRL1 0x18d9 -#define P_GE2D_ANTIFLICK_CTRL1 CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL1) -#define GE2D_ANTIFLICK_COLOR_FILT0 0x18da -#define P_GE2D_ANTIFLICK_COLOR_FILT0 \ - CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT0) -#define GE2D_ANTIFLICK_COLOR_FILT1 0x18db -#define P_GE2D_ANTIFLICK_COLOR_FILT1 \ - CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT1) -#define GE2D_ANTIFLICK_COLOR_FILT2 0x18dc -#define P_GE2D_ANTIFLICK_COLOR_FILT2 \ - CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT2) -#define GE2D_ANTIFLICK_COLOR_FILT3 0x18dd -#define P_GE2D_ANTIFLICK_COLOR_FILT3 \ - CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT3) -#define GE2D_ANTIFLICK_ALPHA_FILT0 0x18de -#define P_GE2D_ANTIFLICK_ALPHA_FILT0 \ - CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT0) -#define GE2D_ANTIFLICK_ALPHA_FILT1 0x18df -#define P_GE2D_ANTIFLICK_ALPHA_FILT1 \ - CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT1) -#define GE2D_ANTIFLICK_ALPHA_FILT2 0x18e0 -#define P_GE2D_ANTIFLICK_ALPHA_FILT2 \ - CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT2) -#define GE2D_ANTIFLICK_ALPHA_FILT3 0x18e1 -#define P_GE2D_ANTIFLICK_ALPHA_FILT3 \ - CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT3) -#define GE2D_SRC1_RANGE_MAP_Y_CTRL 0x18e3 -#define P_GE2D_SRC1_RANGE_MAP_Y_CTRL \ - CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_Y_CTRL) -#define GE2D_SRC1_RANGE_MAP_CB_CTRL 0x18e4 -#define P_GE2D_SRC1_RANGE_MAP_CB_CTRL \ - CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CB_CTRL) -#define GE2D_SRC1_RANGE_MAP_CR_CTRL 0x18e5 -#define P_GE2D_SRC1_RANGE_MAP_CR_CTRL \ - CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CR_CTRL) -#define GE2D_ARB_BURST_NUM 0x18e6 -#define P_GE2D_ARB_BURST_NUM CBUS_REG_ADDR(GE2D_ARB_BURST_NUM) -#define GE2D_TID_TOKEN 0x18e7 -#define P_GE2D_TID_TOKEN CBUS_REG_ADDR(GE2D_TID_TOKEN) -#define GE2D_GEN_CTRL3 0x18e8 -#define P_GE2D_GEN_CTRL3 CBUS_REG_ADDR(GE2D_GEN_CTRL3) -#define GE2D_STATUS2 0x18e9 -#define P_GE2D_STATUS2 CBUS_REG_ADDR(GE2D_STATUS2) -#define GE2D_GEN_CTRL4 0x18ea -#define P_GE2D_GEN_CTRL4 CBUS_REG_ADDR(GE2D_GEN_CTRL4) -#define AUDIO_COP_CTL2 0x1f01 -#define P_AUDIO_COP_CTL2 CBUS_REG_ADDR(AUDIO_COP_CTL2) -#define OPERAND_M_CTL 0x1f02 -#define P_OPERAND_M_CTL CBUS_REG_ADDR(OPERAND_M_CTL) -#define OPERAND1_ADDR 0x1f03 -#define P_OPERAND1_ADDR CBUS_REG_ADDR(OPERAND1_ADDR) -#define OPERAND2_ADDR 0x1f04 -#define P_OPERAND2_ADDR CBUS_REG_ADDR(OPERAND2_ADDR) -#define RESULT_M_CTL 0x1f05 -#define P_RESULT_M_CTL CBUS_REG_ADDR(RESULT_M_CTL) -#define RESULT1_ADDR 0x1f06 -#define P_RESULT1_ADDR CBUS_REG_ADDR(RESULT1_ADDR) -#define RESULT2_ADDR 0x1f07 -#define P_RESULT2_ADDR CBUS_REG_ADDR(RESULT2_ADDR) -#define ADD_SHFT_CTL 0x1f08 -#define P_ADD_SHFT_CTL CBUS_REG_ADDR(ADD_SHFT_CTL) -#define OPERAND_ONE_H 0x1f09 -#define P_OPERAND_ONE_H CBUS_REG_ADDR(OPERAND_ONE_H) -#define OPERAND_ONE_L 0x1f0a -#define P_OPERAND_ONE_L CBUS_REG_ADDR(OPERAND_ONE_L) -#define OPERAND_TWO_H 0x1f0b -#define P_OPERAND_TWO_H CBUS_REG_ADDR(OPERAND_TWO_H) -#define OPERAND_TWO_L 0x1f0c -#define P_OPERAND_TWO_L CBUS_REG_ADDR(OPERAND_TWO_L) -#define RESULT_H 0x1f0d -#define P_RESULT_H CBUS_REG_ADDR(RESULT_H) -#define RESULT_M 0x1f0e -#define P_RESULT_M CBUS_REG_ADDR(RESULT_M) -#define RESULT_L 0x1f0f -#define P_RESULT_L CBUS_REG_ADDR(RESULT_L) -#define WMEM_R_PTR 0x1f10 -#define P_WMEM_R_PTR CBUS_REG_ADDR(WMEM_R_PTR) -#define WMEM_W_PTR 0x1f11 -#define P_WMEM_W_PTR CBUS_REG_ADDR(WMEM_W_PTR) -#define AUDIO_LAYER 0x1f20 -#define P_AUDIO_LAYER CBUS_REG_ADDR(AUDIO_LAYER) -#define AC3_DECODING 0x1f21 -#define P_AC3_DECODING CBUS_REG_ADDR(AC3_DECODING) -#define AC3_DYNAMIC 0x1f22 -#define P_AC3_DYNAMIC CBUS_REG_ADDR(AC3_DYNAMIC) -#define AC3_MELODY 0x1f23 -#define P_AC3_MELODY CBUS_REG_ADDR(AC3_MELODY) -#define AC3_VOCAL 0x1f24 -#define P_AC3_VOCAL CBUS_REG_ADDR(AC3_VOCAL) -#define ASSIST_AMR_SCRATCH0 0x1f4f -#define P_ASSIST_AMR_SCRATCH0 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH0) -#define ASSIST_AMR_SCRATCH1 0x1f50 -#define P_ASSIST_AMR_SCRATCH1 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH1) -#define ASSIST_AMR_SCRATCH2 0x1f51 -#define P_ASSIST_AMR_SCRATCH2 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH2) -#define ASSIST_AMR_SCRATCH3 0x1f52 -#define P_ASSIST_AMR_SCRATCH3 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH3) -#define ASSIST_HW_REV 0x1f53 -#define P_ASSIST_HW_REV CBUS_REG_ADDR(ASSIST_HW_REV) -#define ASSIST_POR_CONFIG 0x1f55 -#define P_ASSIST_POR_CONFIG CBUS_REG_ADDR(ASSIST_POR_CONFIG) -#define ASSIST_SPARE16_REG1 0x1f56 -#define P_ASSIST_SPARE16_REG1 CBUS_REG_ADDR(ASSIST_SPARE16_REG1) -#define ASSIST_SPARE16_REG2 0x1f57 -#define P_ASSIST_SPARE16_REG2 CBUS_REG_ADDR(ASSIST_SPARE16_REG2) -#define ASSIST_SPARE8_REG1 0x1f58 -#define P_ASSIST_SPARE8_REG1 CBUS_REG_ADDR(ASSIST_SPARE8_REG1) -#define ASSIST_SPARE8_REG2 0x1f59 -#define P_ASSIST_SPARE8_REG2 CBUS_REG_ADDR(ASSIST_SPARE8_REG2) -#define ASSIST_SPARE8_REG3 0x1f5a -#define P_ASSIST_SPARE8_REG3 CBUS_REG_ADDR(ASSIST_SPARE8_REG3) -#define AC3_CTRL_REG1 0x1f5b -#define P_AC3_CTRL_REG1 CBUS_REG_ADDR(AC3_CTRL_REG1) -#define AC3_CTRL_REG2 0x1f5c -#define P_AC3_CTRL_REG2 CBUS_REG_ADDR(AC3_CTRL_REG2) -#define AC3_CTRL_REG3 0x1f5d -#define P_AC3_CTRL_REG3 CBUS_REG_ADDR(AC3_CTRL_REG3) -#define AC3_CTRL_REG4 0x1f5e -#define P_AC3_CTRL_REG4 CBUS_REG_ADDR(AC3_CTRL_REG4) -#define ASSIST_GEN_CNTL 0x1f68 -#define P_ASSIST_GEN_CNTL CBUS_REG_ADDR(ASSIST_GEN_CNTL) -#define EE_ASSIST_MBOX0_IRQ_REG 0x1f70 +#define PARSER_SUB_HOLE (PARSER_SUB_START_PTR_BASE + 0x8e) +#define P_PARSER_SUB_HOLE CBUS_REG_ADDR(PARSER_SUB_HOLE) -#define EE_ASSIST_MBOX3_MASK 0x1f7e -#define P_EE_ASSIST_MBOX3_MASK CBUS_REG_ADDR(EE_ASSIST_MBOX3_MASK) -#define AUDIN_SPDIF_MODE 0x2800 -#define P_AUDIN_SPDIF_MODE CBUS_REG_ADDR(AUDIN_SPDIF_MODE) -#define AUDIN_SPDIF_MISC 0x2804 -#define P_AUDIN_SPDIF_MISC CBUS_REG_ADDR(AUDIN_SPDIF_MISC) -#define AUDIN_SPDIF_END 0x280f -#define P_AUDIN_SPDIF_END CBUS_REG_ADDR(AUDIN_SPDIF_END) -#define AUDIN_I2SIN_CTRL 0x2810 -#define P_AUDIN_I2SIN_CTRL CBUS_REG_ADDR(AUDIN_I2SIN_CTRL) -#define AUDIN_SOURCE_SEL 0x2811 -#define P_AUDIN_SOURCE_SEL CBUS_REG_ADDR(AUDIN_SOURCE_SEL) -#define AUDIN_DECODE_FORMAT 0x2812 -#define P_AUDIN_DECODE_FORMAT CBUS_REG_ADDR(AUDIN_DECODE_FORMAT) -#define AUDIN_DECODE_CONTROL_STATUS 0x2813 -#define P_AUDIN_DECODE_CONTROL_STATUS \ - CBUS_REG_ADDR(AUDIN_DECODE_CONTROL_STATUS) -#define AUDIN_DECODE_CHANNEL_STATUS_A_0 0x2814 -#define P_AUDIN_DECODE_CHANNEL_STATUS_A_0 \ - CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_0) -#define AUDIN_DECODE_CHANNEL_STATUS_A_1 0x2815 -#define P_AUDIN_DECODE_CHANNEL_STATUS_A_1 \ - CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_1) -#define AUDIN_DECODE_CHANNEL_STATUS_A_2 0x2816 -#define P_AUDIN_DECODE_CHANNEL_STATUS_A_2 \ - CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_2) -#define AUDIN_DECODE_CHANNEL_STATUS_A_3 0x2817 -#define P_AUDIN_DECODE_CHANNEL_STATUS_A_3 \ - CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_3) -#define AUDIN_DECODE_CHANNEL_STATUS_A_4 0x2818 -#define P_AUDIN_DECODE_CHANNEL_STATUS_A_4 \ - CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_4) -#define AUDIN_DECODE_CHANNEL_STATUS_A_5 0x2819 -#define P_AUDIN_DECODE_CHANNEL_STATUS_A_5 \ - CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_5) -#define AUDIN_FIFO0_START 0x2820 -#define P_AUDIN_FIFO0_START CBUS_REG_ADDR(AUDIN_FIFO0_START) -#define AUDIN_FIFO0_END 0x2821 -#define P_AUDIN_FIFO0_END CBUS_REG_ADDR(AUDIN_FIFO0_END) -#define AUDIN_FIFO0_PTR 0x2822 -#define P_AUDIN_FIFO0_PTR CBUS_REG_ADDR(AUDIN_FIFO0_PTR) -#define AUDIN_FIFO0_INTR 0x2823 -#define P_AUDIN_FIFO0_INTR CBUS_REG_ADDR(AUDIN_FIFO0_INTR) -#define AUDIN_FIFO0_RDPTR 0x2824 -#define P_AUDIN_FIFO0_RDPTR CBUS_REG_ADDR(AUDIN_FIFO0_RDPTR) -#define AUDIN_FIFO0_CTRL 0x2825 -#define P_AUDIN_FIFO0_CTRL CBUS_REG_ADDR(AUDIN_FIFO0_CTRL) -#define AUDIN_FIFO0_CTRL1 0x2826 -#define P_AUDIN_FIFO0_CTRL1 CBUS_REG_ADDR(AUDIN_FIFO0_CTRL1) -#define AUDIN_FIFO0_LVL0 0x2827 -#define P_AUDIN_FIFO0_LVL0 CBUS_REG_ADDR(AUDIN_FIFO0_LVL0) -#define AUDIN_FIFO0_LVL1 0x2828 -#define P_AUDIN_FIFO0_LVL1 CBUS_REG_ADDR(AUDIN_FIFO0_LVL1) -#define AUDIN_FIFO0_LVL2 0x2829 -#define P_AUDIN_FIFO0_LVL2 CBUS_REG_ADDR(AUDIN_FIFO0_LVL2) -#define AUDIN_FIFO0_REQID 0x2830 -#define P_AUDIN_FIFO0_REQID CBUS_REG_ADDR(AUDIN_FIFO0_REQID) -#define AUDIN_FIFO0_WRAP 0x2831 -#define P_AUDIN_FIFO0_WRAP CBUS_REG_ADDR(AUDIN_FIFO0_WRAP) -#define AUDIN_FIFO1_START 0x2833 -#define P_AUDIN_FIFO1_START CBUS_REG_ADDR(AUDIN_FIFO1_START) -#define AUDIN_FIFO1_END 0x2834 -#define P_AUDIN_FIFO1_END CBUS_REG_ADDR(AUDIN_FIFO1_END) -#define AUDIN_FIFO1_PTR 0x2835 -#define P_AUDIN_FIFO1_PTR CBUS_REG_ADDR(AUDIN_FIFO1_PTR) -#define AUDIN_FIFO1_INTR 0x2836 -#define P_AUDIN_FIFO1_INTR CBUS_REG_ADDR(AUDIN_FIFO1_INTR) -#define AUDIN_FIFO1_RDPTR 0x2837 -#define P_AUDIN_FIFO1_RDPTR CBUS_REG_ADDR(AUDIN_FIFO1_RDPTR) -#define AUDIN_FIFO1_CTRL 0x2838 -#define P_AUDIN_FIFO1_CTRL CBUS_REG_ADDR(AUDIN_FIFO1_CTRL) -#define AUDIN_FIFO1_CTRL1 0x2839 -#define P_AUDIN_FIFO1_CTRL1 CBUS_REG_ADDR(AUDIN_FIFO1_CTRL1) -#define AUDIN_FIFO1_LVL0 0x2840 -#define P_AUDIN_FIFO1_LVL0 CBUS_REG_ADDR(AUDIN_FIFO1_LVL0) -#define AUDIN_FIFO1_LVL1 0x2841 -#define P_AUDIN_FIFO1_LVL1 CBUS_REG_ADDR(AUDIN_FIFO1_LVL1) -#define AUDIN_FIFO1_LVL2 0x2842 -#define P_AUDIN_FIFO1_LVL2 CBUS_REG_ADDR(AUDIN_FIFO1_LVL2) -#define AUDIN_FIFO1_REQID 0x2843 -#define P_AUDIN_FIFO1_REQID CBUS_REG_ADDR(AUDIN_FIFO1_REQID) -#define AUDIN_FIFO1_WRAP 0x2844 -#define P_AUDIN_FIFO1_WRAP CBUS_REG_ADDR(AUDIN_FIFO1_WRAP) -#define AUDIN_FIFO2_START 0x2845 -#define P_AUDIN_FIFO2_START CBUS_REG_ADDR(AUDIN_FIFO2_START) -#define AUDIN_FIFO2_END 0x2846 -#define P_AUDIN_FIFO2_END CBUS_REG_ADDR(AUDIN_FIFO2_END) -#define AUDIN_FIFO2_PTR 0x2847 -#define P_AUDIN_FIFO2_PTR CBUS_REG_ADDR(AUDIN_FIFO2_PTR) -#define AUDIN_FIFO2_INTR 0x2848 -#define P_AUDIN_FIFO2_INTR CBUS_REG_ADDR(AUDIN_FIFO2_INTR) -#define AUDIN_FIFO2_RDPTR 0x2849 -#define P_AUDIN_FIFO2_RDPTR CBUS_REG_ADDR(AUDIN_FIFO2_RDPTR) -#define AUDIN_FIFO2_CTRL 0x284a -#define P_AUDIN_FIFO2_CTRL CBUS_REG_ADDR(AUDIN_FIFO2_CTRL) -#define AUDIN_FIFO2_CTRL1 0x284b -#define P_AUDIN_FIFO2_CTRL1 CBUS_REG_ADDR(AUDIN_FIFO2_CTRL1) -#define AUDIN_FIFO2_LVL0 0x284c -#define P_AUDIN_FIFO2_LVL0 CBUS_REG_ADDR(AUDIN_FIFO2_LVL0) -#define AUDIN_FIFO2_LVL1 0x284d -#define P_AUDIN_FIFO2_LVL1 CBUS_REG_ADDR(AUDIN_FIFO2_LVL1) -#define AUDIN_FIFO2_LVL2 0x284e -#define P_AUDIN_FIFO2_LVL2 CBUS_REG_ADDR(AUDIN_FIFO2_LVL2) -#define AUDIN_FIFO2_REQID 0x284f -#define P_AUDIN_FIFO2_REQID CBUS_REG_ADDR(AUDIN_FIFO2_REQID) -#define AUDIN_FIFO2_WRAP 0x2850 -#define P_AUDIN_FIFO2_WRAP CBUS_REG_ADDR(AUDIN_FIFO2_WRAP) -#define AUDIN_INT_CTRL 0x2851 -#define P_AUDIN_INT_CTRL CBUS_REG_ADDR(AUDIN_INT_CTRL) -#define AUDIN_FIFO_INT 0x2852 -#define P_AUDIN_FIFO_INT CBUS_REG_ADDR(AUDIN_FIFO_INT) -#define PCMIN_CTRL0 0x2860 -#define P_PCMIN_CTRL0 CBUS_REG_ADDR(PCMIN_CTRL0) -#define PCMIN_CTRL1 0x2861 -#define P_PCMIN_CTRL1 CBUS_REG_ADDR(PCMIN_CTRL1) -#define PCMIN1_CTRL0 0x2862 -#define P_PCMIN1_CTRL0 CBUS_REG_ADDR(PCMIN1_CTRL0) -#define PCMIN1_CTRL1 0x2863 -#define P_PCMIN1_CTRL1 CBUS_REG_ADDR(PCMIN1_CTRL1) -#define PCMOUT_CTRL0 0x2870 -#define P_PCMOUT_CTRL0 CBUS_REG_ADDR(PCMOUT_CTRL0) -#define PCMOUT_CTRL1 0x2871 -#define P_PCMOUT_CTRL1 CBUS_REG_ADDR(PCMOUT_CTRL1) -#define PCMOUT_CTRL2 0x2872 -#define P_PCMOUT_CTRL2 CBUS_REG_ADDR(PCMOUT_CTRL2) -#define PCMOUT_CTRL3 0x2873 -#define P_PCMOUT_CTRL3 CBUS_REG_ADDR(PCMOUT_CTRL3) -#define PCMOUT1_CTRL0 0x2874 -#define P_PCMOUT1_CTRL0 CBUS_REG_ADDR(PCMOUT1_CTRL0) -#define PCMOUT1_CTRL1 0x2875 -#define P_PCMOUT1_CTRL1 CBUS_REG_ADDR(PCMOUT1_CTRL1) -#define PCMOUT1_CTRL2 0x2876 -#define P_PCMOUT1_CTRL2 CBUS_REG_ADDR(PCMOUT1_CTRL2) -#define PCMOUT1_CTRL3 0x2877 -#define P_PCMOUT1_CTRL3 CBUS_REG_ADDR(PCMOUT1_CTRL3) -#define AUDOUT_CTRL 0x2880 -#define P_AUDOUT_CTRL CBUS_REG_ADDR(AUDOUT_CTRL) -#define AUDOUT_CTRL1 0x2881 -#define P_AUDOUT_CTRL1 CBUS_REG_ADDR(AUDOUT_CTRL1) -#define AUDOUT_BUF0_STA 0x2882 -#define P_AUDOUT_BUF0_STA CBUS_REG_ADDR(AUDOUT_BUF0_STA) -#define AUDOUT_BUF0_EDA 0x2883 -#define P_AUDOUT_BUF0_EDA CBUS_REG_ADDR(AUDOUT_BUF0_EDA) -#define AUDOUT_BUF0_WPTR 0x2884 -#define P_AUDOUT_BUF0_WPTR CBUS_REG_ADDR(AUDOUT_BUF0_WPTR) -#define AUDOUT_BUF1_STA 0x2885 -#define P_AUDOUT_BUF1_STA CBUS_REG_ADDR(AUDOUT_BUF1_STA) -#define AUDOUT_BUF1_EDA 0x2886 -#define P_AUDOUT_BUF1_EDA CBUS_REG_ADDR(AUDOUT_BUF1_EDA) -#define AUDOUT_BUF1_WPTR 0x2887 -#define P_AUDOUT_BUF1_WPTR CBUS_REG_ADDR(AUDOUT_BUF1_WPTR) -#define AUDOUT_FIFO_RPTR 0x2888 -#define P_AUDOUT_FIFO_RPTR CBUS_REG_ADDR(AUDOUT_FIFO_RPTR) -#define AUDOUT_INTR_PTR 0x2889 -#define P_AUDOUT_INTR_PTR CBUS_REG_ADDR(AUDOUT_INTR_PTR) -#define AUDOUT_FIFO_STS 0x288a -#define P_AUDOUT_FIFO_STS CBUS_REG_ADDR(AUDOUT_FIFO_STS) -#define AUDOUT1_CTRL 0x2890 -#define P_AUDOUT1_CTRL CBUS_REG_ADDR(AUDOUT1_CTRL) -#define AUDOUT1_CTRL1 0x2891 -#define P_AUDOUT1_CTRL1 CBUS_REG_ADDR(AUDOUT1_CTRL1) -#define AUDOUT1_BUF0_STA 0x2892 -#define P_AUDOUT1_BUF0_STA CBUS_REG_ADDR(AUDOUT1_BUF0_STA) -#define AUDOUT1_BUF0_EDA 0x2893 -#define P_AUDOUT1_BUF0_EDA CBUS_REG_ADDR(AUDOUT1_BUF0_EDA) -#define AUDOUT1_BUF0_WPTR 0x2894 -#define P_AUDOUT1_BUF0_WPTR CBUS_REG_ADDR(AUDOUT1_BUF0_WPTR) -#define AUDOUT1_BUF1_STA 0x2895 -#define P_AUDOUT1_BUF1_STA CBUS_REG_ADDR(AUDOUT1_BUF1_STA) -#define AUDOUT1_BUF1_EDA 0x2896 -#define P_AUDOUT1_BUF1_EDA CBUS_REG_ADDR(AUDOUT1_BUF1_EDA) -#define AUDOUT1_BUF1_WPTR 0x2897 -#define P_AUDOUT1_BUF1_WPTR CBUS_REG_ADDR(AUDOUT1_BUF1_WPTR) -#define AUDOUT1_FIFO_RPTR 0x2898 -#define P_AUDOUT1_FIFO_RPTR CBUS_REG_ADDR(AUDOUT1_FIFO_RPTR) -#define AUDOUT1_INTR_PTR 0x2899 -#define P_AUDOUT1_INTR_PTR CBUS_REG_ADDR(AUDOUT1_INTR_PTR) -#define AUDOUT1_FIFO_STS 0x289a -#define P_AUDOUT1_FIFO_STS CBUS_REG_ADDR(AUDOUT1_FIFO_STS) -#define AUDIN_HDMI_MEAS_CTRL 0x28a0 -#define P_AUDIN_HDMI_MEAS_CTRL CBUS_REG_ADDR(AUDIN_HDMI_MEAS_CTRL) -#define AUDIN_HDMI_MEAS_CYCLES_M1 0x28a1 -#define AUDIN_FIFO0_PIO_STS 0x28b0 -#define P_AUDIN_FIFO0_PIO_STS CBUS_REG_ADDR(AUDIN_FIFO0_PIO_STS) -#define AUDIN_FIFO0_PIO_RDL 0x28b1 -#define P_AUDIN_FIFO0_PIO_RDL CBUS_REG_ADDR(AUDIN_FIFO0_PIO_RDL) -#define AUDIN_FIFO0_PIO_RDH 0x28b2 -#define P_AUDIN_FIFO0_PIO_RDH CBUS_REG_ADDR(AUDIN_FIFO0_PIO_RDH) -#define AUDIN_FIFO1_PIO_STS 0x28b3 -#define P_AUDIN_FIFO1_PIO_STS CBUS_REG_ADDR(AUDIN_FIFO1_PIO_STS) -#define AUDIN_FIFO1_PIO_RDL 0x28b4 -#define P_AUDIN_FIFO1_PIO_RDL CBUS_REG_ADDR(AUDIN_FIFO1_PIO_RDL) -#define AUDIN_FIFO1_PIO_RDH 0x28b5 -#define P_AUDIN_FIFO1_PIO_RDH CBUS_REG_ADDR(AUDIN_FIFO1_PIO_RDH) -#define AUDIN_FIFO2_PIO_STS 0x28b6 -#define P_AUDIN_FIFO2_PIO_STS CBUS_REG_ADDR(AUDIN_FIFO2_PIO_STS) -#define AUDIN_FIFO2_PIO_RDL 0x28b7 -#define P_AUDIN_FIFO2_PIO_RDL CBUS_REG_ADDR(AUDIN_FIFO2_PIO_RDL) -#define AUDIN_FIFO2_PIO_RDH 0x28b8 -#define P_AUDIN_FIFO2_PIO_RDH CBUS_REG_ADDR(AUDIN_FIFO2_PIO_RDH) -#define AUDOUT_FIFO_PIO_STS 0x28b9 -#define P_AUDOUT_FIFO_PIO_STS CBUS_REG_ADDR(AUDOUT_FIFO_PIO_STS) -#define AUDOUT_FIFO_PIO_WRL 0x28ba -#define P_AUDOUT_FIFO_PIO_WRL CBUS_REG_ADDR(AUDOUT_FIFO_PIO_WRL) -#define AUDOUT_FIFO_PIO_WRH 0x28bb -#define P_AUDOUT_FIFO_PIO_WRH CBUS_REG_ADDR(AUDOUT_FIFO_PIO_WRH) -#define AUDOUT1_FIFO_PIO_STS 0x28bc -#define P_AUDOUT1_FIFO_PIO_STS CBUS_REG_ADDR(AUDOUT1_FIFO_PIO_STS) -#define AUDOUT1_FIFO_PIO_WRL 0x28bd -#define P_AUDOUT1_FIFO_PIO_WRL CBUS_REG_ADDR(AUDOUT1_FIFO_PIO_WRL) -#define AUDOUT1_FIFO_PIO_WRH 0x28be -#define P_AUDOUT1_FIFO_PIO_WRH CBUS_REG_ADDR(AUDOUT1_FIFO_PIO_WRH) -#define AUDIN_ADDR_END 0x28bf -#define P_AUDIN_ADDR_END CBUS_REG_ADDR(AUDIN_ADDR_END) -#define VDIN_SCALE_COEF_IDX 0x1200 -#define P_VDIN_SCALE_COEF_IDX VCBUS_REG_ADDR(VDIN_SCALE_COEF_IDX) -#define VDIN_SCALE_COEF 0x1201 -#define P_VDIN_SCALE_COEF VCBUS_REG_ADDR(VDIN_SCALE_COEF) -#define VDIN_COM_CTRL0 0x1202 -#define P_VDIN_COM_CTRL0 VCBUS_REG_ADDR(VDIN_COM_CTRL0) -#define VDIN_ACTIVE_MAX_PIX_CNT_STATUS 0x1203 -#define VDIN_LCNT_STATUS 0x1204 -#define P_VDIN_LCNT_STATUS VCBUS_REG_ADDR(VDIN_LCNT_STATUS) -#define VDIN_COM_STATUS0 0x1205 -#define P_VDIN_COM_STATUS0 VCBUS_REG_ADDR(VDIN_COM_STATUS0) -#define VDIN_COM_STATUS1 0x1206 -#define P_VDIN_COM_STATUS1 VCBUS_REG_ADDR(VDIN_COM_STATUS1) -#define VDIN_LCNT_SHADOW_STATUS 0x1207 -#define VDIN_ASFIFO_CTRL0 0x1208 -#define P_VDIN_ASFIFO_CTRL0 VCBUS_REG_ADDR(VDIN_ASFIFO_CTRL0) -#define VDIN_ASFIFO_CTRL1 0x1209 -#define P_VDIN_ASFIFO_CTRL1 VCBUS_REG_ADDR(VDIN_ASFIFO_CTRL1) -#define VDIN_WIDTHM1I_WIDTHM1O 0x120a -#define VDIN_SC_MISC_CTRL 0x120b -#define P_VDIN_SC_MISC_CTRL VCBUS_REG_ADDR(VDIN_SC_MISC_CTRL) -#define VDIN_HSC_PHASE_STEP 0x120c -#define P_VDIN_HSC_PHASE_STEP VCBUS_REG_ADDR(VDIN_HSC_PHASE_STEP) -#define VDIN_HSC_INI_CTRL 0x120d -#define P_VDIN_HSC_INI_CTRL VCBUS_REG_ADDR(VDIN_HSC_INI_CTRL) -#define VDIN_COM_STATUS2 0x120e -#define P_VDIN_COM_STATUS2 VCBUS_REG_ADDR(VDIN_COM_STATUS2) -#define VDIN_ASFIFO_CTRL2 0x120f -#define P_VDIN_ASFIFO_CTRL2 VCBUS_REG_ADDR(VDIN_ASFIFO_CTRL2) -#define VDIN_MATRIX_CTRL 0x1210 -#define P_VDIN_MATRIX_CTRL VCBUS_REG_ADDR(VDIN_MATRIX_CTRL) -#define VDIN_LFIFO_CTRL 0x121a -#define P_VDIN_LFIFO_CTRL VCBUS_REG_ADDR(VDIN_LFIFO_CTRL) -#define VDIN_COM_GCLK_CTRL 0x121b -#define P_VDIN_COM_GCLK_CTRL VCBUS_REG_ADDR(VDIN_COM_GCLK_CTRL) -#define VDIN_INTF_WIDTHM1 0x121c -#define P_VDIN_INTF_WIDTHM1 VCBUS_REG_ADDR(VDIN_INTF_WIDTHM1) -#define VDIN_WR_CTRL2 0x121f -#define P_VDIN_WR_CTRL2 VCBUS_REG_ADDR(VDIN_WR_CTRL2) -#define VDIN_WR_CTRL 0x1220 -#define P_VDIN_WR_CTRL VCBUS_REG_ADDR(VDIN_WR_CTRL) -#define VDIN_WR_H_START_END 0x1221 -#define P_VDIN_WR_H_START_END VCBUS_REG_ADDR(VDIN_WR_H_START_END) -#define VDIN_WR_V_START_END 0x1222 -#define P_VDIN_WR_V_START_END VCBUS_REG_ADDR(VDIN_WR_V_START_END) -#define VDIN_VSC_PHASE_STEP 0x1223 -#define P_VDIN_VSC_PHASE_STEP VCBUS_REG_ADDR(VDIN_VSC_PHASE_STEP) -#define VDIN_VSC_INI_CTRL 0x1224 -#define P_VDIN_VSC_INI_CTRL VCBUS_REG_ADDR(VDIN_VSC_INI_CTRL) -#define VDIN_SCIN_HEIGHTM1 0x1225 -#define P_VDIN_SCIN_HEIGHTM1 VCBUS_REG_ADDR(VDIN_SCIN_HEIGHTM1) -#define VDIN_DUMMY_DATA 0x1226 -#define P_VDIN_DUMMY_DATA VCBUS_REG_ADDR(VDIN_DUMMY_DATA) -#define VDIN_HIST_MAX_MIN 0x1233 -#define P_VDIN_HIST_MAX_MIN VCBUS_REG_ADDR(VDIN_HIST_MAX_MIN) -#define VDIN_HIST_SPL_VAL 0x1234 -#define P_VDIN_HIST_SPL_VAL VCBUS_REG_ADDR(VDIN_HIST_SPL_VAL) -#define VDIN_HIST_SPL_PIX_CNT 0x1235 -#define P_VDIN_HIST_CHROMA_SUM VCBUS_REG_ADDR(VDIN_HIST_CHROMA_SUM) -#define VDIN_DNLP_HIST00 0x1237 -#define P_VDIN_DNLP_HIST00 VCBUS_REG_ADDR(VDIN_DNLP_HIST00) -#define VDIN_DNLP_HIST01 0x1238 -#define P_VDIN_DNLP_HIST01 VCBUS_REG_ADDR(VDIN_DNLP_HIST01) -#define VDIN_DNLP_HIST02 0x1239 -#define P_VDIN_DNLP_HIST02 VCBUS_REG_ADDR(VDIN_DNLP_HIST02) -#define VDIN_DNLP_HIST03 0x123a -#define P_VDIN_DNLP_HIST03 VCBUS_REG_ADDR(VDIN_DNLP_HIST03) -#define VDIN_DNLP_HIST04 0x123b -#define P_VDIN_DNLP_HIST04 VCBUS_REG_ADDR(VDIN_DNLP_HIST04) -#define VDIN_DNLP_HIST05 0x123c -#define P_VDIN_DNLP_HIST05 VCBUS_REG_ADDR(VDIN_DNLP_HIST05) -#define VDIN_DNLP_HIST06 0x123d -#define P_VDIN_DNLP_HIST06 VCBUS_REG_ADDR(VDIN_DNLP_HIST06) -#define VDIN_DNLP_HIST07 0x123e -#define P_VDIN_DNLP_HIST07 VCBUS_REG_ADDR(VDIN_DNLP_HIST07) -#define VDIN_DNLP_HIST08 0x123f -#define P_VDIN_DNLP_HIST08 VCBUS_REG_ADDR(VDIN_DNLP_HIST08) -#define VDIN_DNLP_HIST09 0x1240 -#define P_VDIN_DNLP_HIST09 VCBUS_REG_ADDR(VDIN_DNLP_HIST09) -#define VDIN_DNLP_HIST10 0x1241 -#define P_VDIN_DNLP_HIST10 VCBUS_REG_ADDR(VDIN_DNLP_HIST10) -#define VDIN_DNLP_HIST11 0x1242 -#define P_VDIN_DNLP_HIST11 VCBUS_REG_ADDR(VDIN_DNLP_HIST11) -#define VDIN_DNLP_HIST12 0x1243 -#define P_VDIN_DNLP_HIST12 VCBUS_REG_ADDR(VDIN_DNLP_HIST12) -#define VDIN_DNLP_HIST13 0x1244 -#define P_VDIN_DNLP_HIST13 VCBUS_REG_ADDR(VDIN_DNLP_HIST13) -#define VDIN_DNLP_HIST14 0x1245 -#define P_VDIN_DNLP_HIST14 VCBUS_REG_ADDR(VDIN_DNLP_HIST14) -#define VDIN_DNLP_HIST15 0x1246 -#define P_VDIN_DNLP_HIST15 VCBUS_REG_ADDR(VDIN_DNLP_HIST15) -#define VDIN_DNLP_HIST16 0x1247 -#define P_VDIN_DNLP_HIST16 VCBUS_REG_ADDR(VDIN_DNLP_HIST16) -#define VDIN_DNLP_HIST17 0x1248 -#define P_VDIN_DNLP_HIST17 VCBUS_REG_ADDR(VDIN_DNLP_HIST17) -#define VDIN_DNLP_HIST18 0x1249 -#define P_VDIN_DNLP_HIST18 VCBUS_REG_ADDR(VDIN_DNLP_HIST18) -#define VDIN_DNLP_HIST19 0x124a -#define P_VDIN_DNLP_HIST19 VCBUS_REG_ADDR(VDIN_DNLP_HIST19) -#define VDIN_DNLP_HIST20 0x124b -#define P_VDIN_DNLP_HIST20 VCBUS_REG_ADDR(VDIN_DNLP_HIST20) -#define VDIN_DNLP_HIST21 0x124c -#define P_VDIN_DNLP_HIST21 VCBUS_REG_ADDR(VDIN_DNLP_HIST21) -#define VDIN_DNLP_HIST22 0x124d -#define P_VDIN_DNLP_HIST22 VCBUS_REG_ADDR(VDIN_DNLP_HIST22) -#define VDIN_DNLP_HIST23 0x124e -#define P_VDIN_DNLP_HIST23 VCBUS_REG_ADDR(VDIN_DNLP_HIST23) -#define VDIN_DNLP_HIST24 0x124f -#define P_VDIN_DNLP_HIST24 VCBUS_REG_ADDR(VDIN_DNLP_HIST24) -#define VDIN_DNLP_HIST25 0x1250 -#define P_VDIN_DNLP_HIST25 VCBUS_REG_ADDR(VDIN_DNLP_HIST25) -#define VDIN_DNLP_HIST26 0x1251 -#define P_VDIN_DNLP_HIST26 VCBUS_REG_ADDR(VDIN_DNLP_HIST26) -#define VDIN_DNLP_HIST27 0x1252 -#define P_VDIN_DNLP_HIST27 VCBUS_REG_ADDR(VDIN_DNLP_HIST27) -#define VDIN_DNLP_HIST28 0x1253 -#define P_VDIN_DNLP_HIST28 VCBUS_REG_ADDR(VDIN_DNLP_HIST28) -#define VDIN_DNLP_HIST29 0x1254 -#define P_VDIN_DNLP_HIST29 VCBUS_REG_ADDR(VDIN_DNLP_HIST29) -#define VDIN_DNLP_HIST30 0x1255 -#define P_VDIN_DNLP_HIST30 VCBUS_REG_ADDR(VDIN_DNLP_HIST30) -#define VDIN_DNLP_HIST31 0x1256 -#define P_VDIN_DNLP_HIST31 VCBUS_REG_ADDR(VDIN_DNLP_HIST31) - -#define P_VDIN1_ASFIFO_CTRL3 VCBUS_REG_ADDR(VDIN1_ASFIFO_CTRL3) -#define VPP_DUMMY_DATA 0x1d00 -#define P_VPP_DUMMY_DATA VCBUS_REG_ADDR(VPP_DUMMY_DATA) -#define VPP_LINE_IN_LENGTH 0x1d01 -#define P_VPP_LINE_IN_LENGTH VCBUS_REG_ADDR(VPP_LINE_IN_LENGTH) -#define VPP_PIC_IN_HEIGHT 0x1d02 -#define P_VPP_PIC_IN_HEIGHT VCBUS_REG_ADDR(VPP_PIC_IN_HEIGHT) -#define VPP_SCALE_COEF_IDX 0x1d03 -#define P_VPP_SCALE_COEF_IDX VCBUS_REG_ADDR(VPP_SCALE_COEF_IDX) -#define VPP_SCALE_COEF 0x1d04 -#define P_VPP_SCALE_COEF VCBUS_REG_ADDR(VPP_SCALE_COEF) - -#define VPP_VSC_PHASE_CTRL 0x1d0d -#define P_VPP_VSC_PHASE_CTRL VCBUS_REG_ADDR(VPP_VSC_PHASE_CTRL) -#define VPP_VSC_INI_PHASE 0x1d0e -#define P_VPP_VSC_INI_PHASE VCBUS_REG_ADDR(VPP_VSC_INI_PHASE) -#define VPP_HSC_REGION12_STARTP 0x1d10 - -#define VPP_DUMMY_DATA1 0x1d69 -#define P_VPP_DUMMY_DATA1 VCBUS_REG_ADDR(VPP_DUMMY_DATA1) -#define VPP_GAINOFF_CTRL0 0x1d6a -#define P_VPP_GAINOFF_CTRL0 VCBUS_REG_ADDR(VPP_GAINOFF_CTRL0) -#define VPP_GAINOFF_CTRL1 0x1d6b -#define P_VPP_GAINOFF_CTRL1 VCBUS_REG_ADDR(VPP_GAINOFF_CTRL1) -#define VPP_GAINOFF_CTRL2 0x1d6c -#define P_VPP_GAINOFF_CTRL2 VCBUS_REG_ADDR(VPP_GAINOFF_CTRL2) -#define VPP_GAINOFF_CTRL3 0x1d6d -#define P_VPP_GAINOFF_CTRL3 VCBUS_REG_ADDR(VPP_GAINOFF_CTRL3) -#define VPP_GAINOFF_CTRL4 0x1d6e -#define P_VPP_GAINOFF_CTRL4 VCBUS_REG_ADDR(VPP_GAINOFF_CTRL4) -#define VPP_CHROMA_ADDR_PORT 0x1d70 -#define P_VPP_CHROMA_ADDR_PORT VCBUS_REG_ADDR(VPP_CHROMA_ADDR_PORT) -#define VPP_CHROMA_DATA_PORT 0x1d71 -#define P_VPP_CHROMA_DATA_PORT VCBUS_REG_ADDR(VPP_CHROMA_DATA_PORT) -#define VPP_GCLK_CTRL0 0x1d72 -#define P_VPP_GCLK_CTRL0 VCBUS_REG_ADDR(VPP_GCLK_CTRL0) -#define VPP_GCLK_CTRL1 0x1d73 -#define P_VPP_GCLK_CTRL1 VCBUS_REG_ADDR(VPP_GCLK_CTRL1) -#define VPP_SC_GCLK_CTRL 0x1d74 -#define P_VPP_SC_GCLK_CTRL VCBUS_REG_ADDR(VPP_SC_GCLK_CTRL) -#define VPP_MISC1 0x1d76 -#define P_VPP_MISC1 VCBUS_REG_ADDR(VPP_MISC1) -#define VPP_BLACKEXT_CTRL 0x1d80 -#define P_VPP_BLACKEXT_CTRL VCBUS_REG_ADDR(VPP_BLACKEXT_CTRL) -#define VPP_DNLP_CTRL_00 0x1d81 -#define P_VPP_DNLP_CTRL_00 VCBUS_REG_ADDR(VPP_DNLP_CTRL_00) -#define VPP_DNLP_CTRL_01 0x1d82 -#define P_VPP_DNLP_CTRL_01 VCBUS_REG_ADDR(VPP_DNLP_CTRL_01) -#define VPP_DNLP_CTRL_02 0x1d83 -#define P_VPP_DNLP_CTRL_02 VCBUS_REG_ADDR(VPP_DNLP_CTRL_02) -#define VPP_DNLP_CTRL_03 0x1d84 -#define P_VPP_DNLP_CTRL_03 VCBUS_REG_ADDR(VPP_DNLP_CTRL_03) -#define VPP_DNLP_CTRL_04 0x1d85 -#define P_VPP_DNLP_CTRL_04 VCBUS_REG_ADDR(VPP_DNLP_CTRL_04) -#define VPP_DNLP_CTRL_05 0x1d86 -#define P_VPP_DNLP_CTRL_05 VCBUS_REG_ADDR(VPP_DNLP_CTRL_05) -#define VPP_DNLP_CTRL_06 0x1d87 -#define P_VPP_DNLP_CTRL_06 VCBUS_REG_ADDR(VPP_DNLP_CTRL_06) -#define VPP_DNLP_CTRL_07 0x1d88 -#define P_VPP_DNLP_CTRL_07 VCBUS_REG_ADDR(VPP_DNLP_CTRL_07) -#define VPP_DNLP_CTRL_08 0x1d89 -#define P_VPP_DNLP_CTRL_08 VCBUS_REG_ADDR(VPP_DNLP_CTRL_08) -#define VPP_DNLP_CTRL_09 0x1d8a -#define P_VPP_DNLP_CTRL_09 VCBUS_REG_ADDR(VPP_DNLP_CTRL_09) -#define VPP_DNLP_CTRL_10 0x1d8b -#define P_VPP_DNLP_CTRL_10 VCBUS_REG_ADDR(VPP_DNLP_CTRL_10) -#define VPP_DNLP_CTRL_11 0x1d8c -#define P_VPP_DNLP_CTRL_11 VCBUS_REG_ADDR(VPP_DNLP_CTRL_11) -#define VPP_DNLP_CTRL_12 0x1d8d -#define P_VPP_DNLP_CTRL_12 VCBUS_REG_ADDR(VPP_DNLP_CTRL_12) -#define VPP_DNLP_CTRL_13 0x1d8e -#define P_VPP_DNLP_CTRL_13 VCBUS_REG_ADDR(VPP_DNLP_CTRL_13) -#define VPP_DNLP_CTRL_14 0x1d8f -#define P_VPP_DNLP_CTRL_14 VCBUS_REG_ADDR(VPP_DNLP_CTRL_14) -#define VPP_DNLP_CTRL_15 0x1d90 -#define P_VPP_DNLP_CTRL_15 VCBUS_REG_ADDR(VPP_DNLP_CTRL_15) -#define VPP_PEAKING_HGAIN 0x1d91 -#define P_VPP_PEAKING_HGAIN VCBUS_REG_ADDR(VPP_PEAKING_HGAIN) -#define VPP_PEAKING_VGAIN 0x1d92 -#define P_VPP_PEAKING_VGAIN VCBUS_REG_ADDR(VPP_PEAKING_VGAIN) -#define VPP_PEAKING_NLP_1 0x1d93 -#define P_VPP_PEAKING_NLP_1 VCBUS_REG_ADDR(VPP_PEAKING_NLP_1) -#define VPP_PEAKING_NLP_2 0x1d94 -#define P_VPP_PEAKING_NLP_2 VCBUS_REG_ADDR(VPP_PEAKING_NLP_2) -#define VPP_PEAKING_NLP_3 0x1d95 -#define P_VPP_PEAKING_NLP_3 VCBUS_REG_ADDR(VPP_PEAKING_NLP_3) -#define VPP_PEAKING_NLP_4 0x1d96 -#define P_VPP_PEAKING_NLP_4 VCBUS_REG_ADDR(VPP_PEAKING_NLP_4) -#define VPP_PEAKING_NLP_5 0x1d97 -#define P_VPP_PEAKING_NLP_5 VCBUS_REG_ADDR(VPP_PEAKING_NLP_5) -#define VPP_SHARP_LIMIT 0x1d98 -#define P_VPP_SHARP_LIMIT VCBUS_REG_ADDR(VPP_SHARP_LIMIT) -#define VPP_VLTI_CTRL 0x1d99 -#define P_VPP_VLTI_CTRL VCBUS_REG_ADDR(VPP_VLTI_CTRL) -#define VPP_HLTI_CTRL 0x1d9a -#define P_VPP_HLTI_CTRL VCBUS_REG_ADDR(VPP_HLTI_CTRL) -#define VPP_CTI_CTRL 0x1d9b -#define P_VPP_CTI_CTRL VCBUS_REG_ADDR(VPP_CTI_CTRL) -#define VPP_BLUE_STRETCH_1 0x1d9c -#define P_VPP_BLUE_STRETCH_1 VCBUS_REG_ADDR(VPP_BLUE_STRETCH_1) -#define VPP_BLUE_STRETCH_2 0x1d9d -#define P_VPP_BLUE_STRETCH_2 VCBUS_REG_ADDR(VPP_BLUE_STRETCH_2) -#define VPP_BLUE_STRETCH_3 0x1d9e -#define P_VPP_BLUE_STRETCH_3 VCBUS_REG_ADDR(VPP_BLUE_STRETCH_3) -#define VPP_CCORING_CTRL 0x1da0 -#define P_VPP_CCORING_CTRL VCBUS_REG_ADDR(VPP_CCORING_CTRL) -#define VPP_VE_ENABLE_CTRL 0x1da1 -#define P_VPP_VE_ENABLE_CTRL VCBUS_REG_ADDR(VPP_VE_ENABLE_CTRL) -#define VPP_INPUT_CTRL 0x1dab -#define P_VPP_INPUT_CTRL VCBUS_REG_ADDR(VPP_INPUT_CTRL) -#define VPP_CTI_CTRL2 0x1dac -#define P_VPP_CTI_CTRL2 VCBUS_REG_ADDR(VPP_CTI_CTRL2) -#define VPP_PEAKING_SAT_THD1 0x1dad -#define P_VPP_PEAKING_SAT_THD1 VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD1) -#define VPP_PEAKING_SAT_THD2 0x1dae -#define P_VPP_PEAKING_SAT_THD2 VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD2) -#define VPP_PEAKING_SAT_THD3 0x1daf -#define P_VPP_PEAKING_SAT_THD3 VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD3) -#define VPP_PEAKING_SAT_THD4 0x1db0 -#define P_VPP_PEAKING_SAT_THD4 VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD4) -#define VPP_PEAKING_SAT_THD5 0x1db1 -#define P_VPP_PEAKING_SAT_THD5 VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD5) -#define VPP_PEAKING_SAT_THD6 0x1db2 -#define P_VPP_PEAKING_SAT_THD6 VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD6) -#define VPP_PEAKING_SAT_THD7 0x1db3 -#define P_VPP_PEAKING_SAT_THD7 VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD7) -#define VPP_PEAKING_SAT_THD8 0x1db4 -#define P_VPP_PEAKING_SAT_THD8 VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD8) -#define VPP_PEAKING_SAT_THD9 0x1db5 -#define P_VPP_PEAKING_SAT_THD9 VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD9) -#define VPP_PEAKING_GAIN_ADD1 0x1db6 -#define VPP2_GCLK_CTRL0 0x1972 -#define P_VPP2_GCLK_CTRL0 VCBUS_REG_ADDR(VPP2_GCLK_CTRL0) -#define VPP2_GCLK_CTRL1 0x1973 -#define P_VPP2_GCLK_CTRL1 VCBUS_REG_ADDR(VPP2_GCLK_CTRL1) -#define VPP2_SC_GCLK_CTRL 0x1974 -#define P_VPP2_SC_GCLK_CTRL VCBUS_REG_ADDR(VPP2_SC_GCLK_CTRL) -#define VPP2_MISC1 0x1976 -#define P_VPP2_MISC1 VCBUS_REG_ADDR(VPP2_MISC1) -#define VPP2_DNLP_CTRL_00 0x1981 -#define P_VPP2_DNLP_CTRL_00 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_00) -#define VPP2_DNLP_CTRL_01 0x1982 -#define P_VPP2_DNLP_CTRL_01 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_01) -#define VPP2_DNLP_CTRL_02 0x1983 -#define P_VPP2_DNLP_CTRL_02 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_02) -#define VPP2_DNLP_CTRL_03 0x1984 -#define P_VPP2_DNLP_CTRL_03 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_03) -#define VPP2_DNLP_CTRL_04 0x1985 -#define P_VPP2_DNLP_CTRL_04 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_04) -#define VPP2_DNLP_CTRL_05 0x1986 -#define P_VPP2_DNLP_CTRL_05 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_05) -#define VPP2_DNLP_CTRL_06 0x1987 -#define P_VPP2_DNLP_CTRL_06 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_06) -#define VPP2_DNLP_CTRL_07 0x1988 -#define P_VPP2_DNLP_CTRL_07 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_07) -#define VPP2_DNLP_CTRL_08 0x1989 -#define P_VPP2_DNLP_CTRL_08 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_08) -#define VPP2_DNLP_CTRL_09 0x198a -#define P_VPP2_DNLP_CTRL_09 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_09) -#define VPP2_DNLP_CTRL_10 0x198b -#define P_VPP2_DNLP_CTRL_10 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_10) -#define VPP2_DNLP_CTRL_11 0x198c -#define P_VPP2_DNLP_CTRL_11 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_11) -#define VPP2_DNLP_CTRL_12 0x198d -#define P_VPP2_DNLP_CTRL_12 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_12) -#define VPP2_DNLP_CTRL_13 0x198e -#define P_VPP2_DNLP_CTRL_13 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_13) -#define VPP2_DNLP_CTRL_14 0x198f -#define P_VPP2_DNLP_CTRL_14 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_14) -#define VPP2_DNLP_CTRL_15 0x1990 -#define P_VPP2_DNLP_CTRL_15 VCBUS_REG_ADDR(VPP2_DNLP_CTRL_15) -#define VPP2_VE_ENABLE_CTRL 0x19a1 -#define P_VPP2_VE_ENABLE_CTRL VCBUS_REG_ADDR(VPP2_VE_ENABLE_CTRL) -#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 -#define VPP2_OSD_SCALE_COEF 0x19cd -#define P_VPP2_OSD_SCALE_COEF VCBUS_REG_ADDR(VPP2_OSD_SCALE_COEF) -#define VPP2_INT_LINE_NUM 0x19ce -#define P_VPP2_INT_LINE_NUM VCBUS_REG_ADDR(VPP2_INT_LINE_NUM) -#define VIU_ADDR_START 0x1a00 -#define P_VIU_ADDR_START VCBUS_REG_ADDR(VIU_ADDR_START) -#define VIU_ADDR_END 0x1aff -#define P_VIU_ADDR_END VCBUS_REG_ADDR(VIU_ADDR_END) -#define VIU_SW_RESET 0x1a01 -#define P_VIU_SW_RESET VCBUS_REG_ADDR(VIU_SW_RESET) -#define VIU_MISC_CTRL0 0x1a06 -#define P_VIU_MISC_CTRL0 VCBUS_REG_ADDR(VIU_MISC_CTRL0) -#define D2D3_INTF_LENGTH 0x1a08 -#define P_D2D3_INTF_LENGTH VCBUS_REG_ADDR(D2D3_INTF_LENGTH) -#define D2D3_INTF_CTRL0 0x1a09 -#define P_D2D3_INTF_CTRL0 VCBUS_REG_ADDR(D2D3_INTF_CTRL0) -#define VIU_OSD1_CTRL_STAT 0x1a10 -#define P_VIU_OSD1_CTRL_STAT VCBUS_REG_ADDR(VIU_OSD1_CTRL_STAT) -#define VIU_OSD1_CTRL_STAT2 0x1a2d -#define P_VIU_OSD1_CTRL_STAT2 VCBUS_REG_ADDR(VIU_OSD1_CTRL_STAT2) -#define VIU_OSD1_COLOR_ADDR 0x1a11 -#define P_VIU_OSD1_COLOR_ADDR VCBUS_REG_ADDR(VIU_OSD1_COLOR_ADDR) -#define VIU_OSD1_COLOR 0x1a12 -#define P_VIU_OSD1_COLOR VCBUS_REG_ADDR(VIU_OSD1_COLOR) -#define VIU_OSD1_TCOLOR_AG0 0x1a17 -#define P_VIU_OSD1_TCOLOR_AG0 VCBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG0) -#define VIU_OSD1_TCOLOR_AG1 0x1a18 -#define P_VIU_OSD1_TCOLOR_AG1 VCBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG1) -#define VIU_OSD1_TCOLOR_AG2 0x1a19 -#define P_VIU_OSD1_TCOLOR_AG2 VCBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG2) -#define VIU_OSD1_TCOLOR_AG3 0x1a1a -#define P_VIU_OSD1_TCOLOR_AG3 VCBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG3) -#define VIU_OSD1_BLK0_CFG_W0 0x1a1b -#define P_VIU_OSD1_BLK0_CFG_W0 VCBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W0) -#define VIU_OSD1_BLK1_CFG_W0 0x1a1f -#define P_VIU_OSD1_BLK1_CFG_W0 VCBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W0) -#define VIU_OSD1_BLK2_CFG_W0 0x1a23 -#define P_VIU_OSD1_BLK2_CFG_W0 VCBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W0) -#define VIU_OSD1_BLK3_CFG_W0 0x1a27 -#define P_VIU_OSD1_BLK3_CFG_W0 VCBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W0) -#define VIU_OSD1_BLK0_CFG_W1 0x1a1c -#define P_VIU_OSD1_BLK0_CFG_W1 VCBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W1) -#define VIU_OSD1_BLK1_CFG_W1 0x1a20 -#define P_VIU_OSD1_BLK1_CFG_W1 VCBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W1) -#define VIU_OSD1_BLK2_CFG_W1 0x1a24 -#define P_VIU_OSD1_BLK2_CFG_W1 VCBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W1) -#define VIU_OSD1_BLK3_CFG_W1 0x1a28 -#define P_VIU_OSD1_BLK3_CFG_W1 VCBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W1) -#define VIU_OSD1_BLK0_CFG_W2 0x1a1d -#define P_VIU_OSD1_BLK0_CFG_W2 VCBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W2) -#define VIU_OSD1_BLK1_CFG_W2 0x1a21 -#define P_VIU_OSD1_BLK1_CFG_W2 VCBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W2) -#define VIU_OSD1_BLK2_CFG_W2 0x1a25 -#define P_VIU_OSD1_BLK2_CFG_W2 VCBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W2) -#define VIU_OSD1_BLK3_CFG_W2 0x1a29 -#define P_VIU_OSD1_BLK3_CFG_W2 VCBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W2) -#define VIU_OSD1_BLK0_CFG_W3 0x1a1e -#define P_VIU_OSD1_BLK0_CFG_W3 VCBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W3) -#define VIU_OSD1_BLK1_CFG_W3 0x1a22 -#define P_VIU_OSD1_BLK1_CFG_W3 VCBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W3) -#define VIU_OSD1_BLK2_CFG_W3 0x1a26 -#define P_VIU_OSD1_BLK2_CFG_W3 VCBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W3) -#define VIU_OSD1_BLK3_CFG_W3 0x1a2a -#define P_VIU_OSD1_BLK3_CFG_W3 VCBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W3) -#define VIU_OSD1_BLK0_CFG_W4 0x1a13 -#define P_VIU_OSD1_BLK0_CFG_W4 VCBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W4) -#define VIU_OSD1_BLK1_CFG_W4 0x1a14 -#define P_VIU_OSD1_BLK1_CFG_W4 VCBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W4) -#define VIU_OSD1_BLK2_CFG_W4 0x1a15 -#define P_VIU_OSD1_BLK2_CFG_W4 VCBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W4) -#define VIU_OSD1_BLK3_CFG_W4 0x1a16 -#define P_VIU_OSD1_BLK3_CFG_W4 VCBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W4) -#define VIU_OSD1_TEST_RDDATA 0x1a2c -#define P_VIU_OSD1_TEST_RDDATA VCBUS_REG_ADDR(VIU_OSD1_TEST_RDDATA) -#define VIU_OSD1_PROT_CTRL 0x1a2e -#define P_VIU_OSD1_PROT_CTRL VCBUS_REG_ADDR(VIU_OSD1_PROT_CTRL) -#define VIU_OSD2_CTRL_STAT 0x1a30 -#define P_VIU_OSD2_CTRL_STAT VCBUS_REG_ADDR(VIU_OSD2_CTRL_STAT) -#define VIU_OSD2_CTRL_STAT2 0x1a4d -#define P_VIU_OSD2_CTRL_STAT2 VCBUS_REG_ADDR(VIU_OSD2_CTRL_STAT2) -#define VIU_OSD2_COLOR_ADDR 0x1a31 -#define P_VIU_OSD2_COLOR_ADDR VCBUS_REG_ADDR(VIU_OSD2_COLOR_ADDR) -#define VIU_OSD2_COLOR 0x1a32 -#define P_VIU_OSD2_COLOR VCBUS_REG_ADDR(VIU_OSD2_COLOR) -#define VIU_OSD2_HL1_H_START_END 0x1a33 -#define VIU_OSD2_TCOLOR_AG0 0x1a37 -#define P_VIU_OSD2_TCOLOR_AG0 VCBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG0) -#define VIU_OSD2_TCOLOR_AG1 0x1a38 -#define P_VIU_OSD2_TCOLOR_AG1 VCBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG1) -#define VIU_OSD2_TCOLOR_AG2 0x1a39 -#define P_VIU_OSD2_TCOLOR_AG2 VCBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG2) -#define VIU_OSD2_TCOLOR_AG3 0x1a3a -#define P_VIU_OSD2_TCOLOR_AG3 VCBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG3) -#define VIU_OSD2_BLK0_CFG_W0 0x1a3b -#define P_VIU_OSD2_BLK0_CFG_W0 VCBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W0) -#define VIU_OSD2_BLK1_CFG_W0 0x1a3f -#define P_VIU_OSD2_BLK1_CFG_W0 VCBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W0) -#define VIU_OSD2_BLK2_CFG_W0 0x1a43 -#define P_VIU_OSD2_BLK2_CFG_W0 VCBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W0) -#define VIU_OSD2_BLK3_CFG_W0 0x1a47 -#define P_VIU_OSD2_BLK3_CFG_W0 VCBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W0) -#define VIU_OSD2_BLK0_CFG_W1 0x1a3c -#define P_VIU_OSD2_BLK0_CFG_W1 VCBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W1) -#define VIU_OSD2_BLK1_CFG_W1 0x1a40 -#define P_VIU_OSD2_BLK1_CFG_W1 VCBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W1) -#define VIU_OSD2_BLK2_CFG_W1 0x1a44 -#define P_VIU_OSD2_BLK2_CFG_W1 VCBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W1) -#define VIU_OSD2_BLK3_CFG_W1 0x1a48 -#define P_VIU_OSD2_BLK3_CFG_W1 VCBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W1) -#define VIU_OSD2_BLK0_CFG_W2 0x1a3d -#define P_VIU_OSD2_BLK0_CFG_W2 VCBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W2) -#define VIU_OSD2_BLK1_CFG_W2 0x1a41 -#define P_VIU_OSD2_BLK1_CFG_W2 VCBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W2) -#define VIU_OSD2_BLK2_CFG_W2 0x1a45 -#define P_VIU_OSD2_BLK2_CFG_W2 VCBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W2) -#define VIU_OSD2_BLK3_CFG_W2 0x1a49 -#define P_VIU_OSD2_BLK3_CFG_W2 VCBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W2) -#define VIU_OSD2_BLK0_CFG_W3 0x1a3e -#define P_VIU_OSD2_BLK0_CFG_W3 VCBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W3) -#define VIU_OSD2_BLK1_CFG_W3 0x1a42 -#define P_VIU_OSD2_BLK1_CFG_W3 VCBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W3) -#define VIU_OSD2_BLK2_CFG_W3 0x1a46 -#define P_VIU_OSD2_BLK2_CFG_W3 VCBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W3) -#define VIU_OSD2_BLK3_CFG_W3 0x1a4a -#define P_VIU_OSD2_BLK3_CFG_W3 VCBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W3) -#define VIU_OSD2_BLK0_CFG_W4 0x1a64 -#define P_VIU_OSD2_BLK0_CFG_W4 VCBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W4) -#define VIU_OSD2_BLK1_CFG_W4 0x1a65 -#define P_VIU_OSD2_BLK1_CFG_W4 VCBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W4) -#define VIU_OSD2_BLK2_CFG_W4 0x1a66 -#define P_VIU_OSD2_BLK2_CFG_W4 VCBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W4) -#define VIU_OSD2_BLK3_CFG_W4 0x1a67 -#define P_VIU_OSD2_BLK3_CFG_W4 VCBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W4) -#define VIU_OSD2_TEST_RDDATA 0x1a4c -#define P_VIU_OSD2_TEST_RDDATA VCBUS_REG_ADDR(VIU_OSD2_TEST_RDDATA) -#define VIU_OSD2_PROT_CTRL 0x1a4e -#define P_VIU_OSD2_PROT_CTRL VCBUS_REG_ADDR(VIU_OSD2_PROT_CTRL) -#define VD1_IF0_GEN_REG 0x1a50 -#define P_VD1_IF0_GEN_REG VCBUS_REG_ADDR(VD1_IF0_GEN_REG) -#define VD1_IF0_CANVAS0 0x1a51 -#define P_VD1_IF0_CANVAS0 VCBUS_REG_ADDR(VD1_IF0_CANVAS0) -#define VD1_IF0_CANVAS1 0x1a52 -#define P_VD1_IF0_CANVAS1 VCBUS_REG_ADDR(VD1_IF0_CANVAS1) -#define VD1_IF0_LUMA_X0 0x1a53 -#define P_VD1_IF0_LUMA_X0 VCBUS_REG_ADDR(VD1_IF0_LUMA_X0) -#define VD1_IF0_LUMA_Y0 0x1a54 -#define P_VD1_IF0_LUMA_Y0 VCBUS_REG_ADDR(VD1_IF0_LUMA_Y0) -#define VD1_IF0_CHROMA_X0 0x1a55 -#define P_VD1_IF0_CHROMA_X0 VCBUS_REG_ADDR(VD1_IF0_CHROMA_X0) -#define VD1_IF0_CHROMA_Y0 0x1a56 -#define P_VD1_IF0_CHROMA_Y0 VCBUS_REG_ADDR(VD1_IF0_CHROMA_Y0) -#define VD1_IF0_LUMA_X1 0x1a57 -#define P_VD1_IF0_LUMA_X1 VCBUS_REG_ADDR(VD1_IF0_LUMA_X1) -#define VD1_IF0_LUMA_Y1 0x1a58 -#define P_VD1_IF0_LUMA_Y1 VCBUS_REG_ADDR(VD1_IF0_LUMA_Y1) -#define VD1_IF0_CHROMA_X1 0x1a59 -#define P_VD1_IF0_CHROMA_X1 VCBUS_REG_ADDR(VD1_IF0_CHROMA_X1) -#define VD1_IF0_CHROMA_Y1 0x1a5a -#define P_VD1_IF0_CHROMA_Y1 VCBUS_REG_ADDR(VD1_IF0_CHROMA_Y1) -#define VD1_IF0_RPT_LOOP 0x1a5b -#define P_VD1_IF0_RPT_LOOP VCBUS_REG_ADDR(VD1_IF0_RPT_LOOP) - -#define VD1_IF0_LUMA_PSEL 0x1a60 -#define P_VD1_IF0_LUMA_PSEL VCBUS_REG_ADDR(VD1_IF0_LUMA_PSEL) -#define VD1_IF0_CHROMA_PSEL 0x1a61 -#define P_VD1_IF0_CHROMA_PSEL VCBUS_REG_ADDR(VD1_IF0_CHROMA_PSEL) -#define VD1_IF0_DUMMY_PIXEL 0x1a62 -#define P_VD1_IF0_DUMMY_PIXEL VCBUS_REG_ADDR(VD1_IF0_DUMMY_PIXEL) -#define VD1_IF0_RANGE_MAP_Y 0x1a6a -#define P_VD1_IF0_RANGE_MAP_Y VCBUS_REG_ADDR(VD1_IF0_RANGE_MAP_Y) -#define VD1_IF0_RANGE_MAP_CB 0x1a6b -#define P_VD1_IF0_RANGE_MAP_CB VCBUS_REG_ADDR(VD1_IF0_RANGE_MAP_CB) -#define VD1_IF0_RANGE_MAP_CR 0x1a6c -#define P_VD1_IF0_RANGE_MAP_CR VCBUS_REG_ADDR(VD1_IF0_RANGE_MAP_CR) -#define VD1_IF0_GEN_REG2 0x1a6d -#define P_VD1_IF0_GEN_REG2 VCBUS_REG_ADDR(VD1_IF0_GEN_REG2) -#define VD1_IF0_PROT_CNTL 0x1a6e -#define P_VD1_IF0_PROT_CNTL VCBUS_REG_ADDR(VD1_IF0_PROT_CNTL) -#define VIU_VD1_FMT_CTRL 0x1a68 -#define P_VIU_VD1_FMT_CTRL VCBUS_REG_ADDR(VIU_VD1_FMT_CTRL) -#define VIU_VD1_FMT_W 0x1a69 -#define P_VIU_VD1_FMT_W VCBUS_REG_ADDR(VIU_VD1_FMT_W) -#define VD2_IF0_GEN_REG 0x1a70 -#define P_VD2_IF0_GEN_REG VCBUS_REG_ADDR(VD2_IF0_GEN_REG) -#define VD2_IF0_CANVAS0 0x1a71 -#define P_VD2_IF0_CANVAS0 VCBUS_REG_ADDR(VD2_IF0_CANVAS0) -#define VD2_IF0_CANVAS1 0x1a72 -#define P_VD2_IF0_CANVAS1 VCBUS_REG_ADDR(VD2_IF0_CANVAS1) -#define VD2_IF0_LUMA_X0 0x1a73 -#define P_VD2_IF0_LUMA_X0 VCBUS_REG_ADDR(VD2_IF0_LUMA_X0) -#define VD2_IF0_LUMA_Y0 0x1a74 -#define P_VD2_IF0_LUMA_Y0 VCBUS_REG_ADDR(VD2_IF0_LUMA_Y0) -#define VD2_IF0_CHROMA_X0 0x1a75 -#define P_VD2_IF0_CHROMA_X0 VCBUS_REG_ADDR(VD2_IF0_CHROMA_X0) -#define VD2_IF0_CHROMA_Y0 0x1a76 -#define P_VD2_IF0_CHROMA_Y0 VCBUS_REG_ADDR(VD2_IF0_CHROMA_Y0) -#define VD2_IF0_LUMA_X1 0x1a77 -#define P_VD2_IF0_LUMA_X1 VCBUS_REG_ADDR(VD2_IF0_LUMA_X1) -#define VD2_IF0_LUMA_Y1 0x1a78 -#define P_VD2_IF0_LUMA_Y1 VCBUS_REG_ADDR(VD2_IF0_LUMA_Y1) -#define VD2_IF0_CHROMA_X1 0x1a79 -#define P_VD2_IF0_CHROMA_X1 VCBUS_REG_ADDR(VD2_IF0_CHROMA_X1) -#define VD2_IF0_CHROMA_Y1 0x1a7a -#define P_VD2_IF0_CHROMA_Y1 VCBUS_REG_ADDR(VD2_IF0_CHROMA_Y1) - -#define VD2_IF0_LUMA_PSEL 0x1a80 -#define P_VD2_IF0_LUMA_PSEL VCBUS_REG_ADDR(VD2_IF0_LUMA_PSEL) -#define VD2_IF0_CHROMA_PSEL 0x1a81 -#define P_VD2_IF0_CHROMA_PSEL VCBUS_REG_ADDR(VD2_IF0_CHROMA_PSEL) -#define VD2_IF0_DUMMY_PIXEL 0x1a82 -#define P_VD2_IF0_DUMMY_PIXEL VCBUS_REG_ADDR(VD2_IF0_DUMMY_PIXEL) -#define VD2_IF0_LUMA_FIFO_SIZE 0x1a83 -#define P_VD2_IF0_RANGE_MAP_Y VCBUS_REG_ADDR(VD2_IF0_RANGE_MAP_Y) -#define VD2_IF0_RANGE_MAP_CB 0x1a8b -#define P_VD2_IF0_RANGE_MAP_CB VCBUS_REG_ADDR(VD2_IF0_RANGE_MAP_CB) -#define VD2_IF0_RANGE_MAP_CR 0x1a8c -#define P_VD2_IF0_RANGE_MAP_CR VCBUS_REG_ADDR(VD2_IF0_RANGE_MAP_CR) -#define VD2_IF0_GEN_REG2 0x1a8d -#define P_VD2_IF0_GEN_REG2 VCBUS_REG_ADDR(VD2_IF0_GEN_REG2) -#define VD2_IF0_PROT_CNTL 0x1a8e -#define P_VD2_IF0_PROT_CNTL VCBUS_REG_ADDR(VD2_IF0_PROT_CNTL) -#define VIU_VD2_FMT_CTRL 0x1a88 -#define P_VIU_VD2_FMT_CTRL VCBUS_REG_ADDR(VIU_VD2_FMT_CTRL) -#define VIU_VD2_FMT_W 0x1a89 -#define P_VIU_VD2_FMT_W VCBUS_REG_ADDR(VIU_VD2_FMT_W) -#define LDIM_STTS_GCLK_CTRL0 0x1a90 -#define P_LDIM_STTS_GCLK_CTRL0 VCBUS_REG_ADDR(LDIM_STTS_GCLK_CTRL0) -#define LDIM_STTS_CTRL0 0x1a91 -#define P_LDIM_STTS_CTRL0 VCBUS_REG_ADDR(LDIM_STTS_CTRL0) - -#define DI_PRE_CTRL 0x1700 -#define P_DI_PRE_CTRL VCBUS_REG_ADDR(DI_PRE_CTRL) -#define DI_POST_CTRL 0x1701 -#define P_DI_POST_CTRL VCBUS_REG_ADDR(DI_POST_CTRL) -#define DI_POST_SIZE 0x1702 -#define P_DI_POST_SIZE VCBUS_REG_ADDR(DI_POST_SIZE) -#define DI_PRE_SIZE 0x1703 -#define P_DI_PRE_SIZE VCBUS_REG_ADDR(DI_PRE_SIZE) -#define DI_EI_CTRL0 0x1704 -#define P_DI_EI_CTRL0 VCBUS_REG_ADDR(DI_EI_CTRL0) -#define DI_EI_CTRL1 0x1705 -#define P_DI_EI_CTRL1 VCBUS_REG_ADDR(DI_EI_CTRL1) -#define DI_EI_CTRL2 0x1706 -#define P_DI_EI_CTRL2 VCBUS_REG_ADDR(DI_EI_CTRL2) -#define DI_NR_CTRL0 0x1707 -#define P_DI_NR_CTRL0 VCBUS_REG_ADDR(DI_NR_CTRL0) -#define DI_NR_CTRL1 0x1708 -#define P_DI_NR_CTRL1 VCBUS_REG_ADDR(DI_NR_CTRL1) -#define DI_NR_CTRL2 0x1709 -#define P_DI_NR_CTRL2 VCBUS_REG_ADDR(DI_NR_CTRL2) -#define DI_NR_CTRL3 0x170a -#define P_DI_NR_CTRL3 VCBUS_REG_ADDR(DI_NR_CTRL3) -#define DI_MTN_CTRL 0x170b -#define P_DI_MTN_CTRL VCBUS_REG_ADDR(DI_MTN_CTRL) -#define DI_MTN_CTRL1 0x170c -#define P_DI_MTN_CTRL1 VCBUS_REG_ADDR(DI_MTN_CTRL1) -#define DI_BLEND_CTRL 0x170d -#define P_DI_BLEND_CTRL VCBUS_REG_ADDR(DI_BLEND_CTRL) -#define DI_BLEND_CTRL1 0x170e -#define P_DI_BLEND_CTRL1 VCBUS_REG_ADDR(DI_BLEND_CTRL1) -#define DI_BLEND_CTRL2 0x170f -#define P_DI_BLEND_CTRL2 VCBUS_REG_ADDR(DI_BLEND_CTRL2) -#define DI_BLEND_REG0_X 0x1710 -#define P_DI_BLEND_REG0_X VCBUS_REG_ADDR(DI_BLEND_REG0_X) -#define DI_BLEND_REG0_Y 0x1711 -#define P_DI_BLEND_REG0_Y VCBUS_REG_ADDR(DI_BLEND_REG0_Y) -#define DI_BLEND_REG1_X 0x1712 -#define P_DI_BLEND_REG1_X VCBUS_REG_ADDR(DI_BLEND_REG1_X) -#define DI_BLEND_REG1_Y 0x1713 -#define P_DI_BLEND_REG1_Y VCBUS_REG_ADDR(DI_BLEND_REG1_Y) -#define DI_BLEND_REG2_X 0x1714 -#define P_DI_BLEND_REG2_X VCBUS_REG_ADDR(DI_BLEND_REG2_X) -#define DI_BLEND_REG2_Y 0x1715 -#define P_DI_BLEND_REG2_Y VCBUS_REG_ADDR(DI_BLEND_REG2_Y) -#define DI_BLEND_REG3_X 0x1716 -#define P_DI_BLEND_REG3_X VCBUS_REG_ADDR(DI_BLEND_REG3_X) -#define DI_BLEND_REG3_Y 0x1717 -#define P_DI_BLEND_REG3_Y VCBUS_REG_ADDR(DI_BLEND_REG3_Y) -#define DI_CLKG_CTRL 0x1718 -#define P_DI_CLKG_CTRL VCBUS_REG_ADDR(DI_CLKG_CTRL) -#define DI_EI_CTRL3 0x1719 -#define P_DI_EI_CTRL3 VCBUS_REG_ADDR(DI_EI_CTRL3) -#define DI_EI_CTRL4 0x171a -#define P_DI_EI_CTRL4 VCBUS_REG_ADDR(DI_EI_CTRL4) -#define DI_EI_CTRL5 0x171b -#define P_DI_EI_CTRL5 VCBUS_REG_ADDR(DI_EI_CTRL5) -#define DI_EI_CTRL6 0x171c -#define P_DI_EI_CTRL6 VCBUS_REG_ADDR(DI_EI_CTRL6) -#define DI_EI_CTRL7 0x171d -#define P_DI_EI_CTRL7 VCBUS_REG_ADDR(DI_EI_CTRL7) -#define DI_EI_CTRL8 0x171e -#define P_DI_EI_CTRL8 VCBUS_REG_ADDR(DI_EI_CTRL8) -#define DI_EI_CTRL9 0x171f -#define P_DI_EI_CTRL9 VCBUS_REG_ADDR(DI_EI_CTRL9) -#define DI_EI_CTRL10 0x1793 -#define P_DI_EI_CTRL10 VCBUS_REG_ADDR(DI_EI_CTRL10) -#define DI_EI_CTRL11 0x179e -#define P_DI_EI_CTRL11 VCBUS_REG_ADDR(DI_EI_CTRL11) -#define DI_EI_CTRL12 0x179f -#define P_DI_EI_CTRL12 VCBUS_REG_ADDR(DI_EI_CTRL12) -#define DI_EI_CTRL13 0x17a8 -#define P_DI_EI_CTRL13 VCBUS_REG_ADDR(DI_EI_CTRL13) -#define DI_EI_XWIN0 0x1798 -#define P_DI_EI_XWIN0 VCBUS_REG_ADDR(DI_EI_XWIN0) -#define DI_EI_XWIN1 0x1799 -#define P_DI_EI_XWIN1 VCBUS_REG_ADDR(DI_EI_XWIN1) -#define DI_MC_REG0_X 0x1720 -#define P_DI_MC_REG0_X VCBUS_REG_ADDR(DI_MC_REG0_X) -#define DI_MC_REG0_Y 0x1721 -#define P_DI_MC_REG0_Y VCBUS_REG_ADDR(DI_MC_REG0_Y) -#define DI_MC_REG1_X 0x1722 -#define P_DI_MC_REG1_X VCBUS_REG_ADDR(DI_MC_REG1_X) -#define DI_MC_REG1_Y 0x1723 -#define P_DI_MC_REG1_Y VCBUS_REG_ADDR(DI_MC_REG1_Y) -#define DI_MC_REG2_X 0x1724 -#define P_DI_MC_REG2_X VCBUS_REG_ADDR(DI_MC_REG2_X) -#define DI_MC_REG2_Y 0x1725 -#define P_DI_MC_REG2_Y VCBUS_REG_ADDR(DI_MC_REG2_Y) -#define DI_MC_REG3_X 0x1726 -#define P_DI_MC_REG3_X VCBUS_REG_ADDR(DI_MC_REG3_X) -#define DI_MC_REG3_Y 0x1727 -#define P_DI_MC_REG3_Y VCBUS_REG_ADDR(DI_MC_REG3_Y) -#define DI_MC_REG4_X 0x1728 -#define P_DI_MC_REG4_X VCBUS_REG_ADDR(DI_MC_REG4_X) -#define DI_MC_REG4_Y 0x1729 -#define P_DI_MC_REG4_Y VCBUS_REG_ADDR(DI_MC_REG4_Y) -#define DI_MC_32LVL0 0x172a -#define P_DI_MC_32LVL0 VCBUS_REG_ADDR(DI_MC_32LVL0) -#define DI_MC_32LVL1 0x172b -#define P_DI_MC_32LVL1 VCBUS_REG_ADDR(DI_MC_32LVL1) -#define DI_MC_22LVL0 0x172c -#define P_DI_MC_22LVL0 VCBUS_REG_ADDR(DI_MC_22LVL0) -#define DI_MC_22LVL1 0x172d -#define P_DI_MC_22LVL1 VCBUS_REG_ADDR(DI_MC_22LVL1) -#define DI_MC_22LVL2 0x172e -#define P_DI_MC_22LVL2 VCBUS_REG_ADDR(DI_MC_22LVL2) -#define DI_MC_CTRL 0x172f -#define P_DI_MC_CTRL VCBUS_REG_ADDR(DI_MC_CTRL) -#define DI_INTR_CTRL 0x1730 -#define P_DI_INTR_CTRL VCBUS_REG_ADDR(DI_INTR_CTRL) -#define DI_INFO_ADDR 0x1731 -#define P_DI_INFO_ADDR VCBUS_REG_ADDR(DI_INFO_ADDR) -#define DI_INFO_DATA 0x1732 -#define P_DI_INFO_DATA VCBUS_REG_ADDR(DI_INFO_DATA) -#define DI_PRE_HOLD 0x1733 -#define P_DI_PRE_HOLD VCBUS_REG_ADDR(DI_PRE_HOLD) -#define DI_MTN_1_CTRL1 0x1740 -#define P_DI_MTN_1_CTRL1 VCBUS_REG_ADDR(DI_MTN_1_CTRL1) -#define DI_MTN_1_CTRL2 0x1741 -#define P_DI_MTN_1_CTRL2 VCBUS_REG_ADDR(DI_MTN_1_CTRL2) -#define DI_MTN_1_CTRL3 0x1742 -#define P_DI_MTN_1_CTRL3 VCBUS_REG_ADDR(DI_MTN_1_CTRL3) -#define DI_MTN_1_CTRL4 0x1743 -#define P_DI_MTN_1_CTRL4 VCBUS_REG_ADDR(DI_MTN_1_CTRL4) -#define DI_MTN_1_CTRL5 0x1744 -#define P_DI_MTN_1_CTRL5 VCBUS_REG_ADDR(DI_MTN_1_CTRL5) -#define DI_MTN_1_CTRL6 0x17a9 -#define P_DI_MTN_1_CTRL6 VCBUS_REG_ADDR(DI_MTN_1_CTRL6) -#define DI_MTN_1_CTRL7 0x17aa -#define P_DI_MTN_1_CTRL7 VCBUS_REG_ADDR(DI_MTN_1_CTRL7) -#define DI_MTN_1_CTRL8 0x17ab -#define P_DI_MTN_1_CTRL8 VCBUS_REG_ADDR(DI_MTN_1_CTRL8) -#define DI_MTN_1_CTRL9 0x17ac -#define P_DI_MTN_1_CTRL9 VCBUS_REG_ADDR(DI_MTN_1_CTRL9) -#define DI_MTN_1_CTRL10 0x17ad -#define P_DI_MTN_1_CTRL10 VCBUS_REG_ADDR(DI_MTN_1_CTRL10) -#define DI_MTN_1_CTRL11 0x17ae -#define P_DI_MTN_1_CTRL11 VCBUS_REG_ADDR(DI_MTN_1_CTRL11) -#define DI_MTN_1_CTRL12 0x17af -#define P_DI_MTN_1_CTRL12 VCBUS_REG_ADDR(DI_MTN_1_CTRL12) -#define DET3D_MOTN_CFG 0x1734 -#define P_DET3D_MOTN_CFG VCBUS_REG_ADDR(DET3D_MOTN_CFG) -#define DET3D_CB_CFG 0x1735 -#define P_DET3D_CB_CFG VCBUS_REG_ADDR(DET3D_CB_CFG) -#define DET3D_SPLT_CFG 0x1736 -#define P_DET3D_SPLT_CFG VCBUS_REG_ADDR(DET3D_SPLT_CFG) -#define DET3D_HV_MUTE 0x1737 -#define P_DET3D_HV_MUTE VCBUS_REG_ADDR(DET3D_HV_MUTE) -#define DET3D_MAT_STA_P1M1 0x1738 -#define P_DET3D_MAT_STA_P1M1 VCBUS_REG_ADDR(DET3D_MAT_STA_P1M1) -#define DET3D_MAT_STA_P1TH 0x1739 -#define P_DET3D_MAT_STA_P1TH VCBUS_REG_ADDR(DET3D_MAT_STA_P1TH) -#define DET3D_MAT_STA_M1TH 0x173a -#define P_DET3D_MAT_STA_M1TH VCBUS_REG_ADDR(DET3D_MAT_STA_M1TH) -#define DET3D_MAT_STA_RSFT 0x173b -#define P_DET3D_MAT_STA_RSFT VCBUS_REG_ADDR(DET3D_MAT_STA_RSFT) -#define DET3D_MAT_SYMTC_TH 0x173c -#define P_DET3D_MAT_SYMTC_TH VCBUS_REG_ADDR(DET3D_MAT_SYMTC_TH) -#define DET3D_RO_DET_CB_HOR 0x173d -#define P_DET3D_RO_DET_CB_HOR VCBUS_REG_ADDR(DET3D_RO_DET_CB_HOR) -#define DET3D_RO_DET_CB_VER 0x173e -#define P_DET3D_RO_DET_CB_VER VCBUS_REG_ADDR(DET3D_RO_DET_CB_VER) -#define DET3D_RO_SPLT_HT 0x173f -#define P_DET3D_RO_SPLT_HT VCBUS_REG_ADDR(DET3D_RO_SPLT_HT) -#define NR2_MET_NM_CTRL 0x1745 -#define P_NR2_MET_NM_CTRL VCBUS_REG_ADDR(NR2_MET_NM_CTRL) -#define NR2_MET_NM_YCTRL 0x1746 -#define P_NR2_MET_NM_YCTRL VCBUS_REG_ADDR(NR2_MET_NM_YCTRL) -#define NR2_MET_NM_CCTRL 0x1747 -#define P_NR2_MET_NM_CCTRL VCBUS_REG_ADDR(NR2_MET_NM_CCTRL) - -#define NR2_MATNR_SNR_EDGE2B 0x1757 -#define P_NR2_MATNR_SNR_EDGE2B VCBUS_REG_ADDR(NR2_MATNR_SNR_EDGE2B) -#define NR2_MATNR_BETA_EGAIN 0x1758 -#define P_NR2_MATNR_BETA_EGAIN VCBUS_REG_ADDR(NR2_MATNR_BETA_EGAIN) -#define NR2_MATNR_BETA_BRT 0x1759 -#define P_NR2_MATNR_BETA_BRT VCBUS_REG_ADDR(NR2_MATNR_BETA_BRT) -#define NR2_MATNR_XBETA_CFG 0x175a -#define P_NR2_MATNR_XBETA_CFG VCBUS_REG_ADDR(NR2_MATNR_XBETA_CFG) -#define NR2_MATNR_YBETA_SCL 0x175b -#define P_NR2_MATNR_YBETA_SCL VCBUS_REG_ADDR(NR2_MATNR_YBETA_SCL) -#define NR2_MATNR_CBETA_SCL 0x175c -#define P_NR2_MATNR_CBETA_SCL VCBUS_REG_ADDR(NR2_MATNR_CBETA_SCL) -#define NR2_SNR_MASK 0x175d -#define P_NR2_SNR_MASK VCBUS_REG_ADDR(NR2_SNR_MASK) -#define NR2_SAD2NORM_LUT0 0x175e -#define P_NR2_SAD2NORM_LUT0 VCBUS_REG_ADDR(NR2_SAD2NORM_LUT0) -#define NR2_SAD2NORM_LUT1 0x175f -#define P_NR2_SAD2NORM_LUT1 VCBUS_REG_ADDR(NR2_SAD2NORM_LUT1) -#define NR2_SAD2NORM_LUT2 0x1760 -#define P_NR2_SAD2NORM_LUT2 VCBUS_REG_ADDR(NR2_SAD2NORM_LUT2) -#define NR2_SAD2NORM_LUT3 0x1761 -#define P_NR2_SAD2NORM_LUT3 VCBUS_REG_ADDR(NR2_SAD2NORM_LUT3) -#define NR2_EDGE2BETA_LUT0 0x1762 -#define P_NR2_EDGE2BETA_LUT0 VCBUS_REG_ADDR(NR2_EDGE2BETA_LUT0) -#define NR2_EDGE2BETA_LUT1 0x1763 -#define P_NR2_EDGE2BETA_LUT1 VCBUS_REG_ADDR(NR2_EDGE2BETA_LUT1) -#define NR2_EDGE2BETA_LUT2 0x1764 -#define P_NR2_EDGE2BETA_LUT2 VCBUS_REG_ADDR(NR2_EDGE2BETA_LUT2) -#define NR2_EDGE2BETA_LUT3 0x1765 -#define P_NR2_EDGE2BETA_LUT3 VCBUS_REG_ADDR(NR2_EDGE2BETA_LUT3) -#define NR2_MOTION2BETA_LUT0 0x1766 -#define P_NR2_MOTION2BETA_LUT0 VCBUS_REG_ADDR(NR2_MOTION2BETA_LUT0) -#define NR2_MOTION2BETA_LUT1 0x1767 -#define P_NR2_MOTION2BETA_LUT1 VCBUS_REG_ADDR(NR2_MOTION2BETA_LUT1) -#define NR2_MOTION2BETA_LUT2 0x1768 -#define P_NR2_MOTION2BETA_LUT2 VCBUS_REG_ADDR(NR2_MOTION2BETA_LUT2) -#define NR2_MOTION2BETA_LUT3 0x1769 -#define P_NR2_MOTION2BETA_LUT3 VCBUS_REG_ADDR(NR2_MOTION2BETA_LUT3) -#define NR2_MATNR_MTN_CRTL 0x176a -#define P_NR2_MATNR_MTN_CRTL VCBUS_REG_ADDR(NR2_MATNR_MTN_CRTL) -#define NR2_MATNR_MTN_CRTL2 0x176b -#define P_NR2_MATNR_MTN_CRTL2 VCBUS_REG_ADDR(NR2_MATNR_MTN_CRTL2) -#define NR2_MATNR_MTN_COR 0x176c -#define P_NR2_MATNR_MTN_COR VCBUS_REG_ADDR(NR2_MATNR_MTN_COR) -#define NR2_MATNR_MTN_GAIN 0x176d -#define P_NR2_MATNR_MTN_GAIN VCBUS_REG_ADDR(NR2_MATNR_MTN_GAIN) -#define NR2_MATNR_DEGHOST 0x176e -#define P_NR2_MATNR_DEGHOST VCBUS_REG_ADDR(NR2_MATNR_DEGHOST) -#define NR2_MATNR_MTNB_BRT 0x1777 -#define P_NR2_MATNR_MTNB_BRT VCBUS_REG_ADDR(NR2_MATNR_MTNB_BRT) -#define NR2_CUE_MODE 0x1778 -#define P_NR2_CUE_MODE VCBUS_REG_ADDR(NR2_CUE_MODE) -#define NR2_CUE_CON_MOT_TH 0x1779 -#define P_NR2_CUE_CON_MOT_TH VCBUS_REG_ADDR(NR2_CUE_CON_MOT_TH) -#define NR2_CUE_CON_DIF0 0x177a -#define P_NR2_CUE_CON_DIF0 VCBUS_REG_ADDR(NR2_CUE_CON_DIF0) -#define NR2_CUE_CON_DIF1 0x177b -#define P_NR2_CUE_CON_DIF1 VCBUS_REG_ADDR(NR2_CUE_CON_DIF1) -#define NR2_CUE_CON_DIF2 0x177c -#define P_NR2_CUE_CON_DIF2 VCBUS_REG_ADDR(NR2_CUE_CON_DIF2) -#define NR2_CUE_CON_DIF3 0x177d -#define P_NR2_CUE_CON_DIF3 VCBUS_REG_ADDR(NR2_CUE_CON_DIF3) -#define NR2_CUE_PRG_DIF 0x177e -#define P_NR2_CUE_PRG_DIF VCBUS_REG_ADDR(NR2_CUE_PRG_DIF) -#define NR2_CONV_MODE 0x177f -#define P_NR2_CONV_MODE VCBUS_REG_ADDR(NR2_CONV_MODE) -#define DET3D_RO_SPLT_HB 0x1780 -#define P_DET3D_RO_SPLT_HB VCBUS_REG_ADDR(DET3D_RO_SPLT_HB) -#define DET3D_RO_SPLT_VL 0x1781 -#define P_DET3D_RO_SPLT_VL VCBUS_REG_ADDR(DET3D_RO_SPLT_VL) -#define DET3D_RO_SPLT_VR 0x1782 -#define P_DET3D_RO_SPLT_VR VCBUS_REG_ADDR(DET3D_RO_SPLT_VR) -#define DET3D_RO_MAT_LUMA_LR 0x1783 -#define P_DET3D_RO_MAT_LUMA_LR VCBUS_REG_ADDR(DET3D_RO_MAT_LUMA_LR) -#define DET3D_RO_MAT_LUMA_TB 0x1784 -#define P_DET3D_RO_MAT_LUMA_TB VCBUS_REG_ADDR(DET3D_RO_MAT_LUMA_TB) -#define DET3D_RO_MAT_CHRU_LR 0x1785 -#define P_DET3D_RO_MAT_CHRU_LR VCBUS_REG_ADDR(DET3D_RO_MAT_CHRU_LR) -#define DET3D_RO_MAT_CHRU_TB 0x1786 -#define P_DET3D_RO_MAT_CHRU_TB VCBUS_REG_ADDR(DET3D_RO_MAT_CHRU_TB) -#define DET3D_RO_MAT_CHRV_LR 0x1787 -#define P_DET3D_RO_MAT_CHRV_LR VCBUS_REG_ADDR(DET3D_RO_MAT_CHRV_LR) -#define NR2_CFR_PARA_CFG0 0x179c -#define P_NR2_CFR_PARA_CFG0 VCBUS_REG_ADDR(NR2_CFR_PARA_CFG0) -#define NR2_CFR_PARA_CFG1 0x179d -#define P_NR2_CFR_PARA_CFG1 VCBUS_REG_ADDR(NR2_CFR_PARA_CFG1) -#define DI_NR_1_CTRL0 0x1794 -#define P_DI_NR_1_CTRL0 VCBUS_REG_ADDR(DI_NR_1_CTRL0) -#define DI_NR_1_CTRL1 0x1795 -#define P_DI_NR_1_CTRL1 VCBUS_REG_ADDR(DI_NR_1_CTRL1) -#define DI_NR_1_CTRL2 0x1796 -#define P_DI_NR_1_CTRL2 VCBUS_REG_ADDR(DI_NR_1_CTRL2) -#define DI_NR_1_CTRL3 0x1797 -#define P_DI_NR_1_CTRL3 VCBUS_REG_ADDR(DI_NR_1_CTRL3) -#define DI_CONTWR_X 0x17a0 -#define P_DI_CONTWR_X VCBUS_REG_ADDR(DI_CONTWR_X) -#define DI_CONTWR_Y 0x17a1 -#define P_DI_CONTWR_Y VCBUS_REG_ADDR(DI_CONTWR_Y) -#define DI_CONTWR_CTRL 0x17a2 -#define P_DI_CONTWR_CTRL VCBUS_REG_ADDR(DI_CONTWR_CTRL) -#define DI_CONTPRD_X 0x17a3 -#define P_DI_CONTPRD_X VCBUS_REG_ADDR(DI_CONTPRD_X) -#define DI_CONTPRD_Y 0x17a4 -#define P_DI_CONTPRD_Y VCBUS_REG_ADDR(DI_CONTPRD_Y) -#define DI_CONTP2RD_X 0x17a5 -#define P_DI_CONTP2RD_X VCBUS_REG_ADDR(DI_CONTP2RD_X) -#define DI_CONTP2RD_Y 0x17a6 -#define P_DI_CONTP2RD_Y VCBUS_REG_ADDR(DI_CONTP2RD_Y) -#define DI_CONTRD_CTRL 0x17a7 -#define P_DI_CONTRD_CTRL VCBUS_REG_ADDR(DI_CONTRD_CTRL) -#define DI_NRWR_X 0x17c0 -#define P_DI_NRWR_X VCBUS_REG_ADDR(DI_NRWR_X) -#define DI_NRWR_Y 0x17c1 -#define P_DI_NRWR_Y VCBUS_REG_ADDR(DI_NRWR_Y) -#define DI_NRWR_CTRL 0x17c2 -#define P_DI_NRWR_CTRL VCBUS_REG_ADDR(DI_NRWR_CTRL) -#define DI_MTNWR_X 0x17c3 -#define P_DI_MTNWR_X VCBUS_REG_ADDR(DI_MTNWR_X) -#define DI_MTNWR_Y 0x17c4 -#define P_DI_MTNWR_Y VCBUS_REG_ADDR(DI_MTNWR_Y) -#define DI_MTNWR_CTRL 0x17c5 -#define P_DI_MTNWR_CTRL VCBUS_REG_ADDR(DI_MTNWR_CTRL) -#define DI_DIWR_X 0x17c6 -#define P_DI_DIWR_X VCBUS_REG_ADDR(DI_DIWR_X) -#define DI_DIWR_Y 0x17c7 -#define P_DI_DIWR_Y VCBUS_REG_ADDR(DI_DIWR_Y) -#define DI_DIWR_CTRL 0x17c8 -#define P_DI_DIWR_CTRL VCBUS_REG_ADDR(DI_DIWR_CTRL) -#define DI_MTNCRD_X 0x17c9 -#define P_DI_MTNCRD_X VCBUS_REG_ADDR(DI_MTNCRD_X) -#define DI_MTNCRD_Y 0x17ca -#define P_DI_MTNCRD_Y VCBUS_REG_ADDR(DI_MTNCRD_Y) -#define DI_MTNPRD_X 0x17cb -#define P_DI_MTNPRD_X VCBUS_REG_ADDR(DI_MTNPRD_X) -#define DI_MTNPRD_Y 0x17cc -#define P_DI_MTNPRD_Y VCBUS_REG_ADDR(DI_MTNPRD_Y) -#define DI_MTNRD_CTRL 0x17cd -#define P_DI_MTNRD_CTRL VCBUS_REG_ADDR(DI_MTNRD_CTRL) -#define DI_INP_GEN_REG 0x17ce -#define P_DI_INP_GEN_REG VCBUS_REG_ADDR(DI_INP_GEN_REG) -#define DI_INP_CANVAS0 0x17cf -#define P_DI_INP_CANVAS0 VCBUS_REG_ADDR(DI_INP_CANVAS0) -#define DI_INP_LUMA_X0 0x17d0 -#define P_DI_INP_LUMA_X0 VCBUS_REG_ADDR(DI_INP_LUMA_X0) -#define DI_INP_LUMA_Y0 0x17d1 -#define P_DI_INP_LUMA_Y0 VCBUS_REG_ADDR(DI_INP_LUMA_Y0) -#define DI_INP_CHROMA_X0 0x17d2 -#define P_DI_INP_CHROMA_X0 VCBUS_REG_ADDR(DI_INP_CHROMA_X0) -#define DI_INP_CHROMA_Y0 0x17d3 -#define P_DI_INP_CHROMA_Y0 VCBUS_REG_ADDR(DI_INP_CHROMA_Y0) -#define DI_INP_RPT_LOOP 0x17d4 -#define P_DI_INP_RPT_LOOP VCBUS_REG_ADDR(DI_INP_RPT_LOOP) -#define DI_INP_LUMA0_RPT_PAT 0x17d5 -#define P_DI_INP_LUMA0_RPT_PAT VCBUS_REG_ADDR(DI_INP_LUMA0_RPT_PAT) -#define DI_INP_CHROMA0_RPT_PAT 0x17d6 - -#define DI_INP_RANGE_MAP_Y 0x17ba -#define P_DI_INP_RANGE_MAP_Y VCBUS_REG_ADDR(DI_INP_RANGE_MAP_Y) -#define DI_INP_RANGE_MAP_CB 0x17bb -#define P_DI_INP_RANGE_MAP_CB VCBUS_REG_ADDR(DI_INP_RANGE_MAP_CB) -#define DI_INP_RANGE_MAP_CR 0x17bc -#define P_DI_INP_RANGE_MAP_CR VCBUS_REG_ADDR(DI_INP_RANGE_MAP_CR) -#define DI_INP_GEN_REG2 0x1791 -#define P_DI_INP_GEN_REG2 VCBUS_REG_ADDR(DI_INP_GEN_REG2) -#define DI_INP_FMT_CTRL 0x17d9 -#define P_DI_INP_FMT_CTRL VCBUS_REG_ADDR(DI_INP_FMT_CTRL) -#define DI_INP_FMT_W 0x17da -#define P_DI_INP_FMT_W VCBUS_REG_ADDR(DI_INP_FMT_W) -#define DI_MEM_GEN_REG 0x17db -#define P_DI_MEM_GEN_REG VCBUS_REG_ADDR(DI_MEM_GEN_REG) -#define DI_MEM_CANVAS0 0x17dc -#define P_DI_MEM_CANVAS0 VCBUS_REG_ADDR(DI_MEM_CANVAS0) -#define DI_MEM_LUMA_X0 0x17dd -#define P_DI_MEM_LUMA_X0 VCBUS_REG_ADDR(DI_MEM_LUMA_X0) -#define DI_MEM_LUMA_Y0 0x17de -#define P_DI_MEM_LUMA_Y0 VCBUS_REG_ADDR(DI_MEM_LUMA_Y0) -#define DI_MEM_CHROMA_X0 0x17df -#define P_DI_MEM_CHROMA_X0 VCBUS_REG_ADDR(DI_MEM_CHROMA_X0) -#define DI_MEM_CHROMA_Y0 0x17e0 -#define P_DI_MEM_CHROMA_Y0 VCBUS_REG_ADDR(DI_MEM_CHROMA_Y0) -#define DI_MEM_RPT_LOOP 0x17e1 -#define P_DI_MEM_RPT_LOOP VCBUS_REG_ADDR(DI_MEM_RPT_LOOP) - -#define DI_MEM_RANGE_MAP_Y 0x17bd -#define P_DI_MEM_RANGE_MAP_Y VCBUS_REG_ADDR(DI_MEM_RANGE_MAP_Y) -#define DI_MEM_RANGE_MAP_CB 0x17be -#define P_DI_MEM_RANGE_MAP_CB VCBUS_REG_ADDR(DI_MEM_RANGE_MAP_CB) -#define DI_MEM_RANGE_MAP_CR 0x17bf -#define P_DI_MEM_RANGE_MAP_CR VCBUS_REG_ADDR(DI_MEM_RANGE_MAP_CR) -#define DI_MEM_GEN_REG2 0x1792 -#define P_DI_MEM_GEN_REG2 VCBUS_REG_ADDR(DI_MEM_GEN_REG2) -#define DI_MEM_FMT_CTRL 0x17e6 -#define P_DI_MEM_FMT_CTRL VCBUS_REG_ADDR(DI_MEM_FMT_CTRL) -#define DI_MEM_FMT_W 0x17e7 -#define P_DI_MEM_FMT_W VCBUS_REG_ADDR(DI_MEM_FMT_W) -#define DI_IF1_GEN_REG 0x17e8 -#define P_DI_IF1_GEN_REG VCBUS_REG_ADDR(DI_IF1_GEN_REG) -#define DI_IF1_CANVAS0 0x17e9 -#define P_DI_IF1_CANVAS0 VCBUS_REG_ADDR(DI_IF1_CANVAS0) -#define DI_IF1_LUMA_X0 0x17ea -#define P_DI_IF1_LUMA_X0 VCBUS_REG_ADDR(DI_IF1_LUMA_X0) -#define DI_IF1_LUMA_Y0 0x17eb -#define P_DI_IF1_LUMA_Y0 VCBUS_REG_ADDR(DI_IF1_LUMA_Y0) -#define DI_IF1_CHROMA_X0 0x17ec -#define P_DI_IF1_CHROMA_X0 VCBUS_REG_ADDR(DI_IF1_CHROMA_X0) -#define DI_IF1_CHROMA_Y0 0x17ed -#define P_DI_IF1_CHROMA_Y0 VCBUS_REG_ADDR(DI_IF1_CHROMA_Y0) -#define DI_IF1_RPT_LOOP 0x17ee -#define P_DI_IF1_RPT_LOOP VCBUS_REG_ADDR(DI_IF1_RPT_LOOP) -#define DI_IF1_LUMA0_RPT_PAT 0x17ef -#define P_DI_IF1_LUMA0_RPT_PAT VCBUS_REG_ADDR(DI_IF1_LUMA0_RPT_PAT) -#define DI_IF1_CHROMA0_RPT_PAT 0x17f0 -#define P_DI_IF1_DUMMY_PIXEL VCBUS_REG_ADDR(DI_IF1_DUMMY_PIXEL) -#define DI_IF1_LUMA_FIFO_SIZE 0x17f2 - -#define DI_CHAN2_GEN_REG2 0x17b7 -#define P_DI_CHAN2_GEN_REG2 VCBUS_REG_ADDR(DI_CHAN2_GEN_REG2) -#define DI_CHAN2_FMT_CTRL 0x17b8 -#define P_DI_CHAN2_FMT_CTRL VCBUS_REG_ADDR(DI_CHAN2_FMT_CTRL) -#define DI_CHAN2_FMT_W 0x17b9 -#define P_DI_CHAN2_FMT_W VCBUS_REG_ADDR(DI_CHAN2_FMT_W) -#define VIU2_ADDR_START 0x1e00 -#define P_VIU2_ADDR_START VCBUS_REG_ADDR(VIU2_ADDR_START) -#define VIU2_ADDR_END 0x1eff -#define P_VIU2_ADDR_END VCBUS_REG_ADDR(VIU2_ADDR_END) -#define VIU2_SW_RESET 0x1e01 -#define P_VIU2_SW_RESET VCBUS_REG_ADDR(VIU2_SW_RESET) -#define VIU2_OSD1_CTRL_STAT 0x1e10 -#define P_VIU2_OSD1_CTRL_STAT VCBUS_REG_ADDR(VIU2_OSD1_CTRL_STAT) -#define VIU2_OSD1_CTRL_STAT2 0x1e2d -#define P_VIU2_OSD1_CTRL_STAT2 VCBUS_REG_ADDR(VIU2_OSD1_CTRL_STAT2) -#define VIU2_OSD1_COLOR_ADDR 0x1e11 -#define P_VIU2_OSD1_COLOR_ADDR VCBUS_REG_ADDR(VIU2_OSD1_COLOR_ADDR) -#define VIU2_OSD1_COLOR 0x1e12 -#define P_VIU2_OSD1_COLOR VCBUS_REG_ADDR(VIU2_OSD1_COLOR) -#define VIU2_OSD1_TCOLOR_AG0 0x1e17 -#define P_VIU2_OSD1_TCOLOR_AG0 VCBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG0) -#define VIU2_OSD1_TCOLOR_AG1 0x1e18 -#define P_VIU2_OSD1_TCOLOR_AG1 VCBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG1) -#define VIU2_OSD1_TCOLOR_AG2 0x1e19 -#define P_VIU2_OSD1_TCOLOR_AG2 VCBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG2) -#define VIU2_OSD1_TCOLOR_AG3 0x1e1a -#define P_VIU2_OSD1_TCOLOR_AG3 VCBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG3) - - -#define VENC_SYNC_ROUTE 0x1b60 -#define P_VENC_SYNC_ROUTE VCBUS_REG_ADDR(VENC_SYNC_ROUTE) -#define VENC_VIDEO_EXSRC 0x1b61 -#define P_VENC_VIDEO_EXSRC VCBUS_REG_ADDR(VENC_VIDEO_EXSRC) -#define VENC_DVI_SETTING 0x1b62 -#define P_VENC_DVI_SETTING VCBUS_REG_ADDR(VENC_DVI_SETTING) -#define VENC_C656_CTRL 0x1b63 -#define P_VENC_C656_CTRL VCBUS_REG_ADDR(VENC_C656_CTRL) -#define VENC_UPSAMPLE_CTRL0 0x1b64 -#define P_VENC_UPSAMPLE_CTRL0 VCBUS_REG_ADDR(VENC_UPSAMPLE_CTRL0) -#define VENC_UPSAMPLE_CTRL1 0x1b65 -#define P_VENC_UPSAMPLE_CTRL1 VCBUS_REG_ADDR(VENC_UPSAMPLE_CTRL1) -#define VENC_UPSAMPLE_CTRL2 0x1b66 -#define P_VENC_UPSAMPLE_CTRL2 VCBUS_REG_ADDR(VENC_UPSAMPLE_CTRL2) -#define TCON_INVERT_CTL 0x1b67 -#define P_TCON_INVERT_CTL VCBUS_REG_ADDR(TCON_INVERT_CTL) -#define VENC_VIDEO_PROG_MODE 0x1b68 -#define P_VENC_VIDEO_PROG_MODE VCBUS_REG_ADDR(VENC_VIDEO_PROG_MODE) -#define VENC_ENCI_LINE 0x1b69 -#define P_VENC_ENCI_LINE VCBUS_REG_ADDR(VENC_ENCI_LINE) -#define VENC_ENCI_PIXEL 0x1b6a -#define P_VENC_ENCI_PIXEL VCBUS_REG_ADDR(VENC_ENCI_PIXEL) -#define VENC_ENCP_LINE 0x1b6b -#define P_VENC_ENCP_LINE VCBUS_REG_ADDR(VENC_ENCP_LINE) -#define VENC_ENCP_PIXEL 0x1b6c -#define P_VENC_ENCP_PIXEL VCBUS_REG_ADDR(VENC_ENCP_PIXEL) -#define VENC_STATA 0x1b6d -#define P_VENC_STATA VCBUS_REG_ADDR(VENC_STATA) -#define VENC_INTCTRL 0x1b6e -#define P_VENC_INTCTRL VCBUS_REG_ADDR(VENC_INTCTRL) -#define VENC_INTFLAG 0x1b6f -#define P_VENC_INTFLAG VCBUS_REG_ADDR(VENC_INTFLAG) -#define VENC_VIDEO_TST_EN 0x1b70 -#define P_VENC_VIDEO_TST_EN VCBUS_REG_ADDR(VENC_VIDEO_TST_EN) -#define VENC_VIDEO_TST_MDSEL 0x1b71 -#define P_VENC_VIDEO_TST_MDSEL VCBUS_REG_ADDR(VENC_VIDEO_TST_MDSEL) -#define VENC_VIDEO_TST_Y 0x1b72 -#define P_VENC_VIDEO_TST_Y VCBUS_REG_ADDR(VENC_VIDEO_TST_Y) -#define VENC_VIDEO_TST_CB 0x1b73 -#define P_VENC_VIDEO_TST_CB VCBUS_REG_ADDR(VENC_VIDEO_TST_CB) -#define VENC_VIDEO_TST_CR 0x1b74 -#define P_VENC_VIDEO_TST_CR VCBUS_REG_ADDR(VENC_VIDEO_TST_CR) -#define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75 -#define VENC_VDAC_FIFO_CTRL 0x1bfc -#define P_VENC_VDAC_FIFO_CTRL VCBUS_REG_ADDR(VENC_VDAC_FIFO_CTRL) -#define ENCL_TCON_INVERT_CTL 0x1bfd -#define P_ENCL_TCON_INVERT_CTL VCBUS_REG_ADDR(ENCL_TCON_INVERT_CTL) -#define ENCP_VIDEO_EN 0x1b80 -#define P_ENCP_VIDEO_EN VCBUS_REG_ADDR(ENCP_VIDEO_EN) -#define ENCP_VIDEO_SYNC_MODE 0x1b81 -#define P_ENCP_VIDEO_SYNC_MODE VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_MODE) -#define ENCP_MACV_EN 0x1b82 -#define P_ENCP_MACV_EN VCBUS_REG_ADDR(ENCP_MACV_EN) -#define ENCP_VIDEO_Y_SCL 0x1b83 -#define P_ENCP_VIDEO_Y_SCL VCBUS_REG_ADDR(ENCP_VIDEO_Y_SCL) -#define ENCP_VIDEO_PB_SCL 0x1b84 -#define P_ENCP_VIDEO_PB_SCL VCBUS_REG_ADDR(ENCP_VIDEO_PB_SCL) -#define ENCP_VIDEO_PR_SCL 0x1b85 -#define P_ENCP_VIDEO_PR_SCL VCBUS_REG_ADDR(ENCP_VIDEO_PR_SCL) -#define ENCP_VIDEO_SYNC_SCL 0x1b86 -#define P_ENCP_VIDEO_SYNC_SCL VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_SCL) -#define ENCP_VIDEO_MACV_SCL 0x1b87 -#define P_ENCP_VIDEO_MACV_SCL VCBUS_REG_ADDR(ENCP_VIDEO_MACV_SCL) -#define ENCP_VIDEO_Y_OFFST 0x1b88 -#define P_ENCP_VIDEO_Y_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_Y_OFFST) -#define ENCP_VIDEO_PB_OFFST 0x1b89 -#define P_ENCP_VIDEO_PB_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_PB_OFFST) -#define ENCP_VIDEO_PR_OFFST 0x1b8a -#define P_ENCP_VIDEO_PR_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_PR_OFFST) -#define ENCP_VIDEO_MACV_OFFST 0x1b8c -#define ENCP_VIDEO_MODE 0x1b8d -#define P_ENCP_VIDEO_MODE VCBUS_REG_ADDR(ENCP_VIDEO_MODE) -#define ENCP_VIDEO_MODE_ADV 0x1b8e -#define P_ENCP_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCP_VIDEO_MODE_ADV) -#define ENCP_DBG_PX_RST 0x1b90 -#define P_ENCP_DBG_PX_RST VCBUS_REG_ADDR(ENCP_DBG_PX_RST) -#define ENCP_DBG_LN_RST 0x1b91 -#define P_ENCP_DBG_LN_RST VCBUS_REG_ADDR(ENCP_DBG_LN_RST) -#define ENCP_DBG_PX_INT 0x1b92 -#define P_ENCP_DBG_PX_INT VCBUS_REG_ADDR(ENCP_DBG_PX_INT) -#define ENCP_DBG_LN_INT 0x1b93 -#define P_ENCP_DBG_LN_INT VCBUS_REG_ADDR(ENCP_DBG_LN_INT) -#define ENCP_VIDEO_YFP1_HTIME 0x1b94 -#define ENCP_VIDEO_YFP2_HTIME 0x1b95 -#define ENCP_VIDEO_YC_DLY 0x1b96 -#define P_ENCP_VIDEO_YC_DLY VCBUS_REG_ADDR(ENCP_VIDEO_YC_DLY) -#define ENCP_VIDEO_MAX_PXCNT 0x1b97 -#define P_ENCP_VIDEO_MAX_PXCNT VCBUS_REG_ADDR(ENCP_VIDEO_MAX_PXCNT) -#define ENCP_VIDEO_HSO_END 0x1ba8 -#define P_ENCP_VIDEO_HSO_END VCBUS_REG_ADDR(ENCP_VIDEO_HSO_END) -#define ENCP_VIDEO_VSO_BEGIN 0x1ba9 -#define P_ENCP_VIDEO_VSO_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BEGIN) -#define ENCP_VIDEO_VSO_END 0x1baa -#define P_ENCP_VIDEO_VSO_END VCBUS_REG_ADDR(ENCP_VIDEO_VSO_END) -#define ENCP_VIDEO_VSO_BLINE 0x1bab -#define P_ENCP_VIDEO_VSO_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BLINE) -#define ENCP_VIDEO_VSO_ELINE 0x1bac -#define P_ENCP_VIDEO_VSO_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VSO_ELINE) -#define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad -#define ENCP_VIDEO_MAX_LNCNT 0x1bae -#define P_ENCP_VIDEO_MAX_LNCNT VCBUS_REG_ADDR(ENCP_VIDEO_MAX_LNCNT) -#define ENCP_VIDEO_SY_VAL 0x1bb0 -#define P_ENCP_VIDEO_SY_VAL VCBUS_REG_ADDR(ENCP_VIDEO_SY_VAL) -#define ENCP_VIDEO_SY2_VAL 0x1bb1 -#define P_ENCP_VIDEO_SY2_VAL VCBUS_REG_ADDR(ENCP_VIDEO_SY2_VAL) -#define ENCP_VIDEO_BLANKY_VAL 0x1bb2 -#define ENCP_VIDEO_HOFFST 0x1bb5 -#define P_ENCP_VIDEO_HOFFST VCBUS_REG_ADDR(ENCP_VIDEO_HOFFST) -#define ENCP_VIDEO_VOFFST 0x1bb6 -#define P_ENCP_VIDEO_VOFFST VCBUS_REG_ADDR(ENCP_VIDEO_VOFFST) -#define ENCP_VIDEO_RGB_CTRL 0x1bb7 -#define P_ENCP_VIDEO_RGB_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_RGB_CTRL) -#define ENCP_VIDEO_FILT_CTRL 0x1bb8 -#define P_ENCP_VIDEO_FILT_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_FILT_CTRL) -#define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 -#define ENCP_MACV_TIME_DOWN 0x1bcb -#define P_ENCP_MACV_TIME_DOWN VCBUS_REG_ADDR(ENCP_MACV_TIME_DOWN) -#define ENCP_MACV_TIME_LO 0x1bcc -#define P_ENCP_MACV_TIME_LO VCBUS_REG_ADDR(ENCP_MACV_TIME_LO) -#define ENCP_MACV_TIME_UP 0x1bcd -#define P_ENCP_MACV_TIME_UP VCBUS_REG_ADDR(ENCP_MACV_TIME_UP) -#define ENCP_MACV_TIME_RST 0x1bce -#define P_ENCP_MACV_TIME_RST VCBUS_REG_ADDR(ENCP_MACV_TIME_RST) -#define ENCP_VBI_CTRL 0x1bd0 -#define P_ENCP_VBI_CTRL VCBUS_REG_ADDR(ENCP_VBI_CTRL) -#define ENCP_VBI_SETTING 0x1bd1 -#define P_ENCP_VBI_SETTING VCBUS_REG_ADDR(ENCP_VBI_SETTING) -#define ENCP_VBI_BEGIN 0x1bd2 -#define P_ENCP_VBI_BEGIN VCBUS_REG_ADDR(ENCP_VBI_BEGIN) -#define ENCP_VBI_WIDTH 0x1bd3 -#define P_ENCP_VBI_WIDTH VCBUS_REG_ADDR(ENCP_VBI_WIDTH) -#define ENCP_VBI_HVAL 0x1bd4 -#define P_ENCP_VBI_HVAL VCBUS_REG_ADDR(ENCP_VBI_HVAL) -#define ENCP_VBI_DATA0 0x1bd5 -#define P_ENCP_VBI_DATA0 VCBUS_REG_ADDR(ENCP_VBI_DATA0) -#define ENCP_VBI_DATA1 0x1bd6 -#define P_ENCP_VBI_DATA1 VCBUS_REG_ADDR(ENCP_VBI_DATA1) -#define C656_HS_ST 0x1be0 -#define P_C656_HS_ST VCBUS_REG_ADDR(C656_HS_ST) -#define C656_HS_ED 0x1be1 -#define P_C656_HS_ED VCBUS_REG_ADDR(C656_HS_ED) -#define C656_VS_LNST_E 0x1be2 -#define P_C656_VS_LNST_E VCBUS_REG_ADDR(C656_VS_LNST_E) -#define C656_VS_LNST_O 0x1be3 -#define P_C656_VS_LNST_O VCBUS_REG_ADDR(C656_VS_LNST_O) -#define C656_VS_LNED_E 0x1be4 -#define P_C656_VS_LNED_E VCBUS_REG_ADDR(C656_VS_LNED_E) -#define C656_VS_LNED_O 0x1be5 -#define P_C656_VS_LNED_O VCBUS_REG_ADDR(C656_VS_LNED_O) -#define C656_FS_LNST 0x1be6 -#define P_C656_FS_LNST VCBUS_REG_ADDR(C656_FS_LNST) -#define C656_FS_LNED 0x1be7 -#define P_C656_FS_LNED VCBUS_REG_ADDR(C656_FS_LNED) -#define ENCI_VIDEO_MODE 0x1b00 -#define P_ENCI_VIDEO_MODE VCBUS_REG_ADDR(ENCI_VIDEO_MODE) -#define ENCI_VIDEO_MODE_ADV 0x1b01 -#define P_ENCI_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCI_VIDEO_MODE_ADV) -#define ENCI_VIDEO_FSC_ADJ 0x1b02 -#define P_ENCI_VIDEO_FSC_ADJ VCBUS_REG_ADDR(ENCI_VIDEO_FSC_ADJ) -#define ENCI_VIDEO_BRIGHT 0x1b03 -#define P_ENCI_VIDEO_BRIGHT VCBUS_REG_ADDR(ENCI_VIDEO_BRIGHT) -#define ENCI_VIDEO_CONT 0x1b04 -#define P_ENCI_VIDEO_CONT VCBUS_REG_ADDR(ENCI_VIDEO_CONT) -#define ENCI_VIDEO_SAT 0x1b05 -#define P_ENCI_VIDEO_SAT VCBUS_REG_ADDR(ENCI_VIDEO_SAT) -#define ENCI_VIDEO_HUE 0x1b06 -#define P_ENCI_VIDEO_HUE VCBUS_REG_ADDR(ENCI_VIDEO_HUE) -#define ENCI_VIDEO_SCH 0x1b07 -#define P_ENCI_VIDEO_SCH VCBUS_REG_ADDR(ENCI_VIDEO_SCH) -#define ENCI_SYNC_MODE 0x1b08 -#define P_ENCI_SYNC_MODE VCBUS_REG_ADDR(ENCI_SYNC_MODE) -#define ENCI_SYNC_CTRL 0x1b09 -#define P_ENCI_SYNC_CTRL VCBUS_REG_ADDR(ENCI_SYNC_CTRL) -#define ENCI_SYNC_HSO_BEGIN 0x1b0a -#define P_ENCI_SYNC_HSO_BEGIN VCBUS_REG_ADDR(ENCI_SYNC_HSO_BEGIN) -#define ENCI_SYNC_HSO_END 0x1b0b -#define P_ENCI_SYNC_HSO_END VCBUS_REG_ADDR(ENCI_SYNC_HSO_END) -#define ENCI_SYNC_VSO_EVN 0x1b0c -#define P_ENCI_SYNC_VSO_EVN VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVN) -#define ENCI_SYNC_VSO_ODD 0x1b0d -#define P_ENCI_SYNC_VSO_ODD VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODD) -#define ENCI_SYNC_VSO_EVNLN 0x1b0e -#define P_ENCI_SYNC_VSO_EVNLN VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVNLN) -#define ENCI_SYNC_VSO_ODDLN 0x1b0f -#define P_ENCI_SYNC_VSO_ODDLN VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODDLN) -#define ENCI_SYNC_HOFFST 0x1b10 -#define P_ENCI_SYNC_HOFFST VCBUS_REG_ADDR(ENCI_SYNC_HOFFST) -#define ENCI_SYNC_VOFFST 0x1b11 -#define P_ENCI_SYNC_VOFFST VCBUS_REG_ADDR(ENCI_SYNC_VOFFST) -#define ENCI_SYNC_ADJ 0x1b12 -#define P_ENCI_SYNC_ADJ VCBUS_REG_ADDR(ENCI_SYNC_ADJ) -#define ENCI_RGB_SETTING 0x1b13 -#define P_ENCI_RGB_SETTING VCBUS_REG_ADDR(ENCI_RGB_SETTING) -#define ENCI_DE_H_BEGIN 0x1b16 -#define P_ENCI_DE_H_BEGIN VCBUS_REG_ADDR(ENCI_DE_H_BEGIN) -#define ENCI_DE_H_END 0x1b17 -#define P_ENCI_DE_H_END VCBUS_REG_ADDR(ENCI_DE_H_END) -#define ENCI_DE_V_BEGIN_EVEN 0x1b18 -#define P_ENCI_DE_V_BEGIN_EVEN VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_EVEN) -#define ENCI_DE_V_END_EVEN 0x1b19 -#define P_ENCI_DE_V_END_EVEN VCBUS_REG_ADDR(ENCI_DE_V_END_EVEN) -#define ENCI_DE_V_BEGIN_ODD 0x1b1a -#define P_ENCI_DE_V_BEGIN_ODD VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_ODD) -#define ENCI_DE_V_END_ODD 0x1b1b -#define P_ENCI_DE_V_END_ODD VCBUS_REG_ADDR(ENCI_DE_V_END_ODD) -#define ENCI_VBI_SETTING 0x1b20 -#define P_ENCI_VBI_SETTING VCBUS_REG_ADDR(ENCI_VBI_SETTING) -#define ENCI_VBI_CCDT_EVN 0x1b21 -#define P_ENCI_VBI_CCDT_EVN VCBUS_REG_ADDR(ENCI_VBI_CCDT_EVN) -#define ENCI_VBI_CCDT_ODD 0x1b22 -#define P_ENCI_VBI_CCDT_ODD VCBUS_REG_ADDR(ENCI_VBI_CCDT_ODD) -#define ENCI_VBI_CC525_LN 0x1b23 -#define P_ENCI_VBI_CC525_LN VCBUS_REG_ADDR(ENCI_VBI_CC525_LN) -#define ENCI_VBI_CC625_LN 0x1b24 -#define P_ENCI_VBI_CC625_LN VCBUS_REG_ADDR(ENCI_VBI_CC625_LN) -#define ENCI_VBI_WSSDT 0x1b25 -#define P_ENCI_VBI_WSSDT VCBUS_REG_ADDR(ENCI_VBI_WSSDT) -#define ENCI_VBI_WSS_LN 0x1b26 -#define P_ENCI_VBI_WSS_LN VCBUS_REG_ADDR(ENCI_VBI_WSS_LN) -#define ENCI_VBI_CGMSDT_L 0x1b27 -#define P_ENCI_VBI_CGMSDT_L VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_L) -#define ENCI_VBI_CGMSDT_H 0x1b28 -#define P_ENCI_VBI_CGMSDT_H VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_H) -#define ENCI_VBI_CGMS_LN 0x1b29 -#define P_ENCI_VBI_CGMS_LN VCBUS_REG_ADDR(ENCI_VBI_CGMS_LN) -#define ENCI_VBI_TTX_HTIME 0x1b2a -#define P_ENCI_VBI_TTX_HTIME VCBUS_REG_ADDR(ENCI_VBI_TTX_HTIME) -#define ENCI_VBI_TTX_LN 0x1b2b -#define P_ENCI_VBI_TTX_LN VCBUS_REG_ADDR(ENCI_VBI_TTX_LN) -#define ENCI_VBI_TTXDT0 0x1b2c -#define P_ENCI_VBI_TTXDT0 VCBUS_REG_ADDR(ENCI_VBI_TTXDT0) -#define ENCI_VBI_TTXDT1 0x1b2d -#define P_ENCI_VBI_TTXDT1 VCBUS_REG_ADDR(ENCI_VBI_TTXDT1) -#define ENCI_VBI_TTXDT2 0x1b2e -#define P_ENCI_VBI_TTXDT2 VCBUS_REG_ADDR(ENCI_VBI_TTXDT2) -#define ENCI_VBI_TTXDT3 0x1b2f -#define P_ENCI_VBI_TTXDT3 VCBUS_REG_ADDR(ENCI_VBI_TTXDT3) -#define ENCI_MACV_N0 0x1b30 -#define P_ENCI_MACV_N0 VCBUS_REG_ADDR(ENCI_MACV_N0) -#define ENCI_MACV_N1 0x1b31 -#define P_ENCI_MACV_N1 VCBUS_REG_ADDR(ENCI_MACV_N1) -#define ENCI_MACV_N2 0x1b32 -#define P_ENCI_MACV_N2 VCBUS_REG_ADDR(ENCI_MACV_N2) -#define ENCI_MACV_N3 0x1b33 -#define P_ENCI_MACV_N3 VCBUS_REG_ADDR(ENCI_MACV_N3) -#define ENCI_MACV_N4 0x1b34 -#define P_ENCI_MACV_N4 VCBUS_REG_ADDR(ENCI_MACV_N4) -#define ENCI_MACV_N5 0x1b35 -#define P_ENCI_MACV_N5 VCBUS_REG_ADDR(ENCI_MACV_N5) -#define ENCI_MACV_N6 0x1b36 -#define P_ENCI_MACV_N6 VCBUS_REG_ADDR(ENCI_MACV_N6) -#define ENCI_MACV_N7 0x1b37 -#define P_ENCI_MACV_N7 VCBUS_REG_ADDR(ENCI_MACV_N7) -#define ENCI_MACV_N8 0x1b38 -#define P_ENCI_MACV_N8 VCBUS_REG_ADDR(ENCI_MACV_N8) -#define ENCI_MACV_N9 0x1b39 -#define P_ENCI_MACV_N9 VCBUS_REG_ADDR(ENCI_MACV_N9) -#define ENCI_MACV_N10 0x1b3a -#define P_ENCI_MACV_N10 VCBUS_REG_ADDR(ENCI_MACV_N10) -#define ENCI_MACV_N11 0x1b3b -#define P_ENCI_MACV_N11 VCBUS_REG_ADDR(ENCI_MACV_N11) -#define ENCI_MACV_N12 0x1b3c -#define P_ENCI_MACV_N12 VCBUS_REG_ADDR(ENCI_MACV_N12) -#define ENCI_MACV_N13 0x1b3d -#define P_ENCI_MACV_N13 VCBUS_REG_ADDR(ENCI_MACV_N13) -#define ENCI_MACV_N14 0x1b3e -#define P_ENCI_MACV_N14 VCBUS_REG_ADDR(ENCI_MACV_N14) -#define ENCI_MACV_N15 0x1b3f -#define P_ENCI_MACV_N15 VCBUS_REG_ADDR(ENCI_MACV_N15) -#define ENCI_MACV_N16 0x1b40 -#define P_ENCI_MACV_N16 VCBUS_REG_ADDR(ENCI_MACV_N16) -#define ENCI_MACV_N17 0x1b41 -#define P_ENCI_MACV_N17 VCBUS_REG_ADDR(ENCI_MACV_N17) -#define ENCI_MACV_N18 0x1b42 -#define P_ENCI_MACV_N18 VCBUS_REG_ADDR(ENCI_MACV_N18) -#define ENCI_MACV_N19 0x1b43 -#define P_ENCI_MACV_N19 VCBUS_REG_ADDR(ENCI_MACV_N19) -#define ENCI_MACV_N20 0x1b44 -#define P_ENCI_MACV_N20 VCBUS_REG_ADDR(ENCI_MACV_N20) -#define ENCI_MACV_N21 0x1b45 -#define P_ENCI_MACV_N21 VCBUS_REG_ADDR(ENCI_MACV_N21) -#define ENCI_MACV_N22 0x1b46 -#define P_ENCI_MACV_N22 VCBUS_REG_ADDR(ENCI_MACV_N22) -#define ENCI_DBG_PX_RST 0x1b48 -#define P_ENCI_DBG_PX_RST VCBUS_REG_ADDR(ENCI_DBG_PX_RST) -#define ENCI_DBG_FLDLN_RST 0x1b49 -#define P_ENCI_DBG_FLDLN_RST VCBUS_REG_ADDR(ENCI_DBG_FLDLN_RST) -#define ENCI_DBG_PX_INT 0x1b4a -#define P_ENCI_DBG_PX_INT VCBUS_REG_ADDR(ENCI_DBG_PX_INT) -#define ENCI_DBG_FLDLN_INT 0x1b4b -#define P_ENCI_DBG_FLDLN_INT VCBUS_REG_ADDR(ENCI_DBG_FLDLN_INT) -#define ENCI_DBG_MAXPX 0x1b4c -#define P_ENCI_DBG_MAXPX VCBUS_REG_ADDR(ENCI_DBG_MAXPX) -#define ENCI_DBG_MAXLN 0x1b4d -#define P_ENCI_DBG_MAXLN VCBUS_REG_ADDR(ENCI_DBG_MAXLN) -#define ENCI_MACV_MAX_AMP 0x1b50 -#define P_ENCI_MACV_MAX_AMP VCBUS_REG_ADDR(ENCI_MACV_MAX_AMP) -#define ENCI_MACV_PULSE_LO 0x1b51 -#define P_ENCI_MACV_PULSE_LO VCBUS_REG_ADDR(ENCI_MACV_PULSE_LO) -#define ENCI_MACV_PULSE_HI 0x1b52 -#define P_ENCI_MACV_PULSE_HI VCBUS_REG_ADDR(ENCI_MACV_PULSE_HI) -#define ENCI_MACV_BKP_MAX 0x1b53 -#define P_ENCI_MACV_BKP_MAX VCBUS_REG_ADDR(ENCI_MACV_BKP_MAX) -#define ENCI_CFILT_CTRL 0x1b54 -#define P_ENCI_CFILT_CTRL VCBUS_REG_ADDR(ENCI_CFILT_CTRL) -#define ENCI_CFILT7 0x1b55 -#define P_ENCI_CFILT7 VCBUS_REG_ADDR(ENCI_CFILT7) -#define ENCI_YC_DELAY 0x1b56 -#define P_ENCI_YC_DELAY VCBUS_REG_ADDR(ENCI_YC_DELAY) -#define ENCI_VIDEO_EN 0x1b57 -#define P_ENCI_VIDEO_EN VCBUS_REG_ADDR(ENCI_VIDEO_EN) -#define ENCI_DVI_HSO_BEGIN 0x1c00 -#define P_ENCI_DVI_HSO_BEGIN VCBUS_REG_ADDR(ENCI_DVI_HSO_BEGIN) -#define ENCI_DVI_HSO_END 0x1c01 -#define P_ENCI_DVI_HSO_END VCBUS_REG_ADDR(ENCI_DVI_HSO_END) -#define ENCI_DVI_VSO_END_ODD 0x1c09 -#define P_ENCI_DVI_VSO_END_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_END_ODD) -#define ENCI_CFILT_CTRL2 0x1c0a -#define P_ENCI_CFILT_CTRL2 VCBUS_REG_ADDR(ENCI_CFILT_CTRL2) -#define ENCI_DACSEL_0 0x1c0b -#define P_ENCI_DACSEL_0 VCBUS_REG_ADDR(ENCI_DACSEL_0) -#define ENCI_DACSEL_1 0x1c0c -#define P_ENCI_DACSEL_1 VCBUS_REG_ADDR(ENCI_DACSEL_1) -#define ENCP_DACSEL_0 0x1c0d -#define P_ENCP_DACSEL_0 VCBUS_REG_ADDR(ENCP_DACSEL_0) -#define ENCP_DACSEL_1 0x1c0e -#define P_ENCP_DACSEL_1 VCBUS_REG_ADDR(ENCP_DACSEL_1) -#define ENCI_TST_EN 0x1c10 -#define P_ENCI_TST_EN VCBUS_REG_ADDR(ENCI_TST_EN) -#define ENCI_TST_MDSEL 0x1c11 -#define P_ENCI_TST_MDSEL VCBUS_REG_ADDR(ENCI_TST_MDSEL) -#define ENCI_TST_Y 0x1c12 -#define P_ENCI_TST_Y VCBUS_REG_ADDR(ENCI_TST_Y) -#define ENCI_TST_CB 0x1c13 -#define P_ENCI_TST_CB VCBUS_REG_ADDR(ENCI_TST_CB) -#define ENCI_TST_CR 0x1c14 -#define P_ENCI_TST_CR VCBUS_REG_ADDR(ENCI_TST_CR) -#define ENCI_TST_CLRBAR_STRT 0x1c15 -#define ENCT_VFIFO2VD_CTL2 0x1c27 -#define P_ENCT_VFIFO2VD_CTL2 VCBUS_REG_ADDR(ENCT_VFIFO2VD_CTL2) -#define ENCT_TST_EN 0x1c28 -#define P_ENCT_TST_EN VCBUS_REG_ADDR(ENCT_TST_EN) -#define ENCT_TST_MDSEL 0x1c29 -#define P_ENCT_TST_MDSEL VCBUS_REG_ADDR(ENCT_TST_MDSEL) -#define ENCT_TST_Y 0x1c2a -#define P_ENCT_TST_Y VCBUS_REG_ADDR(ENCT_TST_Y) -#define ENCT_TST_CB 0x1c2b -#define P_ENCT_TST_CB VCBUS_REG_ADDR(ENCT_TST_CB) -#define ENCT_TST_CR 0x1c2c -#define P_ENCT_TST_CR VCBUS_REG_ADDR(ENCT_TST_CR) -#define ENCT_TST_CLRBAR_STRT 0x1c2d -#define P_ENCT_TST_CLRBAR_STRT VCBUS_REG_ADDR(ENCT_TST_CLRBAR_STRT) -#define ENCT_TST_CLRBAR_WIDTH 0x1c2e -#define ENCT_TST_VDCNT_STSET 0x1c2f -#define P_ENCT_TST_VDCNT_STSET VCBUS_REG_ADDR(ENCT_TST_VDCNT_STSET) -#define ENCP_DVI_HSO_BEGIN 0x1c30 -#define P_ENCP_DVI_HSO_BEGIN VCBUS_REG_ADDR(ENCP_DVI_HSO_BEGIN) -#define ENCP_DVI_HSO_END 0x1c31 -#define P_ENCP_DVI_HSO_END VCBUS_REG_ADDR(ENCP_DVI_HSO_END) -#define ENCP_DVI_VSO_END_EVN 0x1c38 -#define P_ENCP_DVI_VSO_END_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_END_EVN) -#define ENCP_DVI_VSO_END_ODD 0x1c39 -#define P_ENCP_DVI_VSO_END_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_END_ODD) -#define ENCP_DE_H_BEGIN 0x1c3a -#define P_ENCP_DE_H_BEGIN VCBUS_REG_ADDR(ENCP_DE_H_BEGIN) -#define ENCP_DE_H_END 0x1c3b -#define P_ENCP_DE_H_END VCBUS_REG_ADDR(ENCP_DE_H_END) -#define ENCP_DE_V_BEGIN_EVEN 0x1c3c -#define P_ENCP_DE_V_BEGIN_EVEN VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_EVEN) -#define ENCP_DE_V_END_EVEN 0x1c3d -#define P_ENCP_DE_V_END_EVEN VCBUS_REG_ADDR(ENCP_DE_V_END_EVEN) -#define ENCP_DE_V_BEGIN_ODD 0x1c3e -#define P_ENCP_DE_V_BEGIN_ODD VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_ODD) -#define ENCP_DE_V_END_ODD 0x1c3f -#define P_ENCP_DE_V_END_ODD VCBUS_REG_ADDR(ENCP_DE_V_END_ODD) - -#define ENCI_SYNC_PIXEL_EN 0x1c41 -#define P_ENCI_SYNC_PIXEL_EN VCBUS_REG_ADDR(ENCI_SYNC_PIXEL_EN) -#define ENCI_SYNC_TO_LINE_EN 0x1c42 -#define P_ENCI_SYNC_TO_LINE_EN VCBUS_REG_ADDR(ENCI_SYNC_TO_LINE_EN) -#define ENCI_SYNC_TO_PIXEL 0x1c43 -#define P_ENCI_SYNC_TO_PIXEL VCBUS_REG_ADDR(ENCI_SYNC_TO_PIXEL) - -#define ENCT_VIDEO_EN 0x1c60 -#define P_ENCT_VIDEO_EN VCBUS_REG_ADDR(ENCT_VIDEO_EN) -#define ENCT_VIDEO_Y_SCL 0x1c61 -#define P_ENCT_VIDEO_Y_SCL VCBUS_REG_ADDR(ENCT_VIDEO_Y_SCL) -#define ENCT_VIDEO_PB_SCL 0x1c62 -#define P_ENCT_VIDEO_PB_SCL VCBUS_REG_ADDR(ENCT_VIDEO_PB_SCL) -#define ENCT_VIDEO_PR_SCL 0x1c63 -#define P_ENCT_VIDEO_PR_SCL VCBUS_REG_ADDR(ENCT_VIDEO_PR_SCL) -#define ENCT_VIDEO_Y_OFFST 0x1c64 -#define P_ENCT_VIDEO_Y_OFFST VCBUS_REG_ADDR(ENCT_VIDEO_Y_OFFST) -#define ENCT_VIDEO_PB_OFFST 0x1c65 -#define P_ENCT_VIDEO_PB_OFFST VCBUS_REG_ADDR(ENCT_VIDEO_PB_OFFST) -#define ENCT_VIDEO_PR_OFFST 0x1c66 -#define P_ENCT_VIDEO_PR_OFFST VCBUS_REG_ADDR(ENCT_VIDEO_PR_OFFST) -#define ENCT_VIDEO_MODE 0x1c67 -#define P_ENCT_VIDEO_MODE VCBUS_REG_ADDR(ENCT_VIDEO_MODE) -#define ENCT_VIDEO_MODE_ADV 0x1c68 -#define P_ENCT_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCT_VIDEO_MODE_ADV) -#define ENCT_DBG_PX_RST 0x1c69 -#define P_ENCT_DBG_PX_RST VCBUS_REG_ADDR(ENCT_DBG_PX_RST) -#define ENCT_DBG_LN_RST 0x1c6a -#define P_ENCT_DBG_LN_RST VCBUS_REG_ADDR(ENCT_DBG_LN_RST) -#define ENCT_DBG_PX_INT 0x1c6b -#define P_ENCT_DBG_PX_INT VCBUS_REG_ADDR(ENCT_DBG_PX_INT) -#define ENCT_DBG_LN_INT 0x1c6c -#define P_ENCT_DBG_LN_INT VCBUS_REG_ADDR(ENCT_DBG_LN_INT) -#define ENCL_TST_VDCNT_STSET 0x1c9f -#define P_ENCL_TST_VDCNT_STSET VCBUS_REG_ADDR(ENCL_TST_VDCNT_STSET) -#define ENCL_VIDEO_EN 0x1ca0 -#define P_ENCL_VIDEO_EN VCBUS_REG_ADDR(ENCL_VIDEO_EN) -#define ENCL_VIDEO_Y_SCL 0x1ca1 -#define P_ENCL_VIDEO_Y_SCL VCBUS_REG_ADDR(ENCL_VIDEO_Y_SCL) -#define ENCL_VIDEO_PB_SCL 0x1ca2 -#define P_ENCL_VIDEO_PB_SCL VCBUS_REG_ADDR(ENCL_VIDEO_PB_SCL) -#define ENCL_VIDEO_PR_SCL 0x1ca3 -#define P_ENCL_VIDEO_PR_SCL VCBUS_REG_ADDR(ENCL_VIDEO_PR_SCL) -#define ENCL_VIDEO_Y_OFFST 0x1ca4 -#define P_ENCL_VIDEO_Y_OFFST VCBUS_REG_ADDR(ENCL_VIDEO_Y_OFFST) -#define ENCL_VIDEO_PB_OFFST 0x1ca5 -#define P_ENCL_VIDEO_PB_OFFST VCBUS_REG_ADDR(ENCL_VIDEO_PB_OFFST) -#define ENCL_VIDEO_PR_OFFST 0x1ca6 -#define P_ENCL_VIDEO_PR_OFFST VCBUS_REG_ADDR(ENCL_VIDEO_PR_OFFST) -#define ENCL_VIDEO_MODE 0x1ca7 -#define P_ENCL_VIDEO_MODE VCBUS_REG_ADDR(ENCL_VIDEO_MODE) -#define ENCL_VIDEO_MODE_ADV 0x1ca8 -#define P_ENCL_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCL_VIDEO_MODE_ADV) -#define ENCL_DBG_PX_RST 0x1ca9 -#define P_ENCL_DBG_PX_RST VCBUS_REG_ADDR(ENCL_DBG_PX_RST) -#define ENCL_DBG_LN_RST 0x1caa -#define P_ENCL_DBG_LN_RST VCBUS_REG_ADDR(ENCL_DBG_LN_RST) -#define ENCL_DBG_PX_INT 0x1cab -#define P_ENCL_DBG_PX_INT VCBUS_REG_ADDR(ENCL_DBG_PX_INT) -#define ENCL_DBG_LN_INT 0x1cac -#define P_ENCL_DBG_LN_INT VCBUS_REG_ADDR(ENCL_DBG_LN_INT) -#define ENCL_VIDEO_YC_DLY 0x1caf -#define P_ENCL_VIDEO_YC_DLY VCBUS_REG_ADDR(ENCL_VIDEO_YC_DLY) -#define ENCL_VIDEO_MAX_PXCNT 0x1cb0 -#define P_ENCL_VIDEO_MAX_PXCNT VCBUS_REG_ADDR(ENCL_VIDEO_MAX_PXCNT) -#define ENCL_VIDEO_HAVON_END 0x1cb1 -#define P_ENCL_VIDEO_HAVON_END VCBUS_REG_ADDR(ENCL_VIDEO_HAVON_END) -#define ENCL_VIDEO_HSO_BEGIN 0x1cb5 -#define P_ENCL_VIDEO_HSO_BEGIN VCBUS_REG_ADDR(ENCL_VIDEO_HSO_BEGIN) -#define ENCL_VIDEO_HSO_END 0x1cb6 -#define P_ENCL_VIDEO_HSO_END VCBUS_REG_ADDR(ENCL_VIDEO_HSO_END) -#define ENCL_VIDEO_VSO_BEGIN 0x1cb7 -#define P_ENCL_VIDEO_VSO_BEGIN VCBUS_REG_ADDR(ENCL_VIDEO_VSO_BEGIN) -#define ENCL_VIDEO_VSO_END 0x1cb8 -#define P_ENCL_VIDEO_VSO_END VCBUS_REG_ADDR(ENCL_VIDEO_VSO_END) -#define ENCL_VIDEO_VSO_BLINE 0x1cb9 -#define P_ENCL_VIDEO_VSO_BLINE VCBUS_REG_ADDR(ENCL_VIDEO_VSO_BLINE) -#define ENCL_VIDEO_VSO_ELINE 0x1cba -#define P_ENCL_VIDEO_VSO_ELINE VCBUS_REG_ADDR(ENCL_VIDEO_VSO_ELINE) -#define ENCL_VIDEO_MAX_LNCNT 0x1cbb -#define P_ENCL_VIDEO_MAX_LNCNT VCBUS_REG_ADDR(ENCL_VIDEO_MAX_LNCNT) -#define ENCL_VIDEO_BLANKY_VAL 0x1cbc -#define RDMA_AHB_END_ADDR_3 0x1cf7 -#define P_RDMA_AHB_END_ADDR_3 VCBUS_REG_ADDR(RDMA_AHB_END_ADDR_3) -#define RDMA_ACCESS_AUTO 0x1cf8 -#define P_RDMA_ACCESS_AUTO VCBUS_REG_ADDR(RDMA_ACCESS_AUTO) -#define RDMA_ACCESS_MAN 0x1cf9 -#define P_RDMA_ACCESS_MAN VCBUS_REG_ADDR(RDMA_ACCESS_MAN) -#define RDMA_CTRL 0x1cfa -#define P_RDMA_CTRL VCBUS_REG_ADDR(RDMA_CTRL) -#define RDMA_STATUS 0x1cfb -#define P_RDMA_STATUS VCBUS_REG_ADDR(RDMA_STATUS) -#define L_GAMMA_CNTL_PORT 0x1400 -#define P_L_GAMMA_CNTL_PORT VCBUS_REG_ADDR(L_GAMMA_CNTL_PORT) -#define L_GAMMA_DATA_PORT 0x1401 -#define P_L_GAMMA_DATA_PORT VCBUS_REG_ADDR(L_GAMMA_DATA_PORT) -#define L_GAMMA_ADDR_PORT 0x1402 -#define P_L_GAMMA_ADDR_PORT VCBUS_REG_ADDR(L_GAMMA_ADDR_PORT) -#define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403 -#define L_GAMMA_PROBE_POS_X 0x140d -#define P_L_GAMMA_PROBE_POS_X VCBUS_REG_ADDR(L_GAMMA_PROBE_POS_X) -#define L_GAMMA_PROBE_POS_Y 0x140e -#define P_L_GAMMA_PROBE_POS_Y VCBUS_REG_ADDR(L_GAMMA_PROBE_POS_Y) -#define L_STH1_HS_ADDR 0x1410 -#define P_L_STH1_HS_ADDR VCBUS_REG_ADDR(L_STH1_HS_ADDR) -#define L_STH1_HE_ADDR 0x1411 -#define P_L_STH1_HE_ADDR VCBUS_REG_ADDR(L_STH1_HE_ADDR) -#define L_STH1_VS_ADDR 0x1412 -#define P_L_STH1_VS_ADDR VCBUS_REG_ADDR(L_STH1_VS_ADDR) -#define L_STH1_VE_ADDR 0x1413 -#define P_L_STH1_VE_ADDR VCBUS_REG_ADDR(L_STH1_VE_ADDR) -#define L_STH2_HS_ADDR 0x1414 -#define P_L_STH2_HS_ADDR VCBUS_REG_ADDR(L_STH2_HS_ADDR) -#define L_STH2_HE_ADDR 0x1415 -#define P_L_STH2_HE_ADDR VCBUS_REG_ADDR(L_STH2_HE_ADDR) -#define L_STH2_VS_ADDR 0x1416 -#define P_L_STH2_VS_ADDR VCBUS_REG_ADDR(L_STH2_VS_ADDR) -#define L_STH2_VE_ADDR 0x1417 -#define P_L_STH2_VE_ADDR VCBUS_REG_ADDR(L_STH2_VE_ADDR) -#define L_OEH_HS_ADDR 0x1418 -#define P_L_OEH_HS_ADDR VCBUS_REG_ADDR(L_OEH_HS_ADDR) -#define L_OEH_HE_ADDR 0x1419 -#define P_L_OEH_HE_ADDR VCBUS_REG_ADDR(L_OEH_HE_ADDR) -#define L_OEH_VS_ADDR 0x141a -#define P_L_OEH_VS_ADDR VCBUS_REG_ADDR(L_OEH_VS_ADDR) -#define L_OEH_VE_ADDR 0x141b -#define P_L_OEH_VE_ADDR VCBUS_REG_ADDR(L_OEH_VE_ADDR) -#define L_VCOM_HSWITCH_ADDR 0x141c -#define P_L_VCOM_HSWITCH_ADDR VCBUS_REG_ADDR(L_VCOM_HSWITCH_ADDR) -#define L_VCOM_VS_ADDR 0x141d -#define P_L_VCOM_VS_ADDR VCBUS_REG_ADDR(L_VCOM_VS_ADDR) -#define L_VCOM_VE_ADDR 0x141e -#define P_L_VCOM_VE_ADDR VCBUS_REG_ADDR(L_VCOM_VE_ADDR) -#define L_CPV1_HS_ADDR 0x141f -#define P_L_CPV1_HS_ADDR VCBUS_REG_ADDR(L_CPV1_HS_ADDR) -#define L_CPV1_HE_ADDR 0x1420 -#define P_L_CPV1_HE_ADDR VCBUS_REG_ADDR(L_CPV1_HE_ADDR) -#define L_CPV1_VS_ADDR 0x1421 -#define P_L_CPV1_VS_ADDR VCBUS_REG_ADDR(L_CPV1_VS_ADDR) -#define L_CPV1_VE_ADDR 0x1422 -#define P_L_CPV1_VE_ADDR VCBUS_REG_ADDR(L_CPV1_VE_ADDR) -#define L_CPV2_HS_ADDR 0x1423 -#define P_L_CPV2_HS_ADDR VCBUS_REG_ADDR(L_CPV2_HS_ADDR) -#define L_CPV2_HE_ADDR 0x1424 -#define P_L_CPV2_HE_ADDR VCBUS_REG_ADDR(L_CPV2_HE_ADDR) -#define L_CPV2_VS_ADDR 0x1425 -#define P_L_CPV2_VS_ADDR VCBUS_REG_ADDR(L_CPV2_VS_ADDR) -#define L_CPV2_VE_ADDR 0x1426 -#define P_L_CPV2_VE_ADDR VCBUS_REG_ADDR(L_CPV2_VE_ADDR) -#define L_STV1_HS_ADDR 0x1427 -#define P_L_STV1_HS_ADDR VCBUS_REG_ADDR(L_STV1_HS_ADDR) -#define L_STV1_HE_ADDR 0x1428 -#define P_L_STV1_HE_ADDR VCBUS_REG_ADDR(L_STV1_HE_ADDR) -#define L_STV1_VS_ADDR 0x1429 -#define P_L_STV1_VS_ADDR VCBUS_REG_ADDR(L_STV1_VS_ADDR) -#define L_STV1_VE_ADDR 0x142a -#define P_L_STV1_VE_ADDR VCBUS_REG_ADDR(L_STV1_VE_ADDR) -#define L_STV2_HS_ADDR 0x142b -#define P_L_STV2_HS_ADDR VCBUS_REG_ADDR(L_STV2_HS_ADDR) -#define L_STV2_HE_ADDR 0x142c -#define P_L_STV2_HE_ADDR VCBUS_REG_ADDR(L_STV2_HE_ADDR) -#define L_STV2_VS_ADDR 0x142d -#define P_L_STV2_VS_ADDR VCBUS_REG_ADDR(L_STV2_VS_ADDR) -#define L_STV2_VE_ADDR 0x142e -#define P_L_STV2_VE_ADDR VCBUS_REG_ADDR(L_STV2_VE_ADDR) -#define L_OEV1_HS_ADDR 0x142f -#define P_L_OEV1_HS_ADDR VCBUS_REG_ADDR(L_OEV1_HS_ADDR) -#define L_OEV1_HE_ADDR 0x1430 -#define P_L_OEV1_HE_ADDR VCBUS_REG_ADDR(L_OEV1_HE_ADDR) -#define L_OEV1_VS_ADDR 0x1431 -#define P_L_OEV1_VS_ADDR VCBUS_REG_ADDR(L_OEV1_VS_ADDR) -#define L_OEV1_VE_ADDR 0x1432 -#define P_L_OEV1_VE_ADDR VCBUS_REG_ADDR(L_OEV1_VE_ADDR) -#define L_OEV2_HS_ADDR 0x1433 -#define P_L_OEV2_HS_ADDR VCBUS_REG_ADDR(L_OEV2_HS_ADDR) -#define L_OEV2_HE_ADDR 0x1434 -#define P_L_OEV2_HE_ADDR VCBUS_REG_ADDR(L_OEV2_HE_ADDR) -#define L_OEV2_VS_ADDR 0x1435 -#define P_L_OEV2_VS_ADDR VCBUS_REG_ADDR(L_OEV2_VS_ADDR) -#define L_OEV2_VE_ADDR 0x1436 -#define P_L_OEV2_VE_ADDR VCBUS_REG_ADDR(L_OEV2_VE_ADDR) -#define L_OEV3_HS_ADDR 0x1437 -#define P_L_OEV3_HS_ADDR VCBUS_REG_ADDR(L_OEV3_HS_ADDR) -#define L_OEV3_HE_ADDR 0x1438 -#define P_L_OEV3_HE_ADDR VCBUS_REG_ADDR(L_OEV3_HE_ADDR) -#define L_OEV3_VS_ADDR 0x1439 -#define P_L_OEV3_VS_ADDR VCBUS_REG_ADDR(L_OEV3_VS_ADDR) -#define L_OEV3_VE_ADDR 0x143a -#define P_L_OEV3_VE_ADDR VCBUS_REG_ADDR(L_OEV3_VE_ADDR) -#define L_LCD_PWR_ADDR 0x143b -#define P_L_LCD_PWR_ADDR VCBUS_REG_ADDR(L_LCD_PWR_ADDR) -#define L_LCD_PWM0_LO_ADDR 0x143c -#define P_L_LCD_PWM0_LO_ADDR VCBUS_REG_ADDR(L_LCD_PWM0_LO_ADDR) -#define L_LCD_PWM0_HI_ADDR 0x143d -#define P_L_LCD_PWM0_HI_ADDR VCBUS_REG_ADDR(L_LCD_PWM0_HI_ADDR) -#define L_LCD_PWM1_LO_ADDR 0x143e -#define P_L_LCD_PWM1_LO_ADDR VCBUS_REG_ADDR(L_LCD_PWM1_LO_ADDR) -#define L_LCD_PWM1_HI_ADDR 0x143f -#define P_L_LCD_PWM1_HI_ADDR VCBUS_REG_ADDR(L_LCD_PWM1_HI_ADDR) -#define L_INV_CNT_ADDR 0x1440 -#define P_L_INV_CNT_ADDR VCBUS_REG_ADDR(L_INV_CNT_ADDR) -#define L_TCON_MISC_SEL_ADDR 0x1441 -#define P_L_TCON_MISC_SEL_ADDR VCBUS_REG_ADDR(L_TCON_MISC_SEL_ADDR) -#define MLVDS_CLK_CTL1_HI 0x1443 -#define P_MLVDS_CLK_CTL1_HI VCBUS_REG_ADDR(MLVDS_CLK_CTL1_HI) -#define MLVDS_CLK_CTL1_LO 0x1444 -#define P_MLVDS_CLK_CTL1_LO VCBUS_REG_ADDR(MLVDS_CLK_CTL1_LO) -#define L_TCON_DOUBLE_CTL 0x1449 -#define P_L_TCON_DOUBLE_CTL VCBUS_REG_ADDR(L_TCON_DOUBLE_CTL) -#define L_TCON_PATTERN_HI 0x144a -#define P_L_TCON_PATTERN_HI VCBUS_REG_ADDR(L_TCON_PATTERN_HI) -#define L_TCON_PATTERN_LO 0x144b -#define P_L_TCON_PATTERN_LO VCBUS_REG_ADDR(L_TCON_PATTERN_LO) -#define LDIM_BL_ADDR_PORT 0x144e -#define P_LDIM_BL_ADDR_PORT VCBUS_REG_ADDR(LDIM_BL_ADDR_PORT) -#define LDIM_BL_DATA_PORT 0x144f -#define P_LDIM_BL_DATA_PORT VCBUS_REG_ADDR(LDIM_BL_DATA_PORT) -#define L_DE_HS_ADDR 0x1451 -#define P_L_DE_HS_ADDR VCBUS_REG_ADDR(L_DE_HS_ADDR) -#define L_DE_HE_ADDR 0x1452 -#define P_L_DE_HE_ADDR VCBUS_REG_ADDR(L_DE_HE_ADDR) -#define L_DE_VS_ADDR 0x1453 -#define P_L_DE_VS_ADDR VCBUS_REG_ADDR(L_DE_VS_ADDR) -#define L_DE_VE_ADDR 0x1454 -#define P_L_DE_VE_ADDR VCBUS_REG_ADDR(L_DE_VE_ADDR) -#define L_HSYNC_HS_ADDR 0x1455 -#define P_L_HSYNC_HS_ADDR VCBUS_REG_ADDR(L_HSYNC_HS_ADDR) -#define L_HSYNC_HE_ADDR 0x1456 -#define P_L_HSYNC_HE_ADDR VCBUS_REG_ADDR(L_HSYNC_HE_ADDR) -#define L_HSYNC_VS_ADDR 0x1457 -#define P_L_HSYNC_VS_ADDR VCBUS_REG_ADDR(L_HSYNC_VS_ADDR) -#define L_HSYNC_VE_ADDR 0x1458 -#define P_L_HSYNC_VE_ADDR VCBUS_REG_ADDR(L_HSYNC_VE_ADDR) -#define L_VSYNC_HS_ADDR 0x1459 -#define P_L_VSYNC_HS_ADDR VCBUS_REG_ADDR(L_VSYNC_HS_ADDR) -#define L_VSYNC_HE_ADDR 0x145a -#define P_L_VSYNC_HE_ADDR VCBUS_REG_ADDR(L_VSYNC_HE_ADDR) -#define L_VSYNC_VS_ADDR 0x145b -#define P_L_VSYNC_VS_ADDR VCBUS_REG_ADDR(L_VSYNC_VS_ADDR) -#define L_VSYNC_VE_ADDR 0x145c -#define P_L_VSYNC_VE_ADDR VCBUS_REG_ADDR(L_VSYNC_VE_ADDR) -#define L_LCD_MCU_CTL 0x145d -#define P_L_LCD_MCU_CTL VCBUS_REG_ADDR(L_LCD_MCU_CTL) -#define DUAL_MLVDS_CTL 0x1460 -#define P_DUAL_MLVDS_CTL VCBUS_REG_ADDR(DUAL_MLVDS_CTL) - -#define V_INVERSION_PIXEL 0x1470 -#define P_V_INVERSION_PIXEL VCBUS_REG_ADDR(V_INVERSION_PIXEL) -#define V_INVERSION_LINE 0x1471 -#define P_V_INVERSION_LINE VCBUS_REG_ADDR(V_INVERSION_LINE) -#define V_INVERSION_CONTROL 0x1472 -#define P_V_INVERSION_CONTROL VCBUS_REG_ADDR(V_INVERSION_CONTROL) -#define MLVDS2_CONTROL 0x1474 -#define P_MLVDS2_CONTROL VCBUS_REG_ADDR(MLVDS2_CONTROL) -#define MLVDS2_CONFIG_HI 0x1475 -#define P_MLVDS2_CONFIG_HI VCBUS_REG_ADDR(MLVDS2_CONFIG_HI) -#define MLVDS2_CONFIG_LO 0x1476 -#define P_MLVDS2_CONFIG_LO VCBUS_REG_ADDR(MLVDS2_CONFIG_LO) -#define MLVDS2_DUAL_GATE_WR_START 0x1477 -#define RGB_BASE_ADDR 0x1485 -#define P_RGB_BASE_ADDR VCBUS_REG_ADDR(RGB_BASE_ADDR) -#define RGB_COEFF_ADDR 0x1486 -#define P_RGB_COEFF_ADDR VCBUS_REG_ADDR(RGB_COEFF_ADDR) -#define POL_CNTL_ADDR 0x1487 -#define P_POL_CNTL_ADDR VCBUS_REG_ADDR(POL_CNTL_ADDR) -#define DITH_CNTL_ADDR 0x1488 -#define P_DITH_CNTL_ADDR VCBUS_REG_ADDR(DITH_CNTL_ADDR) -#define GAMMA_PROBE_CTRL 0x1489 -#define P_GAMMA_PROBE_CTRL VCBUS_REG_ADDR(GAMMA_PROBE_CTRL) -#define GAMMA_PROBE_COLOR_L 0x148a -#define P_GAMMA_PROBE_COLOR_L VCBUS_REG_ADDR(GAMMA_PROBE_COLOR_L) -#define GAMMA_PROBE_COLOR_H 0x148b -#define P_GAMMA_PROBE_COLOR_H VCBUS_REG_ADDR(GAMMA_PROBE_COLOR_H) -#define GAMMA_PROBE_HL_COLOR 0x148c -#define P_GAMMA_PROBE_HL_COLOR VCBUS_REG_ADDR(GAMMA_PROBE_HL_COLOR) -#define GAMMA_PROBE_POS_X 0x148d -#define P_GAMMA_PROBE_POS_X VCBUS_REG_ADDR(GAMMA_PROBE_POS_X) -#define GAMMA_PROBE_POS_Y 0x148e -#define P_GAMMA_PROBE_POS_Y VCBUS_REG_ADDR(GAMMA_PROBE_POS_Y) -#define STH1_HS_ADDR 0x1490 -#define P_STH1_HS_ADDR VCBUS_REG_ADDR(STH1_HS_ADDR) -#define STH1_HE_ADDR 0x1491 -#define P_STH1_HE_ADDR VCBUS_REG_ADDR(STH1_HE_ADDR) -#define STH1_VS_ADDR 0x1492 -#define P_STH1_VS_ADDR VCBUS_REG_ADDR(STH1_VS_ADDR) -#define STH1_VE_ADDR 0x1493 -#define P_STH1_VE_ADDR VCBUS_REG_ADDR(STH1_VE_ADDR) -#define STH2_HS_ADDR 0x1494 -#define P_STH2_HS_ADDR VCBUS_REG_ADDR(STH2_HS_ADDR) -#define STH2_HE_ADDR 0x1495 -#define P_STH2_HE_ADDR VCBUS_REG_ADDR(STH2_HE_ADDR) -#define STH2_VS_ADDR 0x1496 -#define P_STH2_VS_ADDR VCBUS_REG_ADDR(STH2_VS_ADDR) -#define STH2_VE_ADDR 0x1497 -#define P_STH2_VE_ADDR VCBUS_REG_ADDR(STH2_VE_ADDR) -#define OEH_HS_ADDR 0x1498 -#define P_OEH_HS_ADDR VCBUS_REG_ADDR(OEH_HS_ADDR) -#define OEH_HE_ADDR 0x1499 -#define P_OEH_HE_ADDR VCBUS_REG_ADDR(OEH_HE_ADDR) -#define OEH_VS_ADDR 0x149a -#define P_OEH_VS_ADDR VCBUS_REG_ADDR(OEH_VS_ADDR) -#define OEH_VE_ADDR 0x149b -#define P_OEH_VE_ADDR VCBUS_REG_ADDR(OEH_VE_ADDR) -#define VCOM_HSWITCH_ADDR 0x149c -#define P_VCOM_HSWITCH_ADDR VCBUS_REG_ADDR(VCOM_HSWITCH_ADDR) -#define VCOM_VS_ADDR 0x149d -#define P_VCOM_VS_ADDR VCBUS_REG_ADDR(VCOM_VS_ADDR) -#define VCOM_VE_ADDR 0x149e -#define P_VCOM_VE_ADDR VCBUS_REG_ADDR(VCOM_VE_ADDR) -#define CPV1_HS_ADDR 0x149f -#define P_CPV1_HS_ADDR VCBUS_REG_ADDR(CPV1_HS_ADDR) -#define CPV1_HE_ADDR 0x14a0 -#define P_CPV1_HE_ADDR VCBUS_REG_ADDR(CPV1_HE_ADDR) -#define CPV1_VS_ADDR 0x14a1 -#define P_CPV1_VS_ADDR VCBUS_REG_ADDR(CPV1_VS_ADDR) -#define CPV1_VE_ADDR 0x14a2 -#define P_CPV1_VE_ADDR VCBUS_REG_ADDR(CPV1_VE_ADDR) -#define CPV2_HS_ADDR 0x14a3 -#define P_CPV2_HS_ADDR VCBUS_REG_ADDR(CPV2_HS_ADDR) -#define CPV2_HE_ADDR 0x14a4 -#define P_CPV2_HE_ADDR VCBUS_REG_ADDR(CPV2_HE_ADDR) -#define CPV2_VS_ADDR 0x14a5 -#define P_CPV2_VS_ADDR VCBUS_REG_ADDR(CPV2_VS_ADDR) -#define CPV2_VE_ADDR 0x14a6 -#define P_CPV2_VE_ADDR VCBUS_REG_ADDR(CPV2_VE_ADDR) -#define STV1_HS_ADDR 0x14a7 -#define P_STV1_HS_ADDR VCBUS_REG_ADDR(STV1_HS_ADDR) -#define STV1_HE_ADDR 0x14a8 -#define P_STV1_HE_ADDR VCBUS_REG_ADDR(STV1_HE_ADDR) -#define STV1_VS_ADDR 0x14a9 -#define P_STV1_VS_ADDR VCBUS_REG_ADDR(STV1_VS_ADDR) -#define STV1_VE_ADDR 0x14aa -#define P_STV1_VE_ADDR VCBUS_REG_ADDR(STV1_VE_ADDR) -#define STV2_HS_ADDR 0x14ab -#define P_STV2_HS_ADDR VCBUS_REG_ADDR(STV2_HS_ADDR) -#define STV2_HE_ADDR 0x14ac -#define P_STV2_HE_ADDR VCBUS_REG_ADDR(STV2_HE_ADDR) -#define STV2_VS_ADDR 0x14ad -#define P_STV2_VS_ADDR VCBUS_REG_ADDR(STV2_VS_ADDR) -#define STV2_VE_ADDR 0x14ae -#define P_STV2_VE_ADDR VCBUS_REG_ADDR(STV2_VE_ADDR) -#define OEV1_HS_ADDR 0x14af -#define P_OEV1_HS_ADDR VCBUS_REG_ADDR(OEV1_HS_ADDR) -#define OEV1_HE_ADDR 0x14b0 -#define P_OEV1_HE_ADDR VCBUS_REG_ADDR(OEV1_HE_ADDR) -#define OEV1_VS_ADDR 0x14b1 -#define P_OEV1_VS_ADDR VCBUS_REG_ADDR(OEV1_VS_ADDR) -#define OEV1_VE_ADDR 0x14b2 -#define P_OEV1_VE_ADDR VCBUS_REG_ADDR(OEV1_VE_ADDR) -#define OEV2_HS_ADDR 0x14b3 -#define P_OEV2_HS_ADDR VCBUS_REG_ADDR(OEV2_HS_ADDR) -#define OEV2_HE_ADDR 0x14b4 -#define P_OEV2_HE_ADDR VCBUS_REG_ADDR(OEV2_HE_ADDR) -#define OEV2_VS_ADDR 0x14b5 -#define P_OEV2_VS_ADDR VCBUS_REG_ADDR(OEV2_VS_ADDR) -#define OEV2_VE_ADDR 0x14b6 -#define P_OEV2_VE_ADDR VCBUS_REG_ADDR(OEV2_VE_ADDR) -#define OEV3_HS_ADDR 0x14b7 -#define P_OEV3_HS_ADDR VCBUS_REG_ADDR(OEV3_HS_ADDR) -#define OEV3_HE_ADDR 0x14b8 -#define P_OEV3_HE_ADDR VCBUS_REG_ADDR(OEV3_HE_ADDR) -#define OEV3_VS_ADDR 0x14b9 -#define P_OEV3_VS_ADDR VCBUS_REG_ADDR(OEV3_VS_ADDR) -#define OEV3_VE_ADDR 0x14ba -#define P_OEV3_VE_ADDR VCBUS_REG_ADDR(OEV3_VE_ADDR) -#define LCD_PWR_ADDR 0x14bb -#define P_LCD_PWR_ADDR VCBUS_REG_ADDR(LCD_PWR_ADDR) -#define LCD_PWM0_LO_ADDR 0x14bc -#define P_LCD_PWM0_LO_ADDR VCBUS_REG_ADDR(LCD_PWM0_LO_ADDR) -#define LCD_PWM0_HI_ADDR 0x14bd -#define P_LCD_PWM0_HI_ADDR VCBUS_REG_ADDR(LCD_PWM0_HI_ADDR) -#define LCD_PWM1_LO_ADDR 0x14be -#define P_LCD_PWM1_LO_ADDR VCBUS_REG_ADDR(LCD_PWM1_LO_ADDR) -#define LCD_PWM1_HI_ADDR 0x14bf -#define P_LCD_PWM1_HI_ADDR VCBUS_REG_ADDR(LCD_PWM1_HI_ADDR) -#define INV_CNT_ADDR 0x14c0 -#define P_INV_CNT_ADDR VCBUS_REG_ADDR(INV_CNT_ADDR) -#define TCON_MISC_SEL_ADDR 0x14c1 -#define P_TCON_MISC_SEL_ADDR VCBUS_REG_ADDR(TCON_MISC_SEL_ADDR) -#define DUAL_PORT_CNTL_ADDR 0x14c2 -#define P_DUAL_PORT_CNTL_ADDR VCBUS_REG_ADDR(DUAL_PORT_CNTL_ADDR) -#define MLVDS_CONTROL 0x14c3 -#define P_MLVDS_CONTROL VCBUS_REG_ADDR(MLVDS_CONTROL) -#define MLVDS_CONFIG_HI 0x14c7 -#define P_MLVDS_CONFIG_HI VCBUS_REG_ADDR(MLVDS_CONFIG_HI) -#define MLVDS_CONFIG_LO 0x14c8 -#define P_MLVDS_CONFIG_LO VCBUS_REG_ADDR(MLVDS_CONFIG_LO) -#define TCON_DOUBLE_CTL 0x14c9 -#define P_TCON_DOUBLE_CTL VCBUS_REG_ADDR(TCON_DOUBLE_CTL) -#define TCON_PATTERN_HI 0x14ca -#define P_TCON_PATTERN_HI VCBUS_REG_ADDR(TCON_PATTERN_HI) -#define TCON_PATTERN_LO 0x14cb -#define P_TCON_PATTERN_LO VCBUS_REG_ADDR(TCON_PATTERN_LO) -#define TCON_CONTROL_HI 0x14cc -#define P_TCON_CONTROL_HI VCBUS_REG_ADDR(TCON_CONTROL_HI) -#define TCON_CONTROL_LO 0x14cd -#define P_TCON_CONTROL_LO VCBUS_REG_ADDR(TCON_CONTROL_LO) -#define LVDS_BLANK_DATA_HI 0x14ce -#define P_LVDS_BLANK_DATA_HI VCBUS_REG_ADDR(LVDS_BLANK_DATA_HI) -#define LVDS_BLANK_DATA_LO 0x14cf -#define P_LVDS_BLANK_DATA_LO VCBUS_REG_ADDR(LVDS_BLANK_DATA_LO) -#define LVDS_PACK_CNTL_ADDR 0x14d0 -#define P_LVDS_PACK_CNTL_ADDR VCBUS_REG_ADDR(LVDS_PACK_CNTL_ADDR) -#define DE_HS_ADDR 0x14d1 -#define P_DE_HS_ADDR VCBUS_REG_ADDR(DE_HS_ADDR) -#define DE_HE_ADDR 0x14d2 -#define P_DE_HE_ADDR VCBUS_REG_ADDR(DE_HE_ADDR) -#define DE_VS_ADDR 0x14d3 -#define P_DE_VS_ADDR VCBUS_REG_ADDR(DE_VS_ADDR) -#define DE_VE_ADDR 0x14d4 -#define P_DE_VE_ADDR VCBUS_REG_ADDR(DE_VE_ADDR) -#define HSYNC_HS_ADDR 0x14d5 -#define P_HSYNC_HS_ADDR VCBUS_REG_ADDR(HSYNC_HS_ADDR) -#define HSYNC_HE_ADDR 0x14d6 -#define P_HSYNC_HE_ADDR VCBUS_REG_ADDR(HSYNC_HE_ADDR) -#define HSYNC_VS_ADDR 0x14d7 -#define P_HSYNC_VS_ADDR VCBUS_REG_ADDR(HSYNC_VS_ADDR) -#define HSYNC_VE_ADDR 0x14d8 -#define P_HSYNC_VE_ADDR VCBUS_REG_ADDR(HSYNC_VE_ADDR) -#define VSYNC_HS_ADDR 0x14d9 -#define P_VSYNC_HS_ADDR VCBUS_REG_ADDR(VSYNC_HS_ADDR) -#define VSYNC_HE_ADDR 0x14da -#define P_VSYNC_HE_ADDR VCBUS_REG_ADDR(VSYNC_HE_ADDR) -#define VSYNC_VS_ADDR 0x14db -#define P_VSYNC_VS_ADDR VCBUS_REG_ADDR(VSYNC_VS_ADDR) -#define VSYNC_VE_ADDR 0x14dc -#define P_VSYNC_VE_ADDR VCBUS_REG_ADDR(VSYNC_VE_ADDR) -#define LCD_MCU_CTL 0x14dd -#define P_LCD_MCU_CTL VCBUS_REG_ADDR(LCD_MCU_CTL) -#define LCD_MCU_DATA_0 0x14de -#define P_LCD_MCU_DATA_0 VCBUS_REG_ADDR(LCD_MCU_DATA_0) -#define LCD_MCU_DATA_1 0x14df -#define P_LCD_MCU_DATA_1 VCBUS_REG_ADDR(LCD_MCU_DATA_1) -#define LVDS_GEN_CNTL 0x14e0 -#define P_LVDS_GEN_CNTL VCBUS_REG_ADDR(LVDS_GEN_CNTL) -#define LVDS_PHY_CNTL0 0x14e1 -#define P_LVDS_PHY_CNTL0 VCBUS_REG_ADDR(LVDS_PHY_CNTL0) -#define LVDS_PHY_CNTL1 0x14e2 -#define P_LVDS_PHY_CNTL1 VCBUS_REG_ADDR(LVDS_PHY_CNTL1) -#define LVDS_PHY_CNTL2 0x14e3 -#define P_LVDS_PHY_CNTL2 VCBUS_REG_ADDR(LVDS_PHY_CNTL2) -#define LVDS_PHY_CNTL3 0x14e4 -#define P_LVDS_PHY_CNTL3 VCBUS_REG_ADDR(LVDS_PHY_CNTL3) -#define LVDS_PHY_CNTL4 0x14e5 -#define P_LVDS_PHY_CNTL4 VCBUS_REG_ADDR(LVDS_PHY_CNTL4) -#define LVDS_PHY_CNTL5 0x14e6 -#define P_LVDS_PHY_CNTL5 VCBUS_REG_ADDR(LVDS_PHY_CNTL5) -#define LVDS_SRG_TEST 0x14e8 -#define P_LVDS_SRG_TEST VCBUS_REG_ADDR(LVDS_SRG_TEST) -#define LVDS_BIST_MUX0 0x14e9 -#define P_LVDS_BIST_MUX0 VCBUS_REG_ADDR(LVDS_BIST_MUX0) -#define LVDS_BIST_MUX1 0x14ea -#define P_LVDS_BIST_MUX1 VCBUS_REG_ADDR(LVDS_BIST_MUX1) -#define LVDS_BIST_FIXED0 0x14eb -#define P_LVDS_BIST_FIXED0 VCBUS_REG_ADDR(LVDS_BIST_FIXED0) -#define LVDS_BIST_FIXED1 0x14ec -#define P_LVDS_BIST_FIXED1 VCBUS_REG_ADDR(LVDS_BIST_FIXED1) -#define P_VPU_OSD1_MMC_CTRL VCBUS_REG_ADDR(VPU_OSD1_MMC_CTRL) -#define VPU_OSD2_MMC_CTRL 0x2702 -#define P_VPU_OSD2_MMC_CTRL VCBUS_REG_ADDR(VPU_OSD2_MMC_CTRL) -#define VPU_VD1_MMC_CTRL 0x2703 -#define P_VPU_VD1_MMC_CTRL VCBUS_REG_ADDR(VPU_VD1_MMC_CTRL) -#define VPU_VD2_MMC_CTRL 0x2704 -#define P_VPU_VD2_MMC_CTRL VCBUS_REG_ADDR(VPU_VD2_MMC_CTRL) -#define VPU_DI_IF1_MMC_CTRL 0x2705 -#define P_VPU_DI_IF1_MMC_CTRL VCBUS_REG_ADDR(VPU_DI_IF1_MMC_CTRL) -#define VPU_DI_MEM_MMC_CTRL 0x2706 -#define P_VPU_DI_MEM_MMC_CTRL VCBUS_REG_ADDR(VPU_DI_MEM_MMC_CTRL) -#define VPU_DI_INP_MMC_CTRL 0x2707 -#define P_VPU_DI_INP_MMC_CTRL VCBUS_REG_ADDR(VPU_DI_INP_MMC_CTRL) -#define VPU_DI_NRWR_MMC_CTRL 0x270b -#define P_VPU_DI_NRWR_MMC_CTRL VCBUS_REG_ADDR(VPU_DI_NRWR_MMC_CTRL) -#define VPU_DI_DIWR_MMC_CTRL 0x270c -#define P_VPU_DI_DIWR_MMC_CTRL VCBUS_REG_ADDR(VPU_DI_DIWR_MMC_CTRL) -#define VPU_VDIN0_MMC_CTRL 0x270d -#define P_VPU_VDIN0_MMC_CTRL VCBUS_REG_ADDR(VPU_VDIN0_MMC_CTRL) -#define VPU_VDIN1_MMC_CTRL 0x270e -#define P_VPU_VDIN1_MMC_CTRL VCBUS_REG_ADDR(VPU_VDIN1_MMC_CTRL) -#define VPU_BT656_MMC_CTRL 0x270f -#define P_VPU_BT656_MMC_CTRL VCBUS_REG_ADDR(VPU_BT656_MMC_CTRL) -#define VPU_TVD3D_MMC_CTRL 0x2710 -#define P_VPU_TVD3D_MMC_CTRL VCBUS_REG_ADDR(VPU_TVD3D_MMC_CTRL) -#define VPU_TVDVBI_MMC_CTRL 0x2711 -#define P_VPU_TVDVBI_MMC_CTRL VCBUS_REG_ADDR(VPU_TVDVBI_MMC_CTRL) -#define VPU_TVDVBI_VSLATCH_ADDR 0x2712 -#define VPU_HDMI_SETTING 0x271b -#define P_VPU_HDMI_SETTING VCBUS_REG_ADDR(VPU_HDMI_SETTING) -#define ENCI_INFO_READ 0x271c -#define P_ENCI_INFO_READ VCBUS_REG_ADDR(ENCI_INFO_READ) -#define ENCP_INFO_READ 0x271d -#define P_ENCP_INFO_READ VCBUS_REG_ADDR(ENCP_INFO_READ) -#define ENCT_INFO_READ 0x271e -#define P_ENCT_INFO_READ VCBUS_REG_ADDR(ENCT_INFO_READ) -#define ENCL_INFO_READ 0x271f -#define P_ENCL_INFO_READ VCBUS_REG_ADDR(ENCL_INFO_READ) -#define VPU_SW_RESET 0x2720 -#define P_VPU_SW_RESET VCBUS_REG_ADDR(VPU_SW_RESET) -#define VPU_D2D3_MMC_CTRL 0x2721 -#define P_VPU_D2D3_MMC_CTRL VCBUS_REG_ADDR(VPU_D2D3_MMC_CTRL) -#define VPU_CONT_MMC_CTRL 0x2722 -#define P_VPU_CONT_MMC_CTRL VCBUS_REG_ADDR(VPU_CONT_MMC_CTRL) -#define VPU_CLK_GATE 0x2723 -#define P_VPU_CLK_GATE VCBUS_REG_ADDR(VPU_CLK_GATE) -#define VPU_RDMA_MMC_CTRL 0x2724 -#define P_VPU_RDMA_MMC_CTRL VCBUS_REG_ADDR(VPU_RDMA_MMC_CTRL) -#define VPU_MEM_PD_REG0 0x2725 -#define P_VPU_MEM_PD_REG0 VCBUS_REG_ADDR(VPU_MEM_PD_REG0) -#define VPU_MEM_PD_REG1 0x2726 -#define P_VPU_MEM_PD_REG1 VCBUS_REG_ADDR(VPU_MEM_PD_REG1) -#define VPU_HDMI_DATA_OVR 0x2727 -#define P_VPU_HDMI_DATA_OVR VCBUS_REG_ADDR(VPU_HDMI_DATA_OVR) -#define VPU_PROT1_MMC_CTRL 0x2728 -#define P_VPU_PROT1_MMC_CTRL VCBUS_REG_ADDR(VPU_PROT1_MMC_CTRL) -#define VPU_PROT2_MMC_CTRL 0x2729 -#define P_VPU_PROT2_MMC_CTRL VCBUS_REG_ADDR(VPU_PROT2_MMC_CTRL) -#define VPU_PROT3_MMC_CTRL 0x272a -#define P_VPU_PROT3_MMC_CTRL VCBUS_REG_ADDR(VPU_PROT3_MMC_CTRL) -#define VPU_ARB4_V1_MMC_CTRL 0x272b -#define P_VPU_ARB4_V1_MMC_CTRL VCBUS_REG_ADDR(VPU_ARB4_V1_MMC_CTRL) -#define VPU_ARB4_V2_MMC_CTRL 0x272c -#define P_VPU_ARB4_V2_MMC_CTRL VCBUS_REG_ADDR(VPU_ARB4_V2_MMC_CTRL) -#define VPU_VPU_PWM_V0 0x2730 -#define P_VPU_VPU_PWM_V0 VCBUS_REG_ADDR(VPU_VPU_PWM_V0) -#define VPU_VPU_PWM_V1 0x2731 -#define P_VPU_VPU_PWM_V1 VCBUS_REG_ADDR(VPU_VPU_PWM_V1) -#define VPU_VPU_PWM_V2 0x2732 -#define P_VPU_VPU_PWM_V2 VCBUS_REG_ADDR(VPU_VPU_PWM_V2) -#define VPU_VPU_PWM_V3 0x2733 -#define P_VPU_VPU_PWM_V3 VCBUS_REG_ADDR(VPU_VPU_PWM_V3) -#define VPU_VPU_PWM_H0 0x2734 -#define P_VPU_VPU_PWM_H0 VCBUS_REG_ADDR(VPU_VPU_PWM_H0) -#define VPU_VPU_PWM_H1 0x2735 -#define P_VPU_VPU_PWM_H1 VCBUS_REG_ADDR(VPU_VPU_PWM_H1) -#define VPU_VPU_PWM_H2 0x2736 -#define VPU_PROT2_Y_LEN_STEP 0x2764 -#define P_VPU_PROT2_Y_LEN_STEP VCBUS_REG_ADDR(VPU_PROT2_Y_LEN_STEP) -#define VPU_PROT2_RPT_LOOP 0x2765 -#define P_VPU_PROT2_RPT_LOOP VCBUS_REG_ADDR(VPU_PROT2_RPT_LOOP) -#define VPU_PROT2_RPT_PAT 0x2766 -#define P_VPU_PROT2_RPT_PAT VCBUS_REG_ADDR(VPU_PROT2_RPT_PAT) -#define VPU_PROT2_DDR 0x2767 -#define P_VPU_PROT2_DDR VCBUS_REG_ADDR(VPU_PROT2_DDR) -#define VPU_PROT2_RBUF_ROOM 0x2768 -#define P_VPU_PROT2_RBUF_ROOM VCBUS_REG_ADDR(VPU_PROT2_RBUF_ROOM) -#define VPU_PROT2_STAT_0 0x2769 -#define P_VPU_PROT2_STAT_0 VCBUS_REG_ADDR(VPU_PROT2_STAT_0) -#define VPU_PROT2_STAT_1 0x276a -#define P_VPU_PROT2_STAT_1 VCBUS_REG_ADDR(VPU_PROT2_STAT_1) -#define VPU_PROT2_STAT_2 0x276b -#define MC_CTRL_REG 0x0900 -#define P_MC_CTRL_REG DOS_REG_ADDR(MC_CTRL_REG) -#define MC_MB_INFO 0x0901 -#define P_MC_MB_INFO DOS_REG_ADDR(MC_MB_INFO) -#define MC_PIC_INFO 0x0902 -#define P_MC_PIC_INFO DOS_REG_ADDR(MC_PIC_INFO) -#define MC_HALF_PEL_ONE 0x0903 -#define P_MC_HALF_PEL_ONE DOS_REG_ADDR(MC_HALF_PEL_ONE) -#define MC_HALF_PEL_TWO 0x0904 -#define P_MC_HALF_PEL_TWO DOS_REG_ADDR(MC_HALF_PEL_TWO) -#define POWER_CTL_MC 0x0905 -#define P_POWER_CTL_MC DOS_REG_ADDR(POWER_CTL_MC) -#define MC_CMD 0x0906 -#define P_MC_CMD DOS_REG_ADDR(MC_CMD) -#define MC_CTRL0 0x0907 -#define P_MC_CTRL0 DOS_REG_ADDR(MC_CTRL0) -#define MC_PIC_W_H 0x0908 -#define P_MC_PIC_W_H DOS_REG_ADDR(MC_PIC_W_H) -#define MC_STATUS0 0x0909 -#define P_MC_STATUS0 DOS_REG_ADDR(MC_STATUS0) -#define MC_STATUS1 0x090a -#define P_MC_STATUS1 DOS_REG_ADDR(MC_STATUS1) -#define MC_CTRL1 0x090b -#define P_MC_CTRL1 DOS_REG_ADDR(MC_CTRL1) -#define MC_MIX_RATIO0 0x090c -#define P_MC_MIX_RATIO0 DOS_REG_ADDR(MC_MIX_RATIO0) -#define MC_MIX_RATIO1 0x090d -#define P_MC_MIX_RATIO1 DOS_REG_ADDR(MC_MIX_RATIO1) -#define MC_DP_MB_XY 0x090e -#define P_MC_DP_MB_XY DOS_REG_ADDR(MC_DP_MB_XY) -#define MC_OM_MB_XY 0x090f -#define P_MC_OM_MB_XY DOS_REG_ADDR(MC_OM_MB_XY) -#define PSCALE_RST 0x0910 -#define P_PSCALE_RST DOS_REG_ADDR(PSCALE_RST) -#define PSCALE_CTRL 0x0911 -#define P_PSCALE_CTRL DOS_REG_ADDR(PSCALE_CTRL) -#define PSCALE_PICI_W 0x0912 -#define P_PSCALE_PICI_W DOS_REG_ADDR(PSCALE_PICI_W) -#define PSCALE_PICI_H 0x0913 -#define P_PSCALE_PICI_H DOS_REG_ADDR(PSCALE_PICI_H) -#define PSCALE_PICO_W 0x0914 -#define P_PSCALE_PICO_W DOS_REG_ADDR(PSCALE_PICO_W) -#define PSCALE_PICO_H 0x0915 -#define P_PSCALE_PICO_H DOS_REG_ADDR(PSCALE_PICO_H) -#define PSCALE_PICO_START_X 0x0916 -#define P_PSCALE_PICO_START_X DOS_REG_ADDR(PSCALE_PICO_START_X) -#define PSCALE_PICO_START_Y 0x0917 -#define P_PSCALE_PICO_START_Y DOS_REG_ADDR(PSCALE_PICO_START_Y) -#define PSCALE_DUMMY 0x0918 -#define P_PSCALE_DUMMY DOS_REG_ADDR(PSCALE_DUMMY) -#define PSCALE_FILT0_COEF0 0x0919 -#define P_PSCALE_FILT0_COEF0 DOS_REG_ADDR(PSCALE_FILT0_COEF0) -#define PSCALE_FILT0_COEF1 0x091a -#define P_PSCALE_FILT0_COEF1 DOS_REG_ADDR(PSCALE_FILT0_COEF1) -#define PSCALE_CMD_CTRL 0x091b -#define P_PSCALE_CMD_CTRL DOS_REG_ADDR(PSCALE_CMD_CTRL) -#define PSCALE_CMD_BLK_X 0x091c -#define P_PSCALE_CMD_BLK_X DOS_REG_ADDR(PSCALE_CMD_BLK_X) -#define PSCALE_CMD_BLK_Y 0x091d -#define P_PSCALE_CMD_BLK_Y DOS_REG_ADDR(PSCALE_CMD_BLK_Y) -#define PSCALE_STATUS 0x091e -#define P_PSCALE_STATUS DOS_REG_ADDR(PSCALE_STATUS) -#define PSCALE_BMEM_ADDR 0x091f -#define P_PSCALE_BMEM_ADDR DOS_REG_ADDR(PSCALE_BMEM_ADDR) -#define PSCALE_BMEM_DAT 0x0920 -#define P_PSCALE_BMEM_DAT DOS_REG_ADDR(PSCALE_BMEM_DAT) -#define PSCALE_DRAM_BUF_CTRL 0x0921 -#define P_PSCALE_DRAM_BUF_CTRL DOS_REG_ADDR(PSCALE_DRAM_BUF_CTRL) -#define PSCALE_MCMD_CTRL 0x0922 -#define P_PSCALE_MCMD_CTRL DOS_REG_ADDR(PSCALE_MCMD_CTRL) -#define PSCALE_MCMD_XSIZE 0x0923 -#define P_PSCALE_MCMD_XSIZE DOS_REG_ADDR(PSCALE_MCMD_XSIZE) -#define PSCALE_MCMD_YSIZE 0x0924 -#define P_PSCALE_MCMD_YSIZE DOS_REG_ADDR(PSCALE_MCMD_YSIZE) -#define PSCALE_PICO_SHIFT_XY 0x0928 -#define P_PSCALE_PICO_SHIFT_XY DOS_REG_ADDR(PSCALE_PICO_SHIFT_XY) -#define PSCALE_CTRL1 0x0929 -#define P_PSCALE_CTRL1 DOS_REG_ADDR(PSCALE_CTRL1) -#define PSCALE_SRCKEY_CTRL0 0x092a -#define PSCALE_CTRL2 0x092e -#define P_PSCALE_CTRL2 DOS_REG_ADDR(PSCALE_CTRL2) -/*add from M8m2*/ -#define HDEC_MC_OMEM_AUTO 0x0930 -#define P_HDEC_MC_OMEM_AUTO DOS_REG_ADDR(HDEC_MC_OMEM_AUTO) -#define HDEC_MC_MBRIGHT_IDX 0x0931 -#define P_HDEC_MC_MBRIGHT_IDX DOS_REG_ADDR(HDEC_MC_MBRIGHT_IDX) -#define HDEC_MC_MBRIGHT_RD 0x0932 -#define P_HDEC_MC_MBRIGHT_RD DOS_REG_ADDR(HDEC_MC_MBRIGHT_RD) -/**/ -#define MC_MPORT_CTRL 0x0940 -#define P_MC_MPORT_CTRL DOS_REG_ADDR(MC_MPORT_CTRL) -#define MC_MPORT_DAT 0x0941 -#define P_MC_MPORT_DAT DOS_REG_ADDR(MC_MPORT_DAT) -#define MC_WT_PRED_CTRL 0x0942 -#define P_MC_WT_PRED_CTRL DOS_REG_ADDR(MC_WT_PRED_CTRL) -#define MC_MBBOT_ST_ODD_ADDR 0x0945 -#define P_MC_MBBOT_ST_ODD_ADDR DOS_REG_ADDR(MC_MBBOT_ST_ODD_ADDR) -#define MC_DPDN_MB_XY 0x0946 -#define P_MC_DPDN_MB_XY DOS_REG_ADDR(MC_DPDN_MB_XY) -#define MC_OMDN_MB_XY 0x0947 -#define P_MC_OMDN_MB_XY DOS_REG_ADDR(MC_OMDN_MB_XY) -#define MC_HCMDBUF_H 0x0948 -#define P_MC_HCMDBUF_H DOS_REG_ADDR(MC_HCMDBUF_H) -#define MC_HCMDBUF_L 0x0949 -#define P_MC_HCMDBUF_L DOS_REG_ADDR(MC_HCMDBUF_L) -#define MC_HCMD_H 0x094a -#define P_MC_HCMD_H DOS_REG_ADDR(MC_HCMD_H) -#define MC_HCMD_L 0x094b -#define P_MC_HCMD_L DOS_REG_ADDR(MC_HCMD_L) -#define MC_IDCT_DAT 0x094c -#define P_MC_IDCT_DAT DOS_REG_ADDR(MC_IDCT_DAT) -#define MC_CTRL_GCLK_CTRL 0x094d -#define P_MC_CTRL_GCLK_CTRL DOS_REG_ADDR(MC_CTRL_GCLK_CTRL) -#define MC_OTHER_GCLK_CTRL 0x094e -#define P_MC_OTHER_GCLK_CTRL DOS_REG_ADDR(MC_OTHER_GCLK_CTRL) -#define MC_CTRL2 0x094f -#define P_MC_CTRL2 DOS_REG_ADDR(MC_CTRL2) -#define MDEC_PIC_DC_CTRL 0x098e -#define P_MDEC_PIC_DC_CTRL DOS_REG_ADDR(MDEC_PIC_DC_CTRL) -#define MDEC_PIC_DC_STATUS 0x098f -#define P_MDEC_PIC_DC_STATUS DOS_REG_ADDR(MDEC_PIC_DC_STATUS) -#define ANC0_CANVAS_ADDR 0x0990 -#define P_ANC0_CANVAS_ADDR DOS_REG_ADDR(ANC0_CANVAS_ADDR) -#define ANC1_CANVAS_ADDR 0x0991 -#define P_ANC1_CANVAS_ADDR DOS_REG_ADDR(ANC1_CANVAS_ADDR) -#define ANC2_CANVAS_ADDR 0x0992 -#define P_ANC2_CANVAS_ADDR DOS_REG_ADDR(ANC2_CANVAS_ADDR) -#define ANC3_CANVAS_ADDR 0x0993 -#define P_ANC3_CANVAS_ADDR DOS_REG_ADDR(ANC3_CANVAS_ADDR) -#define ANC4_CANVAS_ADDR 0x0994 -#define P_ANC4_CANVAS_ADDR DOS_REG_ADDR(ANC4_CANVAS_ADDR) -#define ANC5_CANVAS_ADDR 0x0995 -#define P_ANC5_CANVAS_ADDR DOS_REG_ADDR(ANC5_CANVAS_ADDR) -#define ANC6_CANVAS_ADDR 0x0996 -#define P_ANC6_CANVAS_ADDR DOS_REG_ADDR(ANC6_CANVAS_ADDR) -#define ANC7_CANVAS_ADDR 0x0997 -#define P_ANC7_CANVAS_ADDR DOS_REG_ADDR(ANC7_CANVAS_ADDR) -#define ANC8_CANVAS_ADDR 0x0998 -#define P_ANC8_CANVAS_ADDR DOS_REG_ADDR(ANC8_CANVAS_ADDR) -#define ANC9_CANVAS_ADDR 0x0999 -#define P_ANC9_CANVAS_ADDR DOS_REG_ADDR(ANC9_CANVAS_ADDR) -#define ANC10_CANVAS_ADDR 0x099a -#define P_ANC10_CANVAS_ADDR DOS_REG_ADDR(ANC10_CANVAS_ADDR) -#define ANC11_CANVAS_ADDR 0x099b -#define P_ANC11_CANVAS_ADDR DOS_REG_ADDR(ANC11_CANVAS_ADDR) -#define ANC12_CANVAS_ADDR 0x099c -#define P_ANC12_CANVAS_ADDR DOS_REG_ADDR(ANC12_CANVAS_ADDR) -#define ANC13_CANVAS_ADDR 0x099d -#define P_ANC13_CANVAS_ADDR DOS_REG_ADDR(ANC13_CANVAS_ADDR) -#define ANC14_CANVAS_ADDR 0x099e -#define P_ANC14_CANVAS_ADDR DOS_REG_ADDR(ANC14_CANVAS_ADDR) -#define ANC15_CANVAS_ADDR 0x099f -#define P_ANC15_CANVAS_ADDR DOS_REG_ADDR(ANC15_CANVAS_ADDR) -#define ANC16_CANVAS_ADDR 0x09a0 -#define P_ANC16_CANVAS_ADDR DOS_REG_ADDR(ANC16_CANVAS_ADDR) -#define ANC17_CANVAS_ADDR 0x09a1 -#define P_ANC17_CANVAS_ADDR DOS_REG_ADDR(ANC17_CANVAS_ADDR) -#define ANC18_CANVAS_ADDR 0x09a2 -#define P_ANC18_CANVAS_ADDR DOS_REG_ADDR(ANC18_CANVAS_ADDR) -#define ANC19_CANVAS_ADDR 0x09a3 -#define P_ANC19_CANVAS_ADDR DOS_REG_ADDR(ANC19_CANVAS_ADDR) -#define ANC20_CANVAS_ADDR 0x09a4 -#define P_ANC20_CANVAS_ADDR DOS_REG_ADDR(ANC20_CANVAS_ADDR) -#define ANC21_CANVAS_ADDR 0x09a5 -#define P_ANC21_CANVAS_ADDR DOS_REG_ADDR(ANC21_CANVAS_ADDR) -#define ANC22_CANVAS_ADDR 0x09a6 -#define P_ANC22_CANVAS_ADDR DOS_REG_ADDR(ANC22_CANVAS_ADDR) -#define ANC23_CANVAS_ADDR 0x09a7 -#define P_ANC23_CANVAS_ADDR DOS_REG_ADDR(ANC23_CANVAS_ADDR) -#define ANC24_CANVAS_ADDR 0x09a8 -#define P_ANC24_CANVAS_ADDR DOS_REG_ADDR(ANC24_CANVAS_ADDR) -#define ANC25_CANVAS_ADDR 0x09a9 -#define P_ANC25_CANVAS_ADDR DOS_REG_ADDR(ANC25_CANVAS_ADDR) -#define ANC26_CANVAS_ADDR 0x09aa -#define P_ANC26_CANVAS_ADDR DOS_REG_ADDR(ANC26_CANVAS_ADDR) -#define ANC27_CANVAS_ADDR 0x09ab -#define P_ANC27_CANVAS_ADDR DOS_REG_ADDR(ANC27_CANVAS_ADDR) -#define ANC28_CANVAS_ADDR 0x09ac -#define P_ANC28_CANVAS_ADDR DOS_REG_ADDR(ANC28_CANVAS_ADDR) -#define ANC29_CANVAS_ADDR 0x09ad -#define P_ANC29_CANVAS_ADDR DOS_REG_ADDR(ANC29_CANVAS_ADDR) -#define ANC30_CANVAS_ADDR 0x09ae -#define P_ANC30_CANVAS_ADDR DOS_REG_ADDR(ANC30_CANVAS_ADDR) -#define ANC31_CANVAS_ADDR 0x09af -#define P_ANC31_CANVAS_ADDR DOS_REG_ADDR(ANC31_CANVAS_ADDR) -#define DBKR_CANVAS_ADDR 0x09b0 -#define P_DBKR_CANVAS_ADDR DOS_REG_ADDR(DBKR_CANVAS_ADDR) -#define DBKW_CANVAS_ADDR 0x09b1 -#define P_DBKW_CANVAS_ADDR DOS_REG_ADDR(DBKW_CANVAS_ADDR) -#define REC_CANVAS_ADDR 0x09b2 -#define P_REC_CANVAS_ADDR DOS_REG_ADDR(REC_CANVAS_ADDR) -#define CURR_CANVAS_CTRL 0x09b3 -#define P_CURR_CANVAS_CTRL DOS_REG_ADDR(CURR_CANVAS_CTRL) -#define MDEC_PIC_DC_THRESH 0x09b8 -#define P_MDEC_PIC_DC_THRESH DOS_REG_ADDR(MDEC_PIC_DC_THRESH) -#define MDEC_PICR_BUF_STATUS 0x09b9 -#define P_MDEC_PICR_BUF_STATUS DOS_REG_ADDR(MDEC_PICR_BUF_STATUS) -#define MDEC_PICW_BUF_STATUS 0x09ba -#define P_MDEC_PICW_BUF_STATUS DOS_REG_ADDR(MDEC_PICW_BUF_STATUS) -#define MCW_DBLK_WRRSP_CNT 0x09bb -#define P_MCW_DBLK_WRRSP_CNT DOS_REG_ADDR(MCW_DBLK_WRRSP_CNT) -#define MC_MBBOT_WRRSP_CNT 0x09bc -#define P_MC_MBBOT_WRRSP_CNT DOS_REG_ADDR(MC_MBBOT_WRRSP_CNT) -#define WRRSP_FIFO_PICW_DBK 0x09be -#define P_WRRSP_FIFO_PICW_DBK DOS_REG_ADDR(WRRSP_FIFO_PICW_DBK) -#define WRRSP_FIFO_PICW_MC 0x09bf -#define P_WRRSP_FIFO_PICW_MC DOS_REG_ADDR(WRRSP_FIFO_PICW_MC) -#define AV_SCRATCH_0 0x09c0 -#define P_AV_SCRATCH_0 DOS_REG_ADDR(AV_SCRATCH_0) -#define AV_SCRATCH_1 0x09c1 -#define P_AV_SCRATCH_1 DOS_REG_ADDR(AV_SCRATCH_1) -#define AV_SCRATCH_2 0x09c2 -#define P_AV_SCRATCH_2 DOS_REG_ADDR(AV_SCRATCH_2) -#define AV_SCRATCH_3 0x09c3 -#define P_AV_SCRATCH_3 DOS_REG_ADDR(AV_SCRATCH_3) -#define AV_SCRATCH_4 0x09c4 -#define P_AV_SCRATCH_4 DOS_REG_ADDR(AV_SCRATCH_4) -#define AV_SCRATCH_5 0x09c5 -#define P_AV_SCRATCH_5 DOS_REG_ADDR(AV_SCRATCH_5) -#define AV_SCRATCH_6 0x09c6 -#define P_AV_SCRATCH_6 DOS_REG_ADDR(AV_SCRATCH_6) -#define AV_SCRATCH_7 0x09c7 -#define P_AV_SCRATCH_7 DOS_REG_ADDR(AV_SCRATCH_7) -#define AV_SCRATCH_8 0x09c8 -#define P_AV_SCRATCH_8 DOS_REG_ADDR(AV_SCRATCH_8) -#define AV_SCRATCH_9 0x09c9 -#define P_AV_SCRATCH_9 DOS_REG_ADDR(AV_SCRATCH_9) -#define AV_SCRATCH_A 0x09ca -#define P_AV_SCRATCH_A DOS_REG_ADDR(AV_SCRATCH_A) -#define AV_SCRATCH_B 0x09cb -#define P_AV_SCRATCH_B DOS_REG_ADDR(AV_SCRATCH_B) -#define AV_SCRATCH_C 0x09cc -#define P_AV_SCRATCH_C DOS_REG_ADDR(AV_SCRATCH_C) -#define AV_SCRATCH_D 0x09cd -#define P_AV_SCRATCH_D DOS_REG_ADDR(AV_SCRATCH_D) -#define AV_SCRATCH_E 0x09ce -#define P_AV_SCRATCH_E DOS_REG_ADDR(AV_SCRATCH_E) -#define AV_SCRATCH_F 0x09cf -#define P_AV_SCRATCH_F DOS_REG_ADDR(AV_SCRATCH_F) -#define AV_SCRATCH_G 0x09d0 -#define P_AV_SCRATCH_G DOS_REG_ADDR(AV_SCRATCH_G) -#define AV_SCRATCH_H 0x09d1 -#define P_AV_SCRATCH_H DOS_REG_ADDR(AV_SCRATCH_H) -#define AV_SCRATCH_I 0x09d2 -#define P_AV_SCRATCH_I DOS_REG_ADDR(AV_SCRATCH_I) -#define AV_SCRATCH_J 0x09d3 -#define P_AV_SCRATCH_J DOS_REG_ADDR(AV_SCRATCH_J) -#define AV_SCRATCH_K 0x09d4 -#define P_AV_SCRATCH_K DOS_REG_ADDR(AV_SCRATCH_K) -#define AV_SCRATCH_L 0x09d5 -#define P_AV_SCRATCH_L DOS_REG_ADDR(AV_SCRATCH_L) -#define AV_SCRATCH_M 0x09d6 -#define P_AV_SCRATCH_M DOS_REG_ADDR(AV_SCRATCH_M) -#define AV_SCRATCH_N 0x09d7 -#define P_AV_SCRATCH_N DOS_REG_ADDR(AV_SCRATCH_N) -#define WRRSP_CO_MB 0x09d8 -#define P_WRRSP_CO_MB DOS_REG_ADDR(WRRSP_CO_MB) -#define WRRSP_DCAC 0x09d9 -#define P_WRRSP_DCAC DOS_REG_ADDR(WRRSP_DCAC) -/*add from M8M2*/ -#define WRRSP_VLD 0x09da -#define P_WRRSP_VLD DOS_REG_ADDR(WRRSP_VLD) -#define MDEC_DOUBLEW_CFG0 0x09db -#define P_MDEC_DOUBLEW_CFG0 DOS_REG_ADDR(MDEC_DOUBLEW_CFG0) -#define MDEC_DOUBLEW_CFG1 0x09dc -#define P_MDEC_DOUBLEW_CFG1 DOS_REG_ADDR(MDEC_DOUBLEW_CFG1) -#define MDEC_DOUBLEW_CFG2 0x09dd -#define P_MDEC_DOUBLEW_CFG2 DOS_REG_ADDR(MDEC_DOUBLEW_CFG2) -#define MDEC_DOUBLEW_CFG3 0x09de -#define P_MDEC_DOUBLEW_CFG3 DOS_REG_ADDR(MDEC_DOUBLEW_CFG3) -#define MDEC_DOUBLEW_CFG4 0x09df -#define P_MDEC_DOUBLEW_CFG4 DOS_REG_ADDR(MDEC_DOUBLEW_CFG4) -#define MDEC_DOUBLEW_CFG5 0x09e0 -#define P_MDEC_DOUBLEW_CFG5 DOS_REG_ADDR(MDEC_DOUBLEW_CFG5) -#define MDEC_DOUBLEW_CFG6 0x09e1 -#define P_MDEC_DOUBLEW_CFG6 DOS_REG_ADDR(MDEC_DOUBLEW_CFG6) -#define MDEC_DOUBLEW_CFG7 0x09e2 -#define P_MDEC_DOUBLEW_CFG7 DOS_REG_ADDR(MDEC_DOUBLEW_CFG7) -#define MDEC_DOUBLEW_STATUS 0x09e3 -#define P_MDEC_DOUBLEW_STATUS DOS_REG_ADDR(MDEC_DOUBLEW_STATUS) -/**/ -#define DBLK_RST 0x0950 -#define P_DBLK_RST DOS_REG_ADDR(DBLK_RST) -#define DBLK_CTRL 0x0951 -#define P_DBLK_CTRL DOS_REG_ADDR(DBLK_CTRL) -#define DBLK_MB_WID_HEIGHT 0x0952 -#define P_DBLK_MB_WID_HEIGHT DOS_REG_ADDR(DBLK_MB_WID_HEIGHT) -#define DBLK_STATUS 0x0953 -#define P_DBLK_STATUS DOS_REG_ADDR(DBLK_STATUS) -#define DBLK_CMD_CTRL 0x0954 -#define P_DBLK_CMD_CTRL DOS_REG_ADDR(DBLK_CMD_CTRL) -#define DBLK_MB_XY 0x0955 -#define P_DBLK_MB_XY DOS_REG_ADDR(DBLK_MB_XY) -#define DBLK_QP 0x0956 -#define P_DBLK_QP DOS_REG_ADDR(DBLK_QP) -#define DBLK_Y_BHFILT 0x0957 -#define P_DBLK_Y_BHFILT DOS_REG_ADDR(DBLK_Y_BHFILT) -#define DBLK_Y_BHFILT_HIGH 0x0958 -#define P_DBLK_Y_BHFILT_HIGH DOS_REG_ADDR(DBLK_Y_BHFILT_HIGH) -#define DBLK_Y_BVFILT 0x0959 -#define P_DBLK_Y_BVFILT DOS_REG_ADDR(DBLK_Y_BVFILT) -#define DBLK_CB_BFILT 0x095a -#define P_DBLK_CB_BFILT DOS_REG_ADDR(DBLK_CB_BFILT) -#define DBLK_CR_BFILT 0x095b -#define P_DBLK_CR_BFILT DOS_REG_ADDR(DBLK_CR_BFILT) -#define DBLK_Y_HFILT 0x095c -#define P_DBLK_Y_HFILT DOS_REG_ADDR(DBLK_Y_HFILT) -#define DBLK_Y_HFILT_HIGH 0x095d -#define P_DBLK_Y_HFILT_HIGH DOS_REG_ADDR(DBLK_Y_HFILT_HIGH) -#define DBLK_Y_VFILT 0x095e -#define P_DBLK_Y_VFILT DOS_REG_ADDR(DBLK_Y_VFILT) -#define DBLK_CB_FILT 0x095f -#define P_DBLK_CB_FILT DOS_REG_ADDR(DBLK_CB_FILT) -#define DBLK_CR_FILT 0x0960 -#define P_DBLK_CR_FILT DOS_REG_ADDR(DBLK_CR_FILT) -#define DBLK_BETAX_QP_SEL 0x0961 -#define P_DBLK_BETAX_QP_SEL DOS_REG_ADDR(DBLK_BETAX_QP_SEL) -#define DBLK_CLIP_CTRL0 0x0962 -#define P_DBLK_CLIP_CTRL0 DOS_REG_ADDR(DBLK_CLIP_CTRL0) -#define DBLK_CLIP_CTRL1 0x0963 -#define P_DBLK_CLIP_CTRL1 DOS_REG_ADDR(DBLK_CLIP_CTRL1) -#define DBLK_CLIP_CTRL2 0x0964 -#define P_DBLK_CLIP_CTRL2 DOS_REG_ADDR(DBLK_CLIP_CTRL2) -#define DBLK_CLIP_CTRL3 0x0965 -#define P_DBLK_CLIP_CTRL3 DOS_REG_ADDR(DBLK_CLIP_CTRL3) -#define DBLK_CLIP_CTRL4 0x0966 -#define P_DBLK_CLIP_CTRL4 DOS_REG_ADDR(DBLK_CLIP_CTRL4) -#define DBLK_CLIP_CTRL5 0x0967 -#define P_DBLK_CLIP_CTRL5 DOS_REG_ADDR(DBLK_CLIP_CTRL5) -#define DBLK_CLIP_CTRL6 0x0968 -#define P_DBLK_CLIP_CTRL6 DOS_REG_ADDR(DBLK_CLIP_CTRL6) -#define DBLK_CLIP_CTRL7 0x0969 -#define P_DBLK_CLIP_CTRL7 DOS_REG_ADDR(DBLK_CLIP_CTRL7) -#define DBLK_CLIP_CTRL8 0x096a -#define P_DBLK_CLIP_CTRL8 DOS_REG_ADDR(DBLK_CLIP_CTRL8) -#define DBLK_STATUS1 0x096b -#define P_DBLK_STATUS1 DOS_REG_ADDR(DBLK_STATUS1) -#define DBLK_GCLK_FREE 0x096c -#define P_DBLK_GCLK_FREE DOS_REG_ADDR(DBLK_GCLK_FREE) -#define DBLK_GCLK_OFF 0x096d -#define P_DBLK_GCLK_OFF DOS_REG_ADDR(DBLK_GCLK_OFF) -#define DBLK_AVSFLAGS 0x096e -#define P_DBLK_AVSFLAGS DOS_REG_ADDR(DBLK_AVSFLAGS) -#define DBLK_CBPY 0x0970 -#define P_DBLK_CBPY DOS_REG_ADDR(DBLK_CBPY) -#define DBLK_CBPY_ADJ 0x0971 -#define P_DBLK_CBPY_ADJ DOS_REG_ADDR(DBLK_CBPY_ADJ) -#define DBLK_CBPC 0x0972 -#define P_DBLK_CBPC DOS_REG_ADDR(DBLK_CBPC) -#define DBLK_CBPC_ADJ 0x0973 -#define P_DBLK_CBPC_ADJ DOS_REG_ADDR(DBLK_CBPC_ADJ) -#define DBLK_VHMVD 0x0974 -#define P_DBLK_VHMVD DOS_REG_ADDR(DBLK_VHMVD) -#define DBLK_STRONG 0x0975 -#define P_DBLK_STRONG DOS_REG_ADDR(DBLK_STRONG) -#define DBLK_RV8_QUANT 0x0976 -#define P_DBLK_RV8_QUANT DOS_REG_ADDR(DBLK_RV8_QUANT) -#define DBLK_CBUS_HCMD2 0x0977 -#define P_DBLK_CBUS_HCMD2 DOS_REG_ADDR(DBLK_CBUS_HCMD2) -#define DBLK_CBUS_HCMD1 0x0978 -#define P_DBLK_CBUS_HCMD1 DOS_REG_ADDR(DBLK_CBUS_HCMD1) -#define DBLK_CBUS_HCMD0 0x0979 -#define P_DBLK_CBUS_HCMD0 DOS_REG_ADDR(DBLK_CBUS_HCMD0) -#define DBLK_VLD_HCMD2 0x097a -#define P_DBLK_VLD_HCMD2 DOS_REG_ADDR(DBLK_VLD_HCMD2) -#define DBLK_VLD_HCMD1 0x097b -#define P_DBLK_VLD_HCMD1 DOS_REG_ADDR(DBLK_VLD_HCMD1) -#define DBLK_VLD_HCMD0 0x097c -#define P_DBLK_VLD_HCMD0 DOS_REG_ADDR(DBLK_VLD_HCMD0) -#define DBLK_OST_YBASE 0x097d -#define P_DBLK_OST_YBASE DOS_REG_ADDR(DBLK_OST_YBASE) -#define DBLK_OST_CBCRDIFF 0x097e -#define P_DBLK_OST_CBCRDIFF DOS_REG_ADDR(DBLK_OST_CBCRDIFF) -#define DBLK_CTRL1 0x097f -#define P_DBLK_CTRL1 DOS_REG_ADDR(DBLK_CTRL1) -#define MCRCC_CTL1 0x0980 -#define P_MCRCC_CTL1 DOS_REG_ADDR(MCRCC_CTL1) -#define MCRCC_CTL2 0x0981 -#define P_MCRCC_CTL2 DOS_REG_ADDR(MCRCC_CTL2) -#define MCRCC_CTL3 0x0982 -#define P_MCRCC_CTL3 DOS_REG_ADDR(MCRCC_CTL3) -#define GCLK_EN 0x0983 -#define P_GCLK_EN DOS_REG_ADDR(GCLK_EN) -#define MDEC_SW_RESET 0x0984 -#define P_MDEC_SW_RESET DOS_REG_ADDR(MDEC_SW_RESET) -#define VLD_STATUS_CTRL 0x0c00 -#define P_VLD_STATUS_CTRL DOS_REG_ADDR(VLD_STATUS_CTRL) -#define MPEG1_2_REG 0x0c01 -#define P_MPEG1_2_REG DOS_REG_ADDR(MPEG1_2_REG) -#define F_CODE_REG 0x0c02 -#define P_F_CODE_REG DOS_REG_ADDR(F_CODE_REG) -#define PIC_HEAD_INFO 0x0c03 -#define P_PIC_HEAD_INFO DOS_REG_ADDR(PIC_HEAD_INFO) -#define QP_VALUE_REG 0x0c05 -#define P_QP_VALUE_REG DOS_REG_ADDR(QP_VALUE_REG) -#define MBA_INC 0x0c06 -#define P_MBA_INC DOS_REG_ADDR(MBA_INC) -#define MB_MOTION_MODE 0x0c07 -#define P_MB_MOTION_MODE DOS_REG_ADDR(MB_MOTION_MODE) -#define POWER_CTL_VLD 0x0c08 -#define P_POWER_CTL_VLD DOS_REG_ADDR(POWER_CTL_VLD) -#define MB_WIDTH 0x0c09 -#define P_MB_WIDTH DOS_REG_ADDR(MB_WIDTH) -#define SLICE_QP 0x0c0a -#define P_SLICE_QP DOS_REG_ADDR(SLICE_QP) -#define PRE_START_CODE 0x0c0b -#define P_PRE_START_CODE DOS_REG_ADDR(PRE_START_CODE) -#define SLICE_START_BYTE_01 0x0c0c -#define P_SLICE_START_BYTE_01 DOS_REG_ADDR(SLICE_START_BYTE_01) -#define SLICE_START_BYTE_23 0x0c0d -#define P_SLICE_START_BYTE_23 DOS_REG_ADDR(SLICE_START_BYTE_23) -#define RESYNC_MARKER_LENGTH 0x0c0e -#define P_RESYNC_MARKER_LENGTH DOS_REG_ADDR(RESYNC_MARKER_LENGTH) -#define DECODER_BUFFER_INFO 0x0c0f -#define P_DECODER_BUFFER_INFO DOS_REG_ADDR(DECODER_BUFFER_INFO) -#define FST_FOR_MV_X 0x0c10 -#define P_FST_FOR_MV_X DOS_REG_ADDR(FST_FOR_MV_X) -#define FST_FOR_MV_Y 0x0c11 -#define P_FST_FOR_MV_Y DOS_REG_ADDR(FST_FOR_MV_Y) -#define SCD_FOR_MV_X 0x0c12 -#define P_SCD_FOR_MV_X DOS_REG_ADDR(SCD_FOR_MV_X) -#define SCD_FOR_MV_Y 0x0c13 -#define P_SCD_FOR_MV_Y DOS_REG_ADDR(SCD_FOR_MV_Y) -#define FST_BAK_MV_X 0x0c14 -#define P_FST_BAK_MV_X DOS_REG_ADDR(FST_BAK_MV_X) -#define FST_BAK_MV_Y 0x0c15 -#define P_FST_BAK_MV_Y DOS_REG_ADDR(FST_BAK_MV_Y) -#define SCD_BAK_MV_X 0x0c16 -#define P_SCD_BAK_MV_X DOS_REG_ADDR(SCD_BAK_MV_X) -#define SCD_BAK_MV_Y 0x0c17 -#define P_SCD_BAK_MV_Y DOS_REG_ADDR(SCD_BAK_MV_Y) -#define VLD_DECODE_CONTROL 0x0c18 -#define P_VLD_DECODE_CONTROL DOS_REG_ADDR(VLD_DECODE_CONTROL) -#define VLD_REVERVED_19 0x0c19 -#define P_VLD_REVERVED_19 DOS_REG_ADDR(VLD_REVERVED_19) -#define VIFF_BIT_CNT 0x0c1a -#define P_VIFF_BIT_CNT DOS_REG_ADDR(VIFF_BIT_CNT) -#define BYTE_ALIGN_PEAK_HI 0x0c1b -#define P_BYTE_ALIGN_PEAK_HI DOS_REG_ADDR(BYTE_ALIGN_PEAK_HI) -#define BYTE_ALIGN_PEAK_LO 0x0c1c -#define P_BYTE_ALIGN_PEAK_LO DOS_REG_ADDR(BYTE_ALIGN_PEAK_LO) -#define NEXT_ALIGN_PEAK 0x0c1d -#define P_NEXT_ALIGN_PEAK DOS_REG_ADDR(NEXT_ALIGN_PEAK) -#define VC1_CONTROL_REG 0x0c1e -#define P_VC1_CONTROL_REG DOS_REG_ADDR(VC1_CONTROL_REG) -#define PMV1_X 0x0c20 -#define P_PMV1_X DOS_REG_ADDR(PMV1_X) -#define PMV1_Y 0x0c21 -#define P_PMV1_Y DOS_REG_ADDR(PMV1_Y) -#define PMV2_X 0x0c22 -#define P_PMV2_X DOS_REG_ADDR(PMV2_X) -#define PMV2_Y 0x0c23 -#define P_PMV2_Y DOS_REG_ADDR(PMV2_Y) -#define PMV3_X 0x0c24 -#define P_PMV3_X DOS_REG_ADDR(PMV3_X) -#define PMV3_Y 0x0c25 -#define P_PMV3_Y DOS_REG_ADDR(PMV3_Y) -#define PMV4_X 0x0c26 -#define P_PMV4_X DOS_REG_ADDR(PMV4_X) -#define PMV4_Y 0x0c27 -#define P_PMV4_Y DOS_REG_ADDR(PMV4_Y) -#define M4_TABLE_SELECT 0x0c28 -#define P_M4_TABLE_SELECT DOS_REG_ADDR(M4_TABLE_SELECT) -#define M4_CONTROL_REG 0x0c29 -#define P_M4_CONTROL_REG DOS_REG_ADDR(M4_CONTROL_REG) -#define BLOCK_NUM 0x0c2a -#define P_BLOCK_NUM DOS_REG_ADDR(BLOCK_NUM) -#define PATTERN_CODE 0x0c2b -#define P_PATTERN_CODE DOS_REG_ADDR(PATTERN_CODE) -#define MB_INFO 0x0c2c -#define P_MB_INFO DOS_REG_ADDR(MB_INFO) -#define VLD_DC_PRED 0x0c2d -#define P_VLD_DC_PRED DOS_REG_ADDR(VLD_DC_PRED) -#define VLD_ERROR_MASK 0x0c2e -#define P_VLD_ERROR_MASK DOS_REG_ADDR(VLD_ERROR_MASK) -#define VLD_DC_PRED_C 0x0c2f -#define P_VLD_DC_PRED_C DOS_REG_ADDR(VLD_DC_PRED_C) -#define LAST_SLICE_MV_ADDR 0x0c30 -#define P_LAST_SLICE_MV_ADDR DOS_REG_ADDR(LAST_SLICE_MV_ADDR) -#define LAST_MVX 0x0c31 -#define P_LAST_MVX DOS_REG_ADDR(LAST_MVX) -#define LAST_MVY 0x0c32 -#define P_LAST_MVY DOS_REG_ADDR(LAST_MVY) -#define VLD_C38 0x0c38 -#define P_VLD_C38 DOS_REG_ADDR(VLD_C38) -#define VLD_C39 0x0c39 -#define P_VLD_C39 DOS_REG_ADDR(VLD_C39) -#define VLD_STATUS 0x0c3a -#define P_VLD_STATUS DOS_REG_ADDR(VLD_STATUS) -#define VLD_SHIFT_STATUS 0x0c3b -#define P_VLD_SHIFT_STATUS DOS_REG_ADDR(VLD_SHIFT_STATUS) -#define VOFF_STATUS 0x0c3c -#define P_VOFF_STATUS DOS_REG_ADDR(VOFF_STATUS) -#define VLD_C3D 0x0c3d -#define P_VLD_C3D DOS_REG_ADDR(VLD_C3D) -#define VLD_DBG_INDEX 0x0c3e -#define P_VLD_DBG_INDEX DOS_REG_ADDR(VLD_DBG_INDEX) -#define VLD_DBG_DATA 0x0c3f -#define P_VLD_DBG_DATA DOS_REG_ADDR(VLD_DBG_DATA) -#define VLD_MEM_VIFIFO_START_PTR 0x0c40 -#define P_VLD_TIME_STAMP_0 DOS_REG_ADDR(VLD_TIME_STAMP_0) -#define VLD_TIME_STAMP_1 0x0c4d -#define P_VLD_TIME_STAMP_1 DOS_REG_ADDR(VLD_TIME_STAMP_1) -#define VLD_TIME_STAMP_2 0x0c4e -#define P_VLD_TIME_STAMP_2 DOS_REG_ADDR(VLD_TIME_STAMP_2) -#define VLD_TIME_STAMP_3 0x0c4f -#define P_VLD_TIME_STAMP_3 DOS_REG_ADDR(VLD_TIME_STAMP_3) -#define VLD_MEM_VBUF2_RD_PTR 0x0c54 -#define P_VLD_MEM_VBUF2_RD_PTR DOS_REG_ADDR(VLD_MEM_VBUF2_RD_PTR) -#define VLD_MEM_SWAP_ADDR 0x0c55 -#define P_VLD_MEM_SWAP_ADDR DOS_REG_ADDR(VLD_MEM_SWAP_ADDR) -#define VLD_MEM_SWAP_CTL 0x0c56 -#define P_VLD_MEM_SWAP_CTL DOS_REG_ADDR(VLD_MEM_SWAP_CTL) -#define VCOP_CTRL_REG 0x0e00 -#define P_VCOP_CTRL_REG DOS_REG_ADDR(VCOP_CTRL_REG) -#define QP_CTRL_REG 0x0e01 -#define P_QP_CTRL_REG DOS_REG_ADDR(QP_CTRL_REG) -#define INTRA_QUANT_MATRIX 0x0e02 -#define P_INTRA_QUANT_MATRIX DOS_REG_ADDR(INTRA_QUANT_MATRIX) -#define NON_I_QUANT_MATRIX 0x0e03 -#define P_NON_I_QUANT_MATRIX DOS_REG_ADDR(NON_I_QUANT_MATRIX) -#define DC_SCALER 0x0e04 -#define P_DC_SCALER DOS_REG_ADDR(DC_SCALER) -#define DC_AC_CTRL 0x0e05 -#define P_DC_AC_CTRL DOS_REG_ADDR(DC_AC_CTRL) -#define DC_AC_SCALE_MUL 0x0e06 -#define P_DC_AC_SCALE_MUL DOS_REG_ADDR(DC_AC_SCALE_MUL) -#define DC_AC_SCALE_DIV 0x0e07 -#define P_DC_AC_SCALE_DIV DOS_REG_ADDR(DC_AC_SCALE_DIV) -#define POWER_CTL_IQIDCT 0x0e08 -#define P_POWER_CTL_IQIDCT DOS_REG_ADDR(POWER_CTL_IQIDCT) -#define RV_AI_Y_X 0x0e09 -#define P_RV_AI_Y_X DOS_REG_ADDR(RV_AI_Y_X) -#define RV_AI_U_X 0x0e0a -#define P_RV_AI_U_X DOS_REG_ADDR(RV_AI_U_X) -#define RV_AI_V_X 0x0e0b -#define P_RV_AI_V_X DOS_REG_ADDR(RV_AI_V_X) -#define RV_AI_MB_COUNT 0x0e0c -#define P_RV_AI_MB_COUNT DOS_REG_ADDR(RV_AI_MB_COUNT) -#define IQIDCT_CONTROL 0x0e0e -#define P_IQIDCT_CONTROL DOS_REG_ADDR(IQIDCT_CONTROL) -#define IQIDCT_DEBUG_INFO_0 0x0e0f -#define P_IQIDCT_DEBUG_INFO_0 DOS_REG_ADDR(IQIDCT_DEBUG_INFO_0) -#define DEBLK_CMD 0x0e10 -#define P_DEBLK_CMD DOS_REG_ADDR(DEBLK_CMD) -#define IQIDCT_DEBUG_IDCT 0x0e11 -#define P_IQIDCT_DEBUG_IDCT DOS_REG_ADDR(IQIDCT_DEBUG_IDCT) -#define DCAC_DMA_CTRL 0x0e12 -#define P_DCAC_DMA_CTRL DOS_REG_ADDR(DCAC_DMA_CTRL) -#define DCAC_DMA_ADDRESS 0x0e13 -#define P_DCAC_DMA_ADDRESS DOS_REG_ADDR(DCAC_DMA_ADDRESS) -#define DCAC_CPU_ADDRESS 0x0e14 -#define P_DCAC_CPU_ADDRESS DOS_REG_ADDR(DCAC_CPU_ADDRESS) -#define DCAC_CPU_DATA 0x0e15 -#define P_DCAC_CPU_DATA DOS_REG_ADDR(DCAC_CPU_DATA) -#define DCAC_MB_COUNT 0x0e16 -#define P_DCAC_MB_COUNT DOS_REG_ADDR(DCAC_MB_COUNT) -#define IQ_QUANT 0x0e17 -#define P_IQ_QUANT DOS_REG_ADDR(IQ_QUANT) -#define VC1_BITPLANE_CTL 0x0e18 -#define P_VC1_BITPLANE_CTL DOS_REG_ADDR(VC1_BITPLANE_CTL) -#define MSP 0x0300 -#define P_MSP DOS_REG_ADDR(MSP) -#define MPSR 0x0301 -#define P_MPSR DOS_REG_ADDR(MPSR) -#define MINT_VEC_BASE 0x0302 -#define P_MINT_VEC_BASE DOS_REG_ADDR(MINT_VEC_BASE) -#define MCPU_INTR_GRP 0x0303 -#define P_MCPU_INTR_GRP DOS_REG_ADDR(MCPU_INTR_GRP) -#define MCPU_INTR_MSK 0x0304 -#define P_MCPU_INTR_MSK DOS_REG_ADDR(MCPU_INTR_MSK) -#define MCPU_INTR_REQ 0x0305 -#define P_MCPU_INTR_REQ DOS_REG_ADDR(MCPU_INTR_REQ) -#define MPC_P 0x0306 -#define P_MPC_P DOS_REG_ADDR(MPC_P) -#define MPC_D 0x0307 -#define P_MPC_D DOS_REG_ADDR(MPC_D) -#define MPC_E 0x0308 -#define P_MPC_E DOS_REG_ADDR(MPC_E) -#define MPC_W 0x0309 -#define P_MPC_W DOS_REG_ADDR(MPC_W) -#define MINDEX0_REG 0x030a -#define P_MINDEX0_REG DOS_REG_ADDR(MINDEX0_REG) -#define MINDEX1_REG 0x030b -#define P_MINDEX1_REG DOS_REG_ADDR(MINDEX1_REG) -#define MINDEX2_REG 0x030c -#define P_MINDEX2_REG DOS_REG_ADDR(MINDEX2_REG) -#define MINDEX3_REG 0x030d -#define P_MINDEX3_REG DOS_REG_ADDR(MINDEX3_REG) -#define MINDEX4_REG 0x030e -#define P_MINDEX4_REG DOS_REG_ADDR(MINDEX4_REG) -#define MINDEX5_REG 0x030f -#define P_MINDEX5_REG DOS_REG_ADDR(MINDEX5_REG) -#define MINDEX6_REG 0x0310 -#define P_MINDEX6_REG DOS_REG_ADDR(MINDEX6_REG) -#define MINDEX7_REG 0x0311 -#define P_MINDEX7_REG DOS_REG_ADDR(MINDEX7_REG) -#define MMIN_REG 0x0312 -#define P_MMIN_REG DOS_REG_ADDR(MMIN_REG) -#define MMAX_REG 0x0313 -#define P_MMAX_REG DOS_REG_ADDR(MMAX_REG) -#define MBREAK0_REG 0x0314 -#define P_MBREAK0_REG DOS_REG_ADDR(MBREAK0_REG) -#define MBREAK1_REG 0x0315 -#define P_MBREAK1_REG DOS_REG_ADDR(MBREAK1_REG) -#define MBREAK2_REG 0x0316 -#define P_MBREAK2_REG DOS_REG_ADDR(MBREAK2_REG) -#define MBREAK3_REG 0x0317 -#define P_MBREAK3_REG DOS_REG_ADDR(MBREAK3_REG) -#define MBREAK_TYPE 0x0318 -#define P_MBREAK_TYPE DOS_REG_ADDR(MBREAK_TYPE) -#define MBREAK_CTRL 0x0319 -#define P_MBREAK_CTRL DOS_REG_ADDR(MBREAK_CTRL) -#define MBREAK_STAUTS 0x031a -#define P_MBREAK_STAUTS DOS_REG_ADDR(MBREAK_STAUTS) -#define MDB_ADDR_REG 0x031b -#define P_MDB_ADDR_REG DOS_REG_ADDR(MDB_ADDR_REG) -#define MDB_DATA_REG 0x031c -#define P_MDB_DATA_REG DOS_REG_ADDR(MDB_DATA_REG) -#define MDB_CTRL 0x031d -#define P_MDB_CTRL DOS_REG_ADDR(MDB_CTRL) -#define MSFTINT0 0x031e -#define P_MSFTINT0 DOS_REG_ADDR(MSFTINT0) -#define MSFTINT1 0x031f -#define P_MSFTINT1 DOS_REG_ADDR(MSFTINT1) -#define CSP 0x0320 -#define P_CSP DOS_REG_ADDR(CSP) -#define CPSR 0x0321 -#define P_CPSR DOS_REG_ADDR(CPSR) -#define CINT_VEC_BASE 0x0322 -#define P_CINT_VEC_BASE DOS_REG_ADDR(CINT_VEC_BASE) -#define CCPU_INTR_GRP 0x0323 -#define P_CCPU_INTR_GRP DOS_REG_ADDR(CCPU_INTR_GRP) -#define CCPU_INTR_MSK 0x0324 -#define P_CCPU_INTR_MSK DOS_REG_ADDR(CCPU_INTR_MSK) -#define CCPU_INTR_REQ 0x0325 -#define P_CCPU_INTR_REQ DOS_REG_ADDR(CCPU_INTR_REQ) -#define CPC_P 0x0326 -#define P_CPC_P DOS_REG_ADDR(CPC_P) -#define CPC_D 0x0327 -#define P_CPC_D DOS_REG_ADDR(CPC_D) -#define CPC_E 0x0328 -#define P_CPC_E DOS_REG_ADDR(CPC_E) -#define CPC_W 0x0329 -#define P_CPC_W DOS_REG_ADDR(CPC_W) -#define CINDEX0_REG 0x032a -#define P_CINDEX0_REG DOS_REG_ADDR(CINDEX0_REG) -#define CINDEX1_REG 0x032b -#define P_CINDEX1_REG DOS_REG_ADDR(CINDEX1_REG) -#define CINDEX2_REG 0x032c -#define P_CINDEX2_REG DOS_REG_ADDR(CINDEX2_REG) -#define CINDEX3_REG 0x032d -#define P_CINDEX3_REG DOS_REG_ADDR(CINDEX3_REG) -#define CINDEX4_REG 0x032e -#define P_CINDEX4_REG DOS_REG_ADDR(CINDEX4_REG) -#define CINDEX5_REG 0x032f -#define P_CINDEX5_REG DOS_REG_ADDR(CINDEX5_REG) -#define CINDEX6_REG 0x0330 -#define P_CINDEX6_REG DOS_REG_ADDR(CINDEX6_REG) -#define CINDEX7_REG 0x0331 -#define P_CINDEX7_REG DOS_REG_ADDR(CINDEX7_REG) -#define CMIN_REG 0x0332 -#define P_CMIN_REG DOS_REG_ADDR(CMIN_REG) -#define CMAX_REG 0x0333 -#define P_CMAX_REG DOS_REG_ADDR(CMAX_REG) -#define CBREAK0_REG 0x0334 -#define P_CBREAK0_REG DOS_REG_ADDR(CBREAK0_REG) -#define CBREAK1_REG 0x0335 -#define P_CBREAK1_REG DOS_REG_ADDR(CBREAK1_REG) -#define CBREAK2_REG 0x0336 -#define P_CBREAK2_REG DOS_REG_ADDR(CBREAK2_REG) -#define CBREAK3_REG 0x0337 -#define P_CBREAK3_REG DOS_REG_ADDR(CBREAK3_REG) -#define CBREAK_TYPE 0x0338 -#define P_CBREAK_TYPE DOS_REG_ADDR(CBREAK_TYPE) -#define CBREAK_CTRL 0x0339 -#define P_CBREAK_CTRL DOS_REG_ADDR(CBREAK_CTRL) -#define CBREAK_STAUTS 0x033a -#define P_CBREAK_STAUTS DOS_REG_ADDR(CBREAK_STAUTS) -#define CDB_ADDR_REG 0x033b -#define P_CDB_ADDR_REG DOS_REG_ADDR(CDB_ADDR_REG) -#define CDB_DATA_REG 0x033c -#define P_CDB_DATA_REG DOS_REG_ADDR(CDB_DATA_REG) -#define CDB_CTRL 0x033d -#define P_CDB_CTRL DOS_REG_ADDR(CDB_CTRL) -#define CSFTINT0 0x033e -#define P_CSFTINT0 DOS_REG_ADDR(CSFTINT0) -#define CSFTINT1 0x033f -#define P_CSFTINT1 DOS_REG_ADDR(CSFTINT1) -#define IMEM_DMA_CTRL 0x0340 -#define P_IMEM_DMA_CTRL DOS_REG_ADDR(IMEM_DMA_CTRL) -#define IMEM_DMA_ADR 0x0341 -#define P_IMEM_DMA_ADR DOS_REG_ADDR(IMEM_DMA_ADR) -#define IMEM_DMA_COUNT 0x0342 -#define P_IMEM_DMA_COUNT DOS_REG_ADDR(IMEM_DMA_COUNT) -#define WRRSP_IMEM 0x0343 -#define P_WRRSP_IMEM DOS_REG_ADDR(WRRSP_IMEM) -#define LMEM_DMA_CTRL 0x0350 -#define P_LMEM_DMA_CTRL DOS_REG_ADDR(LMEM_DMA_CTRL) -#define LMEM_DMA_ADR 0x0351 -#define P_LMEM_DMA_ADR DOS_REG_ADDR(LMEM_DMA_ADR) -#define LMEM_DMA_COUNT 0x0352 -#define P_LMEM_DMA_COUNT DOS_REG_ADDR(LMEM_DMA_COUNT) -#define WRRSP_LMEM 0x0353 -#define P_WRRSP_LMEM DOS_REG_ADDR(WRRSP_LMEM) -#define MAC_CTRL1 0x0360 -#define P_MAC_CTRL1 DOS_REG_ADDR(MAC_CTRL1) -#define ACC0REG1 0x0361 -#define P_ACC0REG1 DOS_REG_ADDR(ACC0REG1) -#define ACC1REG1 0x0362 -#define P_ACC1REG1 DOS_REG_ADDR(ACC1REG1) -#define MAC_CTRL2 0x0370 -#define P_MAC_CTRL2 DOS_REG_ADDR(MAC_CTRL2) -#define ACC0REG2 0x0371 -#define P_ACC0REG2 DOS_REG_ADDR(ACC0REG2) -#define ACC1REG2 0x0372 -#define P_ACC1REG2 DOS_REG_ADDR(ACC1REG2) -#define CPU_TRACE 0x0380 -#define P_CPU_TRACE DOS_REG_ADDR(CPU_TRACE) -#define HENC_SCRATCH_0 0x1ac0 -#define P_HENC_SCRATCH_0 DOS_REG_ADDR(HENC_SCRATCH_0) -#define HENC_SCRATCH_1 0x1ac1 -#define P_HENC_SCRATCH_1 DOS_REG_ADDR(HENC_SCRATCH_1) -#define HENC_SCRATCH_2 0x1ac2 -#define P_HENC_SCRATCH_2 DOS_REG_ADDR(HENC_SCRATCH_2) -#define HENC_SCRATCH_3 0x1ac3 -#define P_HENC_SCRATCH_3 DOS_REG_ADDR(HENC_SCRATCH_3) -#define HENC_SCRATCH_4 0x1ac4 -#define P_HENC_SCRATCH_4 DOS_REG_ADDR(HENC_SCRATCH_4) -#define HENC_SCRATCH_5 0x1ac5 -#define P_HENC_SCRATCH_5 DOS_REG_ADDR(HENC_SCRATCH_5) -#define HENC_SCRATCH_6 0x1ac6 -#define P_HENC_SCRATCH_6 DOS_REG_ADDR(HENC_SCRATCH_6) -#define HENC_SCRATCH_7 0x1ac7 -#define P_HENC_SCRATCH_7 DOS_REG_ADDR(HENC_SCRATCH_7) -#define HENC_SCRATCH_8 0x1ac8 -#define P_HENC_SCRATCH_8 DOS_REG_ADDR(HENC_SCRATCH_8) -#define HENC_SCRATCH_9 0x1ac9 -#define P_HENC_SCRATCH_9 DOS_REG_ADDR(HENC_SCRATCH_9) -#define HENC_SCRATCH_A 0x1aca -#define P_HENC_SCRATCH_A DOS_REG_ADDR(HENC_SCRATCH_A) -#define HENC_SCRATCH_B 0x1acb -#define P_HENC_SCRATCH_B DOS_REG_ADDR(HENC_SCRATCH_B) -#define HENC_SCRATCH_C 0x1acc -#define P_HENC_SCRATCH_C DOS_REG_ADDR(HENC_SCRATCH_C) -#define HENC_SCRATCH_D 0x1acd -#define P_HENC_SCRATCH_D DOS_REG_ADDR(HENC_SCRATCH_D) -#define HENC_SCRATCH_E 0x1ace -#define P_HENC_SCRATCH_E DOS_REG_ADDR(HENC_SCRATCH_E) -#define HENC_SCRATCH_F 0x1acf -#define P_HENC_SCRATCH_F DOS_REG_ADDR(HENC_SCRATCH_F) -#define HENC_SCRATCH_G 0x1ad0 -#define P_HENC_SCRATCH_G DOS_REG_ADDR(HENC_SCRATCH_G) -#define HENC_SCRATCH_H 0x1ad1 -#define P_HENC_SCRATCH_H DOS_REG_ADDR(HENC_SCRATCH_H) -#define HENC_SCRATCH_I 0x1ad2 -#define P_HENC_SCRATCH_I DOS_REG_ADDR(HENC_SCRATCH_I) -#define HENC_SCRATCH_J 0x1ad3 -#define P_HENC_SCRATCH_J DOS_REG_ADDR(HENC_SCRATCH_J) -#define HENC_SCRATCH_K 0x1ad4 -#define P_HENC_SCRATCH_K DOS_REG_ADDR(HENC_SCRATCH_K) -#define HENC_SCRATCH_L 0x1ad5 -#define P_HENC_SCRATCH_L DOS_REG_ADDR(HENC_SCRATCH_L) -#define HENC_SCRATCH_M 0x1ad6 -#define P_HENC_SCRATCH_M DOS_REG_ADDR(HENC_SCRATCH_M) -#define HENC_SCRATCH_N 0x1ad7 -#define P_HENC_SCRATCH_N DOS_REG_ADDR(HENC_SCRATCH_N) -#define VLC_STATUS_CTRL 0x1d00 -#define P_VLC_STATUS_CTRL DOS_REG_ADDR(VLC_STATUS_CTRL) -#define VLC_CONFIG 0x1d01 -#define P_VLC_CONFIG DOS_REG_ADDR(VLC_CONFIG) -#define VLC_VB_START_PTR 0x1d10 -#define P_VLC_VB_START_PTR DOS_REG_ADDR(VLC_VB_START_PTR) -#define VLC_VB_END_PTR 0x1d11 -#define P_VLC_VB_END_PTR DOS_REG_ADDR(VLC_VB_END_PTR) -#define VLC_VB_WR_PTR 0x1d12 -#define P_VLC_VB_WR_PTR DOS_REG_ADDR(VLC_VB_WR_PTR) -#define VLC_VB_RD_PTR 0x1d13 -#define P_VLC_VB_RD_PTR DOS_REG_ADDR(VLC_VB_RD_PTR) -#define VLC_VB_SW_RD_PTR 0x1d14 -#define P_VLC_VB_SW_RD_PTR DOS_REG_ADDR(VLC_VB_SW_RD_PTR) -#define VLC_VB_LEFT 0x1d15 -#define P_VLC_VB_LEFT DOS_REG_ADDR(VLC_VB_LEFT) -#define VLC_VB_CONTROL 0x1d16 -#define P_VLC_VB_CONTROL DOS_REG_ADDR(VLC_VB_CONTROL) -#define VLC_VB_MEM_CTL 0x1d17 -#define P_VLC_VB_MEM_CTL DOS_REG_ADDR(VLC_VB_MEM_CTL) -#define VLC_VB_INT_PTR 0x1d18 -#define P_VLC_VB_INT_PTR DOS_REG_ADDR(VLC_VB_INT_PTR) -#define VLC_WRRSP 0x1d19 -#define P_VLC_WRRSP DOS_REG_ADDR(VLC_WRRSP) -#define VLC_TOTAL_BYTES 0x1d1a -#define P_VLC_TOTAL_BYTES DOS_REG_ADDR(VLC_TOTAL_BYTES) -#define VLC_VB_BUFF 0x1d1b -#define P_VLC_VB_BUFF DOS_REG_ADDR(VLC_VB_BUFF) -#define VLC_VB_PRE_BUFF_HI 0x1d1c -#define P_VLC_VB_PRE_BUFF_HI DOS_REG_ADDR(VLC_VB_PRE_BUFF_HI) -#define VLC_VB_PRE_BUFF_LOW 0x1d1d -#define P_VLC_VB_PRE_BUFF_LOW DOS_REG_ADDR(VLC_VB_PRE_BUFF_LOW) -#define VLC_STREAM_BUFF 0x1d1e -#define P_VLC_STREAM_BUFF DOS_REG_ADDR(VLC_STREAM_BUFF) -#define VLC_PUSH_STREAM 0x1d1f -#define P_VLC_PUSH_STREAM DOS_REG_ADDR(VLC_PUSH_STREAM) -#define VLC_PUSH_ELEMENT 0x1d20 -#define P_VLC_PUSH_ELEMENT DOS_REG_ADDR(VLC_PUSH_ELEMENT) -#define VLC_ELEMENT_DATA 0x1d21 -#define P_VLC_ELEMENT_DATA DOS_REG_ADDR(VLC_ELEMENT_DATA) -/*add from M8M2*/ -#define VLC_SPECIAL_CTL 0x1d22 -#define P_VLC_SPECIAL_CTL DOS_REG_ADDR(VLC_SPECIAL_CTL) -#define VLC_HCMD_T_L_INFO 0x1d23 -#define P_VLC_HCMD_T_L_INFO DOS_REG_ADDR(VLC_HCMD_T_L_INFO) -#define VLC_HCMD_CUR_INFO 0x1d24 -#define P_VLC_HCMD_CUR_INFO DOS_REG_ADDR(VLC_HCMD_CUR_INFO) -/**/ -#define IE_CONTROL 0x1f40 -#define P_IE_CONTROL DOS_REG_ADDR(IE_CONTROL) -#define IE_MB_POSITION 0x1f41 -#define P_IE_MB_POSITION DOS_REG_ADDR(IE_MB_POSITION) -#define IE_ME_MB_INFO 0x1f42 -#define P_IE_ME_MB_INFO DOS_REG_ADDR(IE_ME_MB_INFO) -#define SAD_CONTROL 0x1f43 -#define P_SAD_CONTROL DOS_REG_ADDR(SAD_CONTROL) -#define IE_RESULT_BUFFER 0x1f44 -#define P_IE_RESULT_BUFFER DOS_REG_ADDR(IE_RESULT_BUFFER) -#define IE_I4_PRED_MODE_HI 0x1f45 -#define P_IE_I4_PRED_MODE_HI DOS_REG_ADDR(IE_I4_PRED_MODE_HI) -#define IE_I4_PRED_MODE_LO 0x1f46 -#define P_IE_I4_PRED_MODE_LO DOS_REG_ADDR(IE_I4_PRED_MODE_LO) -#define IE_C_PRED_MODE 0x1f47 -#define P_IE_C_PRED_MODE DOS_REG_ADDR(IE_C_PRED_MODE) -#define IE_CUR_REF_SEL 0x1f48 -#define P_IE_CUR_REF_SEL DOS_REG_ADDR(IE_CUR_REF_SEL) -#define ME_CONTROL 0x1f49 -#define P_ME_CONTROL DOS_REG_ADDR(ME_CONTROL) -#define ME_START_POSITION 0x1f4a -#define P_ME_START_POSITION DOS_REG_ADDR(ME_START_POSITION) -#define ME_STATUS 0x1f4b -#define P_ME_STATUS DOS_REG_ADDR(ME_STATUS) -#define ME_DEBUG 0x1f4c -#define P_ME_DEBUG DOS_REG_ADDR(ME_DEBUG) -#define ME_SKIP_LINE 0x1f4d -#define P_ME_SKIP_LINE DOS_REG_ADDR(ME_SKIP_LINE) -#define ME_AB_MEM_CTL 0x1f4e -#define P_ME_AB_MEM_CTL DOS_REG_ADDR(ME_AB_MEM_CTL) -#define ME_PIC_INFO 0x1f4f -#define P_ME_PIC_INFO DOS_REG_ADDR(ME_PIC_INFO) -#define ME_SAD_ENOUGH_01 0x1f50 -#define P_ME_SAD_ENOUGH_01 DOS_REG_ADDR(ME_SAD_ENOUGH_01) -#define ME_SAD_ENOUGH_23 0x1f51 -#define P_ME_SAD_ENOUGH_23 DOS_REG_ADDR(ME_SAD_ENOUGH_23) -#define ME_STEP0_CLOSE_MV 0x1f52 -#define P_ME_STEP0_CLOSE_MV DOS_REG_ADDR(ME_STEP0_CLOSE_MV) -#define ME_F_SKIP_SAD 0x1f53 -#define P_ME_F_SKIP_SAD DOS_REG_ADDR(ME_F_SKIP_SAD) -#define ME_F_SKIP_WEIGHT 0x1f54 -#define P_ME_F_SKIP_WEIGHT DOS_REG_ADDR(ME_F_SKIP_WEIGHT) -#define ME_MV_MERGE_CTL 0x1f55 -#define P_ME_MV_MERGE_CTL DOS_REG_ADDR(ME_MV_MERGE_CTL) -#define ME_MV_WEIGHT_01 0x1f56 -#define P_ME_MV_WEIGHT_01 DOS_REG_ADDR(ME_MV_WEIGHT_01) -#define ME_MV_WEIGHT_23 0x1f57 -#define P_ME_MV_WEIGHT_23 DOS_REG_ADDR(ME_MV_WEIGHT_23) -#define ME_SAD_RANGE_INC 0x1f58 -#define P_ME_SAD_RANGE_INC DOS_REG_ADDR(ME_SAD_RANGE_INC) -#define ME_SUB_MERGE_CTL 0x1f59 -#define P_ME_SUB_MERGE_CTL DOS_REG_ADDR(ME_SUB_MERGE_CTL) -#define ME_SUB_REF_MV_CTL 0x1f5a -#define P_ME_SUB_REF_MV_CTL DOS_REG_ADDR(ME_SUB_REF_MV_CTL) -#define ME_SUB_FIX_SAD 0x1f5c -#define P_ME_SUB_FIX_SAD DOS_REG_ADDR(ME_SUB_FIX_SAD) -#define ME_SUB_FIX_MIN_SAD 0x1f5d -#define P_ME_SUB_FIX_MIN_SAD DOS_REG_ADDR(ME_SUB_FIX_MIN_SAD) -#define ME_SUB_SNAP_GLITCH 0x1f5e -#define P_ME_SUB_SNAP_GLITCH DOS_REG_ADDR(ME_SUB_SNAP_GLITCH) -#define ME_SUB_ACT_CTL 0x1f5f -#define P_ME_SUB_ACT_CTL DOS_REG_ADDR(ME_SUB_ACT_CTL) -/*add from M8M2*/ -#define HEVC_ASSIST_GCLK_EN 0x3003 -#define P_HEVC_ASSIST_GCLK_EN DOS_REG_ADDR(HEVC_ASSIST_GCLK_EN) -#define HEVC_ASSIST_SW_RESET 0x3004 -#define P_HEVC_ASSIST_SW_RESET DOS_REG_ADDR(HEVC_ASSIST_SW_RESET) -#define HEVC_ASSIST_AMR1_INT0 0x3025 -#define HEVC_ASSIST_DMA_INT2 0x3066 -#define P_HEVC_ASSIST_DMA_INT2 DOS_REG_ADDR(HEVC_ASSIST_DMA_INT2) -#define HEVC_PARSER_VERSION 0x3100 -#define P_HEVC_PARSER_VERSION DOS_REG_ADDR(HEVC_PARSER_VERSION) -#define HEVC_STREAM_CONTROL 0x3101 -#define P_HEVC_STREAM_CONTROL DOS_REG_ADDR(HEVC_STREAM_CONTROL) -#define HEVC_STREAM_END_ADDR 0x3103 -#define P_HEVC_STREAM_END_ADDR DOS_REG_ADDR(HEVC_STREAM_END_ADDR) -#define HEVC_STREAM_WR_PTR 0x3104 -#define P_HEVC_STREAM_WR_PTR DOS_REG_ADDR(HEVC_STREAM_WR_PTR) -#define HEVC_STREAM_RD_PTR 0x3105 -#define P_HEVC_STREAM_RD_PTR DOS_REG_ADDR(HEVC_STREAM_RD_PTR) -#define HEVC_STREAM_LEVEL 0x3106 -#define P_HEVC_STREAM_LEVEL DOS_REG_ADDR(HEVC_STREAM_LEVEL) -#define HEVC_STREAM_FIFO_CTL 0x3107 -#define P_HEVC_STREAM_FIFO_CTL DOS_REG_ADDR(HEVC_STREAM_FIFO_CTL) -#define HEVC_SHIFT_CONTROL 0x3108 -#define P_HEVC_SHIFT_CONTROL DOS_REG_ADDR(HEVC_SHIFT_CONTROL) -#define HEVC_SHIFT_STARTCODE 0x3109 -#define P_HEVC_SHIFT_STARTCODE DOS_REG_ADDR(HEVC_SHIFT_STARTCODE) -#define HEVC_SHIFT_STATUS 0x310b -#define P_HEVC_SHIFT_STATUS DOS_REG_ADDR(HEVC_SHIFT_STATUS) -#define HEVC_SHIFTED_DATA 0x310c -#define P_HEVC_SHIFTED_DATA DOS_REG_ADDR(HEVC_SHIFTED_DATA) -#define HEVC_PARSER_RESULT_0 0x3118 -#define P_HEVC_PARSER_RESULT_0 DOS_REG_ADDR(HEVC_PARSER_RESULT_0) -#define HEVC_PARSER_RESULT_1 0x3119 -#define P_HEVC_PARSER_RESULT_1 DOS_REG_ADDR(HEVC_PARSER_RESULT_1) -#define HEVC_PARSER_RESULT_2 0x311a -#define P_HEVC_PARSER_RESULT_2 DOS_REG_ADDR(HEVC_PARSER_RESULT_2) -#define HEVC_PARSER_RESULT_3 0x311b -#define P_HEVC_PARSER_RESULT_3 DOS_REG_ADDR(HEVC_PARSER_RESULT_3) -#define HEVC_CABAC_TOP_INFO 0x311c -#define P_HEVC_CABAC_TOP_INFO DOS_REG_ADDR(HEVC_CABAC_TOP_INFO) -#define HEVC_SAO_IF_STATUS 0x3130 -#define P_HEVC_SAO_IF_STATUS DOS_REG_ADDR(HEVC_SAO_IF_STATUS) -#define HEVC_SAO_IF_DATA_Y 0x3131 -#define P_HEVC_SAO_IF_DATA_Y DOS_REG_ADDR(HEVC_SAO_IF_DATA_Y) -#define HEVC_SAO_IF_DATA_U 0x3132 -#define P_HEVC_SAO_IF_DATA_U DOS_REG_ADDR(HEVC_SAO_IF_DATA_U) -#define HEVC_SAO_IF_DATA_V 0x3133 -#define P_HEVC_SAO_IF_DATA_V DOS_REG_ADDR(HEVC_SAO_IF_DATA_V) -#define HEVC_STREAM_SWAP_ADDR 0x3134 -#define HEVC_MPRED_VERSION 0x3200 -#define P_HEVC_MPRED_VERSION DOS_REG_ADDR(HEVC_MPRED_VERSION) -#define HEVC_MPRED_CTRL0 0x3201 -#define P_HEVC_MPRED_CTRL0 DOS_REG_ADDR(HEVC_MPRED_CTRL0) -#define HEVC_MPRED_CTRL1 0x3202 -#define P_HEVC_MPRED_CTRL1 DOS_REG_ADDR(HEVC_MPRED_CTRL1) -#define HEVC_MPRED_INT_EN 0x3203 -#define P_HEVC_MPRED_INT_EN DOS_REG_ADDR(HEVC_MPRED_INT_EN) -#define HEVC_MPRED_INT_STATUS 0x3204 - -#define HEVC_MPRED_REF_NUM 0x3209 -#define P_HEVC_MPRED_REF_NUM DOS_REG_ADDR(HEVC_MPRED_REF_NUM) -#define HEVC_MPRED_LT_REF 0x320a -#define P_HEVC_MPRED_LT_REF DOS_REG_ADDR(HEVC_MPRED_LT_REF) -#define HEVC_MPRED_LT_COLREF 0x320b -#define P_HEVC_MPRED_LT_COLREF DOS_REG_ADDR(HEVC_MPRED_LT_COLREF) -#define HEVC_MPRED_REF_EN_L0 0x320c -#define P_HEVC_MPRED_REF_EN_L0 DOS_REG_ADDR(HEVC_MPRED_REF_EN_L0) -#define HEVC_MPRED_REF_EN_L1 0x320d -#define P_HEVC_MPRED_REF_EN_L1 DOS_REG_ADDR(HEVC_MPRED_REF_EN_L1) -#define HEVC_MPRED_CURR_LCU 0x3219 -#define P_HEVC_MPRED_CURR_LCU DOS_REG_ADDR(HEVC_MPRED_CURR_LCU) -#define HEVC_MPRED_ABV_WPTR 0x321a -#define P_HEVC_MPRED_ABV_WPTR DOS_REG_ADDR(HEVC_MPRED_ABV_WPTR) -#define HEVC_MPRED_ABV_RPTR 0x321b -#define P_HEVC_MPRED_ABV_RPTR DOS_REG_ADDR(HEVC_MPRED_ABV_RPTR) -#define HEVC_MPRED_CTRL2 0x321c -#define P_HEVC_MPRED_CTRL2 DOS_REG_ADDR(HEVC_MPRED_CTRL2) -#define HEVC_MPRED_CTRL3 0x321d -#define P_HEVC_MPRED_CTRL3 DOS_REG_ADDR(HEVC_MPRED_CTRL3) -#define HEVC_MPRED_MV_WLCUY 0x321e -#define P_HEVC_MPRED_MV_WLCUY DOS_REG_ADDR(HEVC_MPRED_MV_WLCUY) -#define HEVC_MPRED_MV_RLCUY 0x321f -#define P_HEVC_MPRED_MV_RLCUY DOS_REG_ADDR(HEVC_MPRED_MV_RLCUY) - -#define HEVC_MPRED_DBG_MODE0 0x3241 -#define P_HEVC_MPRED_DBG_MODE0 DOS_REG_ADDR(HEVC_MPRED_DBG_MODE0) -#define HEVC_MPRED_DBG_MODE1 0x3242 -#define P_HEVC_MPRED_DBG_MODE1 DOS_REG_ADDR(HEVC_MPRED_DBG_MODE1) -#define HEVC_MPRED_DBG2_MODE 0x3243 -#define P_HEVC_MPRED_DBG2_MODE DOS_REG_ADDR(HEVC_MPRED_DBG2_MODE) -#define HEVC_MPRED_IMP_CMD0 0x3244 -#define P_HEVC_MPRED_IMP_CMD0 DOS_REG_ADDR(HEVC_MPRED_IMP_CMD0) -#define HEVC_MPRED_IMP_CMD1 0x3245 -#define P_HEVC_MPRED_IMP_CMD1 DOS_REG_ADDR(HEVC_MPRED_IMP_CMD1) -#define HEVC_MPRED_IMP_CMD2 0x3246 -#define P_HEVC_MPRED_IMP_CMD2 DOS_REG_ADDR(HEVC_MPRED_IMP_CMD2) -#define HEVC_MPRED_IMP_CMD3 0x3247 -#define P_HEVC_MPRED_IMP_CMD3 DOS_REG_ADDR(HEVC_MPRED_IMP_CMD3) -#define HEVCD_IPP_TOP_LCUCONFIG 0x3406 -#define P_HEVC_DBLK_CFG0 DOS_REG_ADDR(HEVC_DBLK_CFG0) -#define HEVC_DBLK_CFG1 0x3501 -#define P_HEVC_DBLK_CFG1 DOS_REG_ADDR(HEVC_DBLK_CFG1) -#define HEVC_DBLK_CFG2 0x3502 -#define P_HEVC_DBLK_CFG2 DOS_REG_ADDR(HEVC_DBLK_CFG2) -#define HEVC_DBLK_CFG3 0x3503 -#define P_HEVC_DBLK_CFG3 DOS_REG_ADDR(HEVC_DBLK_CFG3) -#define HEVC_DBLK_CFG4 0x3504 -#define P_HEVC_DBLK_CFG4 DOS_REG_ADDR(HEVC_DBLK_CFG4) -#define HEVC_DBLK_CFG5 0x3505 -#define P_HEVC_DBLK_CFG5 DOS_REG_ADDR(HEVC_DBLK_CFG5) -#define HEVC_DBLK_CFG6 0x3506 -#define P_HEVC_DBLK_CFG6 DOS_REG_ADDR(HEVC_DBLK_CFG6) -#define HEVC_DBLK_CFG7 0x3507 -#define P_HEVC_DBLK_CFG7 DOS_REG_ADDR(HEVC_DBLK_CFG7) -#define HEVC_DBLK_CFG8 0x3508 -#define P_HEVC_DBLK_CFG8 DOS_REG_ADDR(HEVC_DBLK_CFG8) -#define HEVC_DBLK_CFG9 0x3509 -#define P_HEVC_DBLK_CFG9 DOS_REG_ADDR(HEVC_DBLK_CFG9) -#define HEVC_DBLK_CFGA 0x350a -#define P_HEVC_DBLK_CFGA DOS_REG_ADDR(HEVC_DBLK_CFGA) -#define HEVC_DBLK_STS0 0x350b -#define P_HEVC_DBLK_STS0 DOS_REG_ADDR(HEVC_DBLK_STS0) -#define HEVC_DBLK_STS1 0x350c -#define P_HEVC_DBLK_STS1 DOS_REG_ADDR(HEVC_DBLK_STS1) -#define HEVC_SAO_VERSION 0x3600 -#define P_HEVC_SAO_VERSION DOS_REG_ADDR(HEVC_SAO_VERSION) -#define HEVC_SAO_CTRL0 0x3601 -#define P_HEVC_SAO_CTRL0 DOS_REG_ADDR(HEVC_SAO_CTRL0) -#define HEVC_SAO_CTRL1 0x3602 -#define P_HEVC_SAO_CTRL1 DOS_REG_ADDR(HEVC_SAO_CTRL1) -#define HEVC_SAO_INT_EN 0x3603 -#define P_HEVC_SAO_INT_EN DOS_REG_ADDR(HEVC_SAO_INT_EN) -#define HEVC_SAO_INT_STATUS 0x3604 -#define P_HEVC_SAO_INT_STATUS DOS_REG_ADDR(HEVC_SAO_INT_STATUS) - -#define HEVC_SAO_TILE_START 0x3607 -#define P_HEVC_SAO_TILE_START DOS_REG_ADDR(HEVC_SAO_TILE_START) -#define HEVC_SAO_AXI_WCTRL 0x3609 -#define P_HEVC_SAO_AXI_WCTRL DOS_REG_ADDR(HEVC_SAO_AXI_WCTRL) -#define HEVC_SAO_AXI_RCTRL 0x360a -#define P_HEVC_SAO_AXI_RCTRL DOS_REG_ADDR(HEVC_SAO_AXI_RCTRL) - -#define HEVC_SAO_ABV_WPTR 0x3614 -#define P_HEVC_SAO_ABV_WPTR DOS_REG_ADDR(HEVC_SAO_ABV_WPTR) -#define HEVC_SAO_ABV_RPTR 0x3615 -#define P_HEVC_SAO_ABV_RPTR DOS_REG_ADDR(HEVC_SAO_ABV_RPTR) -#define HEVC_SAO_VB_WPTR 0x3616 -#define P_HEVC_SAO_VB_WPTR DOS_REG_ADDR(HEVC_SAO_VB_WPTR) -#define HEVC_SAO_VB_RPTR 0x3617 -#define P_HEVC_SAO_VB_RPTR DOS_REG_ADDR(HEVC_SAO_VB_RPTR) -#define HEVC_SAO_DBG_MODE0 0x361e -#define P_HEVC_SAO_DBG_MODE0 DOS_REG_ADDR(HEVC_SAO_DBG_MODE0) -#define HEVC_SAO_DBG_MODE1 0x361f -#define P_HEVC_SAO_DBG_MODE1 DOS_REG_ADDR(HEVC_SAO_DBG_MODE1) -#define HEVC_SAO_CTRL2 0x3620 -#define P_HEVC_SAO_CTRL2 DOS_REG_ADDR(HEVC_SAO_CTRL2) -#define HEVC_SAO_CTRL3 0x3621 -#define P_HEVC_SAO_CTRL3 DOS_REG_ADDR(HEVC_SAO_CTRL3) -#define HEVC_SAO_CTRL4 0x3622 -#define P_HEVC_SAO_CTRL4 DOS_REG_ADDR(HEVC_SAO_CTRL4) -#define HEVC_SAO_CTRL5 0x3623 -#define P_HEVC_SAO_CTRL5 DOS_REG_ADDR(HEVC_SAO_CTRL5) -#define HEVC_SAO_CTRL6 0x3624 -#define P_HEVC_SAO_CTRL6 DOS_REG_ADDR(HEVC_SAO_CTRL6) -#define HEVC_SAO_CTRL7 0x3625 -#define P_HEVC_SAO_CTRL7 DOS_REG_ADDR(HEVC_SAO_CTRL7) -#define HEVC_SAO_DBG_DATA_0 0x3630 -#define P_HEVC_SAO_DBG_DATA_0 DOS_REG_ADDR(HEVC_SAO_DBG_DATA_0) -#define HEVC_SAO_DBG_DATA_1 0x3631 -#define P_HEVC_SAO_DBG_DATA_1 DOS_REG_ADDR(HEVC_SAO_DBG_DATA_1) -#define HEVC_SAO_DBG_DATA_2 0x3632 -#define P_HEVC_SAO_DBG_DATA_2 DOS_REG_ADDR(HEVC_SAO_DBG_DATA_2) -#define HEVC_SAO_DBG_DATA_3 0x3633 -#define P_HEVC_SAO_DBG_DATA_3 DOS_REG_ADDR(HEVC_SAO_DBG_DATA_3) -#define HEVC_SAO_DBG_DATA_4 0x3634 -#define P_HEVC_SAO_DBG_DATA_4 DOS_REG_ADDR(HEVC_SAO_DBG_DATA_4) -#define HEVC_SAO_DBG_DATA_5 0x3635 -#define P_HEVC_SAO_DBG_DATA_5 DOS_REG_ADDR(HEVC_SAO_DBG_DATA_5) -#define HEVC_SAO_DBG_DATA_6 0x3636 -#define P_HEVC_SAO_DBG_DATA_6 DOS_REG_ADDR(HEVC_SAO_DBG_DATA_6) -#define HEVC_IQIT_STAT_GEN0 0x3708 -#define P_HEVC_IQIT_STAT_GEN0 DOS_REG_ADDR(HEVC_IQIT_STAT_GEN0) -#define HEVC_QP_WRITE 0x3709 -#define P_HEVC_QP_WRITE DOS_REG_ADDR(HEVC_QP_WRITE) -#define HEVC_IQIT_STAT_GEN1 0x370a -#define P_HEVC_IQIT_STAT_GEN1 DOS_REG_ADDR(HEVC_IQIT_STAT_GEN1) -/**/ -#define DOS_SW_RESET0 0x3f00 -#define P_DOS_SW_RESET0 DOS_REG_ADDR(DOS_SW_RESET0) -#define DOS_GCLK_EN0 0x3f01 -#define P_DOS_GCLK_EN0 DOS_REG_ADDR(DOS_GCLK_EN0) -#define DOS_GEN_CTRL0 0x3f02 -#define P_DOS_GEN_CTRL0 DOS_REG_ADDR(DOS_GEN_CTRL0) -#define DOS_APB_ERR_CTRL 0x3f03 -#define P_DOS_APB_ERR_CTRL DOS_REG_ADDR(DOS_APB_ERR_CTRL) -#define DOS_APB_ERR_STAT 0x3f04 -#define P_DOS_APB_ERR_STAT DOS_REG_ADDR(DOS_APB_ERR_STAT) -#define DOS_VDEC_INT_EN 0x3f05 -#define P_DOS_VDEC_INT_EN DOS_REG_ADDR(DOS_VDEC_INT_EN) -#define DOS_HCODEC_INT_EN 0x3f06 -#define P_DOS_HCODEC_INT_EN DOS_REG_ADDR(DOS_HCODEC_INT_EN) -#define DOS_SW_RESET1 0x3f07 -#define P_DOS_SW_RESET1 DOS_REG_ADDR(DOS_SW_RESET1) -#define DOS_SW_RESET2 0x3f08 -#define P_DOS_SW_RESET2 DOS_REG_ADDR(DOS_SW_RESET2) -#define DOS_GCLK_EN1 0x3f09 -#define P_DOS_GCLK_EN1 DOS_REG_ADDR(DOS_GCLK_EN1) -#define DOS_VDEC2_INT_EN 0x3f0a -#define P_DOS_VDEC2_INT_EN DOS_REG_ADDR(DOS_VDEC2_INT_EN) -#define DOS_VDIN_LCNT 0x3f0b -#define P_DOS_VDIN_LCNT DOS_REG_ADDR(DOS_VDIN_LCNT) -#define DOS_VDIN_FCNT 0x3f0c -#define P_DOS_VDIN_FCNT DOS_REG_ADDR(DOS_VDIN_FCNT) -#define DOS_VDIN_CCTL 0x3f0d -#define P_DOS_VDIN_CCTL DOS_REG_ADDR(DOS_VDIN_CCTL) -#define DOS_SCRATCH0 0x3f10 -#define P_DOS_SCRATCH0 DOS_REG_ADDR(DOS_SCRATCH0) -#define DOS_SCRATCH1 0x3f11 -#define P_DOS_SCRATCH1 DOS_REG_ADDR(DOS_SCRATCH1) -#define DOS_SCRATCH2 0x3f12 -#define P_DOS_SCRATCH2 DOS_REG_ADDR(DOS_SCRATCH2) -#define DOS_SCRATCH3 0x3f13 -#define P_DOS_SCRATCH3 DOS_REG_ADDR(DOS_SCRATCH3) -#define DOS_SCRATCH4 0x3f14 -#define P_DOS_SCRATCH4 DOS_REG_ADDR(DOS_SCRATCH4) -#define DOS_SCRATCH5 0x3f15 -#define P_DOS_SCRATCH5 DOS_REG_ADDR(DOS_SCRATCH5) -#define DOS_SCRATCH6 0x3f16 -#define P_DOS_SCRATCH6 DOS_REG_ADDR(DOS_SCRATCH6) -#define DOS_SCRATCH7 0x3f17 -#define P_DOS_SCRATCH7 DOS_REG_ADDR(DOS_SCRATCH7) -#define DOS_SCRATCH8 0x3f18 -#define P_DOS_SCRATCH8 DOS_REG_ADDR(DOS_SCRATCH8) -#define DOS_SCRATCH9 0x3f19 -#define P_DOS_SCRATCH9 DOS_REG_ADDR(DOS_SCRATCH9) -#define DOS_SCRATCH10 0x3f1a -#define P_DOS_SCRATCH10 DOS_REG_ADDR(DOS_SCRATCH10) -#define DOS_SCRATCH11 0x3f1b -#define P_DOS_SCRATCH11 DOS_REG_ADDR(DOS_SCRATCH11) -#define DOS_SCRATCH12 0x3f1c -#define P_DOS_SCRATCH12 DOS_REG_ADDR(DOS_SCRATCH12) -#define DOS_SCRATCH13 0x3f1d -#define P_DOS_SCRATCH13 DOS_REG_ADDR(DOS_SCRATCH13) -#define DOS_SCRATCH14 0x3f1e -#define P_DOS_SCRATCH14 DOS_REG_ADDR(DOS_SCRATCH14) -#define DOS_SCRATCH15 0x3f1f -#define P_DOS_SCRATCH15 DOS_REG_ADDR(DOS_SCRATCH15) -#define DOS_SCRATCH16 0x3f20 -#define P_DOS_SCRATCH16 DOS_REG_ADDR(DOS_SCRATCH16) -#define DOS_SCRATCH17 0x3f21 -#define P_DOS_SCRATCH17 DOS_REG_ADDR(DOS_SCRATCH17) -#define DOS_SCRATCH18 0x3f22 -#define P_DOS_SCRATCH18 DOS_REG_ADDR(DOS_SCRATCH18) -#define DOS_SCRATCH19 0x3f23 -#define P_DOS_SCRATCH19 DOS_REG_ADDR(DOS_SCRATCH19) -#define DOS_SCRATCH20 0x3f24 -#define P_DOS_SCRATCH20 DOS_REG_ADDR(DOS_SCRATCH20) -#define DOS_SCRATCH21 0x3f25 -#define P_DOS_SCRATCH21 DOS_REG_ADDR(DOS_SCRATCH21) -#define DOS_SCRATCH22 0x3f26 -#define P_DOS_SCRATCH22 DOS_REG_ADDR(DOS_SCRATCH22) -#define DOS_SCRATCH23 0x3f27 -#define P_DOS_SCRATCH23 DOS_REG_ADDR(DOS_SCRATCH23) -#define DOS_SCRATCH24 0x3f28 -#define P_DOS_SCRATCH24 DOS_REG_ADDR(DOS_SCRATCH24) -#define DOS_SCRATCH25 0x3f29 -#define P_DOS_SCRATCH25 DOS_REG_ADDR(DOS_SCRATCH25) -#define DOS_SCRATCH26 0x3f2a -#define P_DOS_SCRATCH26 DOS_REG_ADDR(DOS_SCRATCH26) -#define DOS_SCRATCH27 0x3f2b -#define P_DOS_SCRATCH27 DOS_REG_ADDR(DOS_SCRATCH27) -#define DOS_SCRATCH28 0x3f2c -#define P_DOS_SCRATCH28 DOS_REG_ADDR(DOS_SCRATCH28) -#define DOS_SCRATCH29 0x3f2d -#define P_DOS_SCRATCH29 DOS_REG_ADDR(DOS_SCRATCH29) -#define DOS_SCRATCH30 0x3f2e -#define P_DOS_SCRATCH30 DOS_REG_ADDR(DOS_SCRATCH30) -#define DOS_SCRATCH31 0x3f2f -#define P_DOS_SCRATCH31 DOS_REG_ADDR(DOS_SCRATCH31) -#define DOS_MEM_PD_VDEC 0x3f30 -#define P_DOS_MEM_PD_VDEC DOS_REG_ADDR(DOS_MEM_PD_VDEC) -#define DOS_MEM_PD_VDEC2 0x3f31 -#define P_DOS_MEM_PD_VDEC2 DOS_REG_ADDR(DOS_MEM_PD_VDEC2) -#define DOS_MEM_PD_HCODEC 0x3f32 -#define P_DOS_MEM_PD_HCODEC DOS_REG_ADDR(DOS_MEM_PD_HCODEC) -/*add from M8M2*/ -#define DOS_MEM_PD_HEVC 0x3f33 -#define P_DOS_MEM_PD_HEVC DOS_REG_ADDR(DOS_MEM_PD_HEVC) -#define DOS_SW_RESET3 0x3f34 -#define P_DOS_SW_RESET3 DOS_REG_ADDR(DOS_SW_RESET3) -#define DOS_GCLK_EN3 0x3f35 -#define P_DOS_GCLK_EN3 DOS_REG_ADDR(DOS_GCLK_EN3) -#define DOS_HEVC_INT_EN 0x3f36 -#define P_DOS_HEVC_INT_EN DOS_REG_ADDR(DOS_HEVC_INT_EN) -/**/ - -#define HCODEC_MC_CTRL_REG 0x1900 -#define P_HCODEC_MC_CTRL_REG DOS_REG_ADDR(HCODEC_MC_CTRL_REG) -#define HCODEC_MC_MB_INFO 0x1901 -#define P_HCODEC_MC_MB_INFO DOS_REG_ADDR(HCODEC_MC_MB_INFO) -#define HCODEC_MC_PIC_INFO 0x1902 -#define P_HCODEC_MC_PIC_INFO DOS_REG_ADDR(HCODEC_MC_PIC_INFO) -#define HCODEC_POWER_CTL_MC 0x1905 -#define P_HCODEC_POWER_CTL_MC DOS_REG_ADDR(HCODEC_POWER_CTL_MC) -#define HCODEC_MC_CMD 0x1906 -#define P_HCODEC_MC_CMD DOS_REG_ADDR(HCODEC_MC_CMD) -#define HCODEC_MC_CTRL0 0x1907 -#define P_HCODEC_MC_CTRL0 DOS_REG_ADDR(HCODEC_MC_CTRL0) -#define HCODEC_MC_PIC_W_H 0x1908 -#define P_HCODEC_MC_PIC_W_H DOS_REG_ADDR(HCODEC_MC_PIC_W_H) -#define HCODEC_MC_STATUS0 0x1909 -#define P_HCODEC_MC_STATUS0 DOS_REG_ADDR(HCODEC_MC_STATUS0) -#define HCODEC_MC_STATUS1 0x190a -#define P_HCODEC_MC_STATUS1 DOS_REG_ADDR(HCODEC_MC_STATUS1) -#define HCODEC_MC_CTRL1 0x190b -#define P_HCODEC_MC_CTRL1 DOS_REG_ADDR(HCODEC_MC_CTRL1) -#define HCODEC_MC_MIX_RATIO0 0x190c -#define P_HCODEC_MC_MIX_RATIO0 DOS_REG_ADDR(HCODEC_MC_MIX_RATIO0) -#define HCODEC_MC_MIX_RATIO1 0x190d -#define P_HCODEC_MC_MIX_RATIO1 DOS_REG_ADDR(HCODEC_MC_MIX_RATIO1) -#define HCODEC_MC_DP_MB_XY 0x190e -#define P_HCODEC_MC_DP_MB_XY DOS_REG_ADDR(HCODEC_MC_DP_MB_XY) -#define HCODEC_MC_OM_MB_XY 0x190f -#define P_HCODEC_MC_OM_MB_XY DOS_REG_ADDR(HCODEC_MC_OM_MB_XY) -#define HCODEC_PSCALE_RST 0x1910 -#define P_HCODEC_PSCALE_RST DOS_REG_ADDR(HCODEC_PSCALE_RST) -#define HCODEC_PSCALE_CTRL 0x1911 -#define P_HCODEC_PSCALE_CTRL DOS_REG_ADDR(HCODEC_PSCALE_CTRL) -#define HCODEC_PSCALE_PICI_W 0x1912 -#define P_HCODEC_PSCALE_PICI_W DOS_REG_ADDR(HCODEC_PSCALE_PICI_W) -#define HCODEC_PSCALE_PICI_H 0x1913 -#define P_HCODEC_PSCALE_PICI_H DOS_REG_ADDR(HCODEC_PSCALE_PICI_H) -#define HCODEC_PSCALE_PICO_W 0x1914 -#define P_HCODEC_PSCALE_PICO_W DOS_REG_ADDR(HCODEC_PSCALE_PICO_W) -#define HCODEC_PSCALE_PICO_H 0x1915 -#define P_HCODEC_PSCALE_PICO_H DOS_REG_ADDR(HCODEC_PSCALE_PICO_H) -#define HCODEC_PSCALE_PICO_START_X 0x1916 - - -/**/ -#define HCODEC_MC_MPORT_CTRL 0x1940 -#define P_HCODEC_MC_MPORT_CTRL DOS_REG_ADDR(HCODEC_MC_MPORT_CTRL) -#define HCODEC_MC_MPORT_DAT 0x1941 -#define P_HCODEC_MC_MPORT_DAT DOS_REG_ADDR(HCODEC_MC_MPORT_DAT) -#define HCODEC_MC_DPDN_MB_XY 0x1946 -#define P_HCODEC_MC_DPDN_MB_XY DOS_REG_ADDR(HCODEC_MC_DPDN_MB_XY) -#define HCODEC_MC_OMDN_MB_XY 0x1947 -#define HCODEC_AV_SCRATCH_0 0x19c0 -#define P_HCODEC_AV_SCRATCH_0 DOS_REG_ADDR(HCODEC_AV_SCRATCH_0) -#define HCODEC_AV_SCRATCH_1 0x19c1 -#define P_HCODEC_AV_SCRATCH_1 DOS_REG_ADDR(HCODEC_AV_SCRATCH_1) -#define HCODEC_AV_SCRATCH_2 0x19c2 -#define P_HCODEC_AV_SCRATCH_2 DOS_REG_ADDR(HCODEC_AV_SCRATCH_2) -#define HCODEC_AV_SCRATCH_3 0x19c3 -#define P_HCODEC_AV_SCRATCH_3 DOS_REG_ADDR(HCODEC_AV_SCRATCH_3) -#define HCODEC_AV_SCRATCH_4 0x19c4 -#define P_HCODEC_AV_SCRATCH_4 DOS_REG_ADDR(HCODEC_AV_SCRATCH_4) -#define HCODEC_AV_SCRATCH_5 0x19c5 -#define P_HCODEC_AV_SCRATCH_5 DOS_REG_ADDR(HCODEC_AV_SCRATCH_5) -#define HCODEC_AV_SCRATCH_6 0x19c6 -#define P_HCODEC_AV_SCRATCH_6 DOS_REG_ADDR(HCODEC_AV_SCRATCH_6) -#define HCODEC_AV_SCRATCH_7 0x19c7 -#define P_HCODEC_AV_SCRATCH_7 DOS_REG_ADDR(HCODEC_AV_SCRATCH_7) -#define HCODEC_AV_SCRATCH_8 0x19c8 -#define P_HCODEC_AV_SCRATCH_8 DOS_REG_ADDR(HCODEC_AV_SCRATCH_8) -#define HCODEC_AV_SCRATCH_9 0x19c9 -#define P_HCODEC_AV_SCRATCH_9 DOS_REG_ADDR(HCODEC_AV_SCRATCH_9) -#define HCODEC_AV_SCRATCH_A 0x19ca -#define P_HCODEC_AV_SCRATCH_A DOS_REG_ADDR(HCODEC_AV_SCRATCH_A) -#define HCODEC_AV_SCRATCH_B 0x19cb -#define P_HCODEC_AV_SCRATCH_B DOS_REG_ADDR(HCODEC_AV_SCRATCH_B) -#define HCODEC_AV_SCRATCH_C 0x19cc -#define P_HCODEC_AV_SCRATCH_C DOS_REG_ADDR(HCODEC_AV_SCRATCH_C) -#define HCODEC_AV_SCRATCH_D 0x19cd -#define P_HCODEC_AV_SCRATCH_D DOS_REG_ADDR(HCODEC_AV_SCRATCH_D) -#define HCODEC_AV_SCRATCH_E 0x19ce -#define P_HCODEC_AV_SCRATCH_E DOS_REG_ADDR(HCODEC_AV_SCRATCH_E) -#define HCODEC_AV_SCRATCH_F 0x19cf -#define P_HCODEC_AV_SCRATCH_F DOS_REG_ADDR(HCODEC_AV_SCRATCH_F) -#define HCODEC_AV_SCRATCH_G 0x19d0 -#define P_HCODEC_AV_SCRATCH_G DOS_REG_ADDR(HCODEC_AV_SCRATCH_G) -#define HCODEC_AV_SCRATCH_H 0x19d1 -#define P_HCODEC_AV_SCRATCH_H DOS_REG_ADDR(HCODEC_AV_SCRATCH_H) -#define HCODEC_AV_SCRATCH_I 0x19d2 -#define P_HCODEC_AV_SCRATCH_I DOS_REG_ADDR(HCODEC_AV_SCRATCH_I) -#define HCODEC_AV_SCRATCH_J 0x19d3 -#define P_HCODEC_AV_SCRATCH_J DOS_REG_ADDR(HCODEC_AV_SCRATCH_J) -#define HCODEC_AV_SCRATCH_K 0x19d4 -#define P_HCODEC_AV_SCRATCH_K DOS_REG_ADDR(HCODEC_AV_SCRATCH_K) -#define HCODEC_AV_SCRATCH_L 0x19d5 -#define P_HCODEC_AV_SCRATCH_L DOS_REG_ADDR(HCODEC_AV_SCRATCH_L) -#define HCODEC_AV_SCRATCH_M 0x19d6 -#define P_HCODEC_AV_SCRATCH_M DOS_REG_ADDR(HCODEC_AV_SCRATCH_M) -#define HCODEC_AV_SCRATCH_N 0x19d7 -#define P_HCODEC_AV_SCRATCH_N DOS_REG_ADDR(HCODEC_AV_SCRATCH_N) -#define HCODEC_WRRSP_CO_MB 0x19d8 -#define P_HCODEC_WRRSP_CO_MB DOS_REG_ADDR(HCODEC_WRRSP_CO_MB) -#define HCODEC_WRRSP_DCAC 0x19d9 -#define P_HCODEC_WRRSP_DCAC DOS_REG_ADDR(HCODEC_WRRSP_DCAC) -/*add from M8M2*/ -#define VDEC2_AV_SCRATCH_0 0x29c0 -#define P_VDEC2_AV_SCRATCH_0 DOS_REG_ADDR(VDEC2_AV_SCRATCH_0) -#define VDEC2_AV_SCRATCH_1 0x29c1 -#define P_VDEC2_AV_SCRATCH_1 DOS_REG_ADDR(VDEC2_AV_SCRATCH_1) -#define VDEC2_AV_SCRATCH_2 0x29c2 -#define P_VDEC2_AV_SCRATCH_2 DOS_REG_ADDR(VDEC2_AV_SCRATCH_2) -#define VDEC2_AV_SCRATCH_3 0x29c3 -#define P_VDEC2_AV_SCRATCH_3 DOS_REG_ADDR(VDEC2_AV_SCRATCH_3) -#define VDEC2_AV_SCRATCH_4 0x29c4 -#define P_VDEC2_AV_SCRATCH_4 DOS_REG_ADDR(VDEC2_AV_SCRATCH_4) -#define VDEC2_AV_SCRATCH_5 0x29c5 -#define P_VDEC2_AV_SCRATCH_5 DOS_REG_ADDR(VDEC2_AV_SCRATCH_5) -#define VDEC2_AV_SCRATCH_6 0x29c6 -#define P_VDEC2_AV_SCRATCH_6 DOS_REG_ADDR(VDEC2_AV_SCRATCH_6) -#define VDEC2_AV_SCRATCH_7 0x29c7 -#define P_VDEC2_AV_SCRATCH_7 DOS_REG_ADDR(VDEC2_AV_SCRATCH_7) -#define VDEC2_AV_SCRATCH_8 0x29c8 -#define P_VDEC2_AV_SCRATCH_8 DOS_REG_ADDR(VDEC2_AV_SCRATCH_8) -#define VDEC2_AV_SCRATCH_9 0x29c9 -#define P_VDEC2_AV_SCRATCH_9 DOS_REG_ADDR(VDEC2_AV_SCRATCH_9) -#define VDEC2_AV_SCRATCH_A 0x29ca -#define P_VDEC2_AV_SCRATCH_A DOS_REG_ADDR(VDEC2_AV_SCRATCH_A) -#define VDEC2_AV_SCRATCH_B 0x29cb -#define P_VDEC2_AV_SCRATCH_B DOS_REG_ADDR(VDEC2_AV_SCRATCH_B) -#define VDEC2_AV_SCRATCH_C 0x29cc -#define P_VDEC2_AV_SCRATCH_C DOS_REG_ADDR(VDEC2_AV_SCRATCH_C) -#define VDEC2_AV_SCRATCH_D 0x29cd -#define P_VDEC2_AV_SCRATCH_D DOS_REG_ADDR(VDEC2_AV_SCRATCH_D) -#define VDEC2_AV_SCRATCH_E 0x29ce -#define P_VDEC2_AV_SCRATCH_E DOS_REG_ADDR(VDEC2_AV_SCRATCH_E) -#define VDEC2_AV_SCRATCH_F 0x29cf -#define P_VDEC2_AV_SCRATCH_F DOS_REG_ADDR(VDEC2_AV_SCRATCH_F) -#define VDEC2_AV_SCRATCH_G 0x29d0 -#define P_VDEC2_AV_SCRATCH_G DOS_REG_ADDR(VDEC2_AV_SCRATCH_G) -#define VDEC2_AV_SCRATCH_H 0x29d1 -#define P_VDEC2_AV_SCRATCH_H DOS_REG_ADDR(VDEC2_AV_SCRATCH_H) -#define VDEC2_AV_SCRATCH_I 0x29d2 -#define P_VDEC2_AV_SCRATCH_I DOS_REG_ADDR(VDEC2_AV_SCRATCH_I) -#define VDEC2_AV_SCRATCH_J 0x29d3 -#define P_VDEC2_AV_SCRATCH_J DOS_REG_ADDR(VDEC2_AV_SCRATCH_J) -#define VDEC2_AV_SCRATCH_K 0x29d4 -#define P_VDEC2_AV_SCRATCH_K DOS_REG_ADDR(VDEC2_AV_SCRATCH_K) -#define VDEC2_AV_SCRATCH_L 0x29d5 -#define P_VDEC2_AV_SCRATCH_L DOS_REG_ADDR(VDEC2_AV_SCRATCH_L) -#define VDEC2_AV_SCRATCH_M 0x29d6 -#define P_VDEC2_AV_SCRATCH_M DOS_REG_ADDR(VDEC2_AV_SCRATCH_M) -#define VDEC2_AV_SCRATCH_N 0x29d7 -#define P_VDEC2_AV_SCRATCH_N DOS_REG_ADDR(VDEC2_AV_SCRATCH_N) -#define VDEC2_WRRSP_CO_MB 0x29d8 -#define P_VDEC2_WRRSP_CO_MB DOS_REG_ADDR(VDEC2_WRRSP_CO_MB) -#define VDEC2_WRRSP_DCAC 0x29d9 -#define P_VDEC2_WRRSP_DCAC DOS_REG_ADDR(VDEC2_WRRSP_DCAC) -/*add from M8M2*/ -/**/ -#define VDEC2_DBLK_RST 0x2950 -#define P_VDEC2_DBLK_RST DOS_REG_ADDR(VDEC2_DBLK_RST) -#define VDEC2_DBLK_CTRL 0x2951 -#define P_VDEC2_DBLK_CTRL DOS_REG_ADDR(VDEC2_DBLK_CTRL) -#define VDEC2_DBLK_MB_WID_HEIGHT 0x2952 -#define VDEC2_DBLK_STATUS 0x2953 -#define P_VDEC2_DBLK_STATUS DOS_REG_ADDR(VDEC2_DBLK_STATUS) -#define VDEC2_DBLK_CMD_CTRL 0x2954 -#define P_VDEC2_DBLK_CMD_CTRL DOS_REG_ADDR(VDEC2_DBLK_CMD_CTRL) -#define VDEC2_DBLK_MB_XY 0x2955 -#define P_VDEC2_DBLK_MB_XY DOS_REG_ADDR(VDEC2_DBLK_MB_XY) -#define VDEC2_DBLK_QP 0x2956 -#define P_VDEC2_DBLK_QP DOS_REG_ADDR(VDEC2_DBLK_QP) -#define VDEC2_DBLK_Y_BHFILT 0x2957 -#define P_VDEC2_DBLK_Y_BHFILT DOS_REG_ADDR(VDEC2_DBLK_Y_BHFILT) -#define VDEC2_DBLK_Y_BHFILT_HIGH 0x2958 -#define VDEC2_DBLK_Y_BVFILT 0x2959 -#define P_VDEC2_DBLK_Y_BVFILT DOS_REG_ADDR(VDEC2_DBLK_Y_BVFILT) -#define VDEC2_DBLK_CB_BFILT 0x295a -#define P_VDEC2_DBLK_CB_BFILT DOS_REG_ADDR(VDEC2_DBLK_CB_BFILT) -#define VDEC2_DBLK_CR_BFILT 0x295b -#define P_VDEC2_DBLK_CR_BFILT DOS_REG_ADDR(VDEC2_DBLK_CR_BFILT) -#define VDEC2_DBLK_Y_HFILT 0x295c -#define P_VDEC2_DBLK_Y_HFILT DOS_REG_ADDR(VDEC2_DBLK_Y_HFILT) -#define VDEC2_DBLK_Y_VFILT 0x295e -#define P_VDEC2_DBLK_Y_VFILT DOS_REG_ADDR(VDEC2_DBLK_Y_VFILT) -#define VDEC2_DBLK_CB_FILT 0x295f -#define P_VDEC2_DBLK_CB_FILT DOS_REG_ADDR(VDEC2_DBLK_CB_FILT) -#define VDEC2_DBLK_CR_FILT 0x2960 -#define P_VDEC2_DBLK_CR_FILT DOS_REG_ADDR(VDEC2_DBLK_CR_FILT) -#define VDEC2_DBLK_STATUS1 0x296b -#define P_VDEC2_DBLK_STATUS1 DOS_REG_ADDR(VDEC2_DBLK_STATUS1) -#define VDEC2_DBLK_GCLK_FREE 0x296c -#define P_VDEC2_DBLK_GCLK_FREE DOS_REG_ADDR(VDEC2_DBLK_GCLK_FREE) -#define VDEC2_DBLK_GCLK_OFF 0x296d -#define P_VDEC2_DBLK_GCLK_OFF DOS_REG_ADDR(VDEC2_DBLK_GCLK_OFF) -#define VDEC2_DBLK_AVSFLAGS 0x296e -#define P_VDEC2_DBLK_AVSFLAGS DOS_REG_ADDR(VDEC2_DBLK_AVSFLAGS) -#define VDEC2_DBLK_CBPY 0x2970 -#define P_VDEC2_DBLK_CBPY DOS_REG_ADDR(VDEC2_DBLK_CBPY) -#define VDEC2_DBLK_CBPY_ADJ 0x2971 -#define P_VDEC2_DBLK_CBPY_ADJ DOS_REG_ADDR(VDEC2_DBLK_CBPY_ADJ) -#define VDEC2_DBLK_CBPC 0x2972 -#define P_VDEC2_DBLK_CBPC DOS_REG_ADDR(VDEC2_DBLK_CBPC) -#define VDEC2_DBLK_CBPC_ADJ 0x2973 -#define P_VDEC2_DBLK_CBPC_ADJ DOS_REG_ADDR(VDEC2_DBLK_CBPC_ADJ) -#define VDEC2_DBLK_VHMVD 0x2974 -#define P_VDEC2_DBLK_VHMVD DOS_REG_ADDR(VDEC2_DBLK_VHMVD) -#define VDEC2_DBLK_STRONG 0x2975 -#define P_VDEC2_DBLK_STRONG DOS_REG_ADDR(VDEC2_DBLK_STRONG) -#define VDEC2_DBLK_RV8_QUANT 0x2976 -#define P_VDEC2_DBLK_RV8_QUANT DOS_REG_ADDR(VDEC2_DBLK_RV8_QUANT) -#define VDEC2_DBLK_CBUS_HCMD2 0x2977 -#define VDEC2_DBLK_VLD_HCMD2 0x297a -#define P_VDEC2_DBLK_VLD_HCMD2 DOS_REG_ADDR(VDEC2_DBLK_VLD_HCMD2) -#define VDEC2_DBLK_VLD_HCMD1 0x297b -#define P_VDEC2_DBLK_VLD_HCMD1 DOS_REG_ADDR(VDEC2_DBLK_VLD_HCMD1) -#define VDEC2_DBLK_VLD_HCMD0 0x297c -#define P_VDEC2_DBLK_VLD_HCMD0 DOS_REG_ADDR(VDEC2_DBLK_VLD_HCMD0) -#define VDEC2_MCRCC_CTL1 0x2980 -#define P_VDEC2_MCRCC_CTL1 DOS_REG_ADDR(VDEC2_MCRCC_CTL1) -#define VDEC2_MCRCC_CTL2 0x2981 -#define P_VDEC2_MCRCC_CTL2 DOS_REG_ADDR(VDEC2_MCRCC_CTL2) -#define VDEC2_MCRCC_CTL3 0x2982 -#define P_VDEC2_MCRCC_CTL3 DOS_REG_ADDR(VDEC2_MCRCC_CTL3) -#define VDEC2_GCLK_EN 0x2983 -#define P_VDEC2_GCLK_EN DOS_REG_ADDR(VDEC2_GCLK_EN) -#define VDEC2_MDEC_SW_RESET 0x2984 -#define P_VDEC2_MDEC_SW_RESET DOS_REG_ADDR(VDEC2_MDEC_SW_RESET) -/*add from M8M2*/ -#define HEVC_MC_CTRL_REG 0x3900 -#define P_HEVC_MC_CTRL_REG DOS_REG_ADDR(HEVC_MC_CTRL_REG) -#define HEVC_MC_MB_INFO 0x3901 -#define P_HEVC_MC_MB_INFO DOS_REG_ADDR(HEVC_MC_MB_INFO) -#define HEVC_MC_PIC_INFO 0x3902 -#define P_HEVC_MC_PIC_INFO DOS_REG_ADDR(HEVC_MC_PIC_INFO) -#define HEVC_MC_HALF_PEL_ONE 0x3903 -#define P_HEVC_MC_HALF_PEL_ONE DOS_REG_ADDR(HEVC_MC_HALF_PEL_ONE) -#define HEVC_MC_HALF_PEL_TWO 0x3904 -#define P_HEVC_MC_HALF_PEL_TWO DOS_REG_ADDR(HEVC_MC_HALF_PEL_TWO) -#define HEVC_POWER_CTL_MC 0x3905 -#define P_HEVC_POWER_CTL_MC DOS_REG_ADDR(HEVC_POWER_CTL_MC) -#define HEVC_MC_CMD 0x3906 -#define P_HEVC_MC_CMD DOS_REG_ADDR(HEVC_MC_CMD) -#define HEVC_MC_CTRL0 0x3907 -#define P_HEVC_MC_CTRL0 DOS_REG_ADDR(HEVC_MC_CTRL0) -#define HEVC_MC_PIC_W_H 0x3908 -#define P_HEVC_MC_PIC_W_H DOS_REG_ADDR(HEVC_MC_PIC_W_H) -#define HEVC_MC_STATUS0 0x3909 -#define P_HEVC_MC_STATUS0 DOS_REG_ADDR(HEVC_MC_STATUS0) -#define HEVC_MC_STATUS1 0x390a -#define P_HEVC_MC_STATUS1 DOS_REG_ADDR(HEVC_MC_STATUS1) -#define HEVC_MC_CTRL1 0x390b -#define P_HEVC_MC_CTRL1 DOS_REG_ADDR(HEVC_MC_CTRL1) -#define HEVC_MC_MIX_RATIO0 0x390c -#define P_HEVC_MC_MIX_RATIO0 DOS_REG_ADDR(HEVC_MC_MIX_RATIO0) -#define HEVC_MC_MIX_RATIO1 0x390d -#define P_HEVC_MC_MIX_RATIO1 DOS_REG_ADDR(HEVC_MC_MIX_RATIO1) -#define HEVC_MC_DP_MB_XY 0x390e -#define P_HEVC_MC_DP_MB_XY DOS_REG_ADDR(HEVC_MC_DP_MB_XY) -#define HEVC_MC_OM_MB_XY 0x390f -#define P_HEVC_MC_OM_MB_XY DOS_REG_ADDR(HEVC_MC_OM_MB_XY) -#define HEVC_PSCALE_RST 0x3910 -#define P_HEVC_PSCALE_RST DOS_REG_ADDR(HEVC_PSCALE_RST) -#define HEVC_PSCALE_CTRL 0x3911 -#define P_HEVC_PSCALE_CTRL DOS_REG_ADDR(HEVC_PSCALE_CTRL) -#define HEVC_PSCALE_PICI_W 0x3912 -#define P_HEVC_PSCALE_PICI_W DOS_REG_ADDR(HEVC_PSCALE_PICI_W) -#define HEVC_PSCALE_PICI_H 0x3913 -#define P_HEVC_PSCALE_PICI_H DOS_REG_ADDR(HEVC_PSCALE_PICI_H) -#define HEVC_PSCALE_PICO_W 0x3914 -#define P_HEVC_PSCALE_PICO_W DOS_REG_ADDR(HEVC_PSCALE_PICO_W) -#define HEVC_PSCALE_PICO_H 0x3915 -#define P_HEVC_PSCALE_PICO_H DOS_REG_ADDR(HEVC_PSCALE_PICO_H) - -#define HEVC_MC_DPDN_MB_XY 0x3946 -#define P_HEVC_MC_DPDN_MB_XY DOS_REG_ADDR(HEVC_MC_DPDN_MB_XY) -#define HEVC_MC_OMDN_MB_XY 0x3947 -#define P_HEVC_MC_OMDN_MB_XY DOS_REG_ADDR(HEVC_MC_OMDN_MB_XY) -#define HEVC_MC_HCMDBUF_H 0x3948 -#define P_HEVC_MC_HCMDBUF_H DOS_REG_ADDR(HEVC_MC_HCMDBUF_H) -#define HEVC_MC_HCMDBUF_L 0x3949 -#define P_HEVC_MC_HCMDBUF_L DOS_REG_ADDR(HEVC_MC_HCMDBUF_L) -#define HEVC_MC_HCMD_H 0x394a -#define P_HEVC_MC_HCMD_H DOS_REG_ADDR(HEVC_MC_HCMD_H) -#define HEVC_MC_HCMD_L 0x394b -#define P_HEVC_MC_HCMD_L DOS_REG_ADDR(HEVC_MC_HCMD_L) -#define HEVC_MC_IDCT_DAT 0x394c -#define P_HEVC_MC_IDCT_DAT DOS_REG_ADDR(HEVC_MC_IDCT_DAT) -#define HEVC_MC_OTHER_GCLK_CTRL 0x394e - -#define HEVC_AV_SCRATCH_0 0x39c0 -#define P_HEVC_AV_SCRATCH_0 DOS_REG_ADDR(HEVC_AV_SCRATCH_0) -#define HEVC_AV_SCRATCH_1 0x39c1 -#define P_HEVC_AV_SCRATCH_1 DOS_REG_ADDR(HEVC_AV_SCRATCH_1) -#define HEVC_AV_SCRATCH_2 0x39c2 -#define P_HEVC_AV_SCRATCH_2 DOS_REG_ADDR(HEVC_AV_SCRATCH_2) -#define HEVC_AV_SCRATCH_3 0x39c3 -#define P_HEVC_AV_SCRATCH_3 DOS_REG_ADDR(HEVC_AV_SCRATCH_3) -#define HEVC_AV_SCRATCH_4 0x39c4 -#define P_HEVC_AV_SCRATCH_4 DOS_REG_ADDR(HEVC_AV_SCRATCH_4) -#define HEVC_AV_SCRATCH_5 0x39c5 -#define P_HEVC_AV_SCRATCH_5 DOS_REG_ADDR(HEVC_AV_SCRATCH_5) -#define HEVC_AV_SCRATCH_6 0x39c6 -#define P_HEVC_AV_SCRATCH_6 DOS_REG_ADDR(HEVC_AV_SCRATCH_6) -#define HEVC_AV_SCRATCH_7 0x39c7 -#define P_HEVC_AV_SCRATCH_7 DOS_REG_ADDR(HEVC_AV_SCRATCH_7) -#define HEVC_AV_SCRATCH_8 0x39c8 -#define P_HEVC_AV_SCRATCH_8 DOS_REG_ADDR(HEVC_AV_SCRATCH_8) -#define HEVC_AV_SCRATCH_9 0x39c9 -#define P_HEVC_AV_SCRATCH_9 DOS_REG_ADDR(HEVC_AV_SCRATCH_9) -#define HEVC_AV_SCRATCH_A 0x39ca -#define P_HEVC_AV_SCRATCH_A DOS_REG_ADDR(HEVC_AV_SCRATCH_A) -#define HEVC_AV_SCRATCH_B 0x39cb -#define P_HEVC_AV_SCRATCH_B DOS_REG_ADDR(HEVC_AV_SCRATCH_B) -#define HEVC_AV_SCRATCH_C 0x39cc -#define P_HEVC_AV_SCRATCH_C DOS_REG_ADDR(HEVC_AV_SCRATCH_C) -#define HEVC_AV_SCRATCH_D 0x39cd -#define P_HEVC_AV_SCRATCH_D DOS_REG_ADDR(HEVC_AV_SCRATCH_D) -#define HEVC_AV_SCRATCH_E 0x39ce -#define P_HEVC_AV_SCRATCH_E DOS_REG_ADDR(HEVC_AV_SCRATCH_E) -#define HEVC_AV_SCRATCH_F 0x39cf -#define P_HEVC_AV_SCRATCH_F DOS_REG_ADDR(HEVC_AV_SCRATCH_F) -#define HEVC_AV_SCRATCH_G 0x39d0 -#define P_HEVC_AV_SCRATCH_G DOS_REG_ADDR(HEVC_AV_SCRATCH_G) -#define HEVC_AV_SCRATCH_H 0x39d1 -#define P_HEVC_AV_SCRATCH_H DOS_REG_ADDR(HEVC_AV_SCRATCH_H) -#define HEVC_AV_SCRATCH_I 0x39d2 -#define P_HEVC_AV_SCRATCH_I DOS_REG_ADDR(HEVC_AV_SCRATCH_I) -#define HEVC_AV_SCRATCH_J 0x39d3 -#define P_HEVC_AV_SCRATCH_J DOS_REG_ADDR(HEVC_AV_SCRATCH_J) -#define HEVC_AV_SCRATCH_K 0x39d4 -#define P_HEVC_AV_SCRATCH_K DOS_REG_ADDR(HEVC_AV_SCRATCH_K) -#define HEVC_AV_SCRATCH_L 0x39d5 -#define P_HEVC_AV_SCRATCH_L DOS_REG_ADDR(HEVC_AV_SCRATCH_L) -#define HEVC_AV_SCRATCH_M 0x39d6 -#define P_HEVC_AV_SCRATCH_M DOS_REG_ADDR(HEVC_AV_SCRATCH_M) -#define HEVC_AV_SCRATCH_N 0x39d7 -#define P_HEVC_AV_SCRATCH_N DOS_REG_ADDR(HEVC_AV_SCRATCH_N) -#define HEVC_WRRSP_CO_MB 0x39d8 -#define P_HEVC_WRRSP_CO_MB DOS_REG_ADDR(HEVC_WRRSP_CO_MB) - -#define HEVC_DBLK_RST 0x3950 -#define P_HEVC_DBLK_RST DOS_REG_ADDR(HEVC_DBLK_RST) -#define HEVC_DBLK_CTRL 0x3951 -#define P_HEVC_DBLK_CTRL DOS_REG_ADDR(HEVC_DBLK_CTRL) -#define HEVC_DBLK_MB_WID_HEIGHT 0x3952 -#define HEVC_DBLK_STATUS 0x3953 -#define P_HEVC_DBLK_STATUS DOS_REG_ADDR(HEVC_DBLK_STATUS) -#define HEVC_DBLK_CMD_CTRL 0x3954 -#define P_HEVC_DBLK_CMD_CTRL DOS_REG_ADDR(HEVC_DBLK_CMD_CTRL) -#define HEVC_DBLK_MB_XY 0x3955 -#define P_HEVC_DBLK_MB_XY DOS_REG_ADDR(HEVC_DBLK_MB_XY) -#define HEVC_DBLK_QP 0x3956 -#define P_HEVC_DBLK_QP DOS_REG_ADDR(HEVC_DBLK_QP) -#define HEVC_DBLK_Y_BHFILT 0x3957 -#define P_HEVC_DBLK_Y_BHFILT DOS_REG_ADDR(HEVC_DBLK_Y_BHFILT) -#define HEVC_DBLK_Y_BVFILT 0x3959 -#define P_HEVC_DBLK_Y_BVFILT DOS_REG_ADDR(HEVC_DBLK_Y_BVFILT) -#define HEVC_DBLK_CB_BFILT 0x395a -#define P_HEVC_DBLK_CB_BFILT DOS_REG_ADDR(HEVC_DBLK_CB_BFILT) -#define HEVC_DBLK_CR_BFILT 0x395b -#define P_HEVC_DBLK_CR_BFILT DOS_REG_ADDR(HEVC_DBLK_CR_BFILT) -#define HEVC_DBLK_Y_HFILT 0x395c -#define P_HEVC_DBLK_Y_HFILT DOS_REG_ADDR(HEVC_DBLK_Y_HFILT) -#define HEVC_DBLK_Y_VFILT 0x395e -#define P_HEVC_DBLK_Y_VFILT DOS_REG_ADDR(HEVC_DBLK_Y_VFILT) -#define HEVC_DBLK_CB_FILT 0x395f -#define P_HEVC_DBLK_CB_FILT DOS_REG_ADDR(HEVC_DBLK_CB_FILT) -#define HEVC_DBLK_CR_FILT 0x3960 -#define P_HEVC_DBLK_CR_FILT DOS_REG_ADDR(HEVC_DBLK_CR_FILT) -#define HEVC_DBLK_CLIP_CTRL0 0x3962 -#define P_HEVC_DBLK_CLIP_CTRL0 DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL0) -#define HEVC_DBLK_CLIP_CTRL1 0x3963 -#define P_HEVC_DBLK_CLIP_CTRL1 DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL1) -#define HEVC_DBLK_CLIP_CTRL2 0x3964 -#define P_HEVC_DBLK_CLIP_CTRL2 DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL2) -#define HEVC_DBLK_CLIP_CTRL3 0x3965 -#define P_HEVC_DBLK_CLIP_CTRL3 DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL3) -#define HEVC_DBLK_CLIP_CTRL4 0x3966 -#define P_HEVC_DBLK_CLIP_CTRL4 DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL4) -#define HEVC_DBLK_CLIP_CTRL5 0x3967 -#define P_HEVC_DBLK_CLIP_CTRL5 DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL5) -#define HEVC_DBLK_CLIP_CTRL6 0x3968 -#define P_HEVC_DBLK_CLIP_CTRL6 DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL6) -#define HEVC_DBLK_CLIP_CTRL7 0x3969 -#define P_HEVC_DBLK_CLIP_CTRL7 DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL7) -#define HEVC_DBLK_CLIP_CTRL8 0x396a -#define P_HEVC_DBLK_CLIP_CTRL8 DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL8) -#define HEVC_DBLK_STATUS1 0x396b -#define P_HEVC_DBLK_STATUS1 DOS_REG_ADDR(HEVC_DBLK_STATUS1) -#define HEVC_DBLK_GCLK_FREE 0x396c -#define P_HEVC_DBLK_GCLK_FREE DOS_REG_ADDR(HEVC_DBLK_GCLK_FREE) -#define HEVC_DBLK_GCLK_OFF 0x396d -#define P_HEVC_DBLK_GCLK_OFF DOS_REG_ADDR(HEVC_DBLK_GCLK_OFF) -#define HEVC_DBLK_AVSFLAGS 0x396e -#define P_HEVC_DBLK_AVSFLAGS DOS_REG_ADDR(HEVC_DBLK_AVSFLAGS) -#define HEVC_DBLK_CBPY 0x3970 -#define P_HEVC_DBLK_CBPY DOS_REG_ADDR(HEVC_DBLK_CBPY) -#define HEVC_DBLK_CBPY_ADJ 0x3971 -#define P_HEVC_DBLK_CBPY_ADJ DOS_REG_ADDR(HEVC_DBLK_CBPY_ADJ) -#define HEVC_DBLK_CBPC 0x3972 -#define P_HEVC_DBLK_CBPC DOS_REG_ADDR(HEVC_DBLK_CBPC) -#define HEVC_DBLK_CBPC_ADJ 0x3973 -#define P_HEVC_DBLK_CBPC_ADJ DOS_REG_ADDR(HEVC_DBLK_CBPC_ADJ) -#define HEVC_DBLK_VHMVD 0x3974 -#define P_HEVC_DBLK_VHMVD DOS_REG_ADDR(HEVC_DBLK_VHMVD) -#define HEVC_DBLK_STRONG 0x3975 -#define P_HEVC_DBLK_STRONG DOS_REG_ADDR(HEVC_DBLK_STRONG) -#define HEVC_DBLK_RV8_QUANT 0x3976 -#define P_HEVC_DBLK_RV8_QUANT DOS_REG_ADDR(HEVC_DBLK_RV8_QUANT) -#define HEVC_DBLK_CBUS_HCMD2 0x3977 -#define P_HEVC_DBLK_CBUS_HCMD2 DOS_REG_ADDR(HEVC_DBLK_CBUS_HCMD2) -#define HEVC_DBLK_CBUS_HCMD1 0x3978 -#define P_HEVC_DBLK_CBUS_HCMD1 DOS_REG_ADDR(HEVC_DBLK_CBUS_HCMD1) -#define HEVC_DBLK_CBUS_HCMD0 0x3979 -#define P_HEVC_DBLK_CBUS_HCMD0 DOS_REG_ADDR(HEVC_DBLK_CBUS_HCMD0) -#define HEVC_DBLK_VLD_HCMD2 0x397a -#define P_HEVC_DBLK_VLD_HCMD2 DOS_REG_ADDR(HEVC_DBLK_VLD_HCMD2) -#define HEVC_DBLK_VLD_HCMD1 0x397b -#define P_HEVC_DBLK_VLD_HCMD1 DOS_REG_ADDR(HEVC_DBLK_VLD_HCMD1) -#define HEVC_DBLK_VLD_HCMD0 0x397c -#define P_HEVC_DBLK_VLD_HCMD0 DOS_REG_ADDR(HEVC_DBLK_VLD_HCMD0) -#define HEVC_DBLK_OST_YBASE 0x397d -#define P_HEVC_DBLK_OST_YBASE DOS_REG_ADDR(HEVC_DBLK_OST_YBASE) -#define HEVC_DBLK_CTRL1 0x397f -#define P_HEVC_DBLK_CTRL1 DOS_REG_ADDR(HEVC_DBLK_CTRL1) -#define HEVC_MCRCC_CTL1 0x3980 -#define P_HEVC_MCRCC_CTL1 DOS_REG_ADDR(HEVC_MCRCC_CTL1) -#define HEVC_MCRCC_CTL2 0x3981 -#define P_HEVC_MCRCC_CTL2 DOS_REG_ADDR(HEVC_MCRCC_CTL2) -#define HEVC_MCRCC_CTL3 0x3982 -#define P_HEVC_MCRCC_CTL3 DOS_REG_ADDR(HEVC_MCRCC_CTL3) -#define HEVC_GCLK_EN 0x3983 -#define P_HEVC_GCLK_EN DOS_REG_ADDR(HEVC_GCLK_EN) -#define HEVC_MDEC_SW_RESET 0x3984 -#define P_HEVC_MDEC_SW_RESET DOS_REG_ADDR(HEVC_MDEC_SW_RESET) -/**/ -#define HEVC_DCAC_CPU_DATA 0x3e15 -#define P_HEVC_DCAC_CPU_DATA DOS_REG_ADDR(HEVC_DCAC_CPU_DATA) -#define HEVC_DCAC_MB_COUNT 0x3e16 -#define P_HEVC_DCAC_MB_COUNT DOS_REG_ADDR(HEVC_DCAC_MB_COUNT) -#define HEVC_IQ_QUANT 0x3e17 -#define P_HEVC_IQ_QUANT DOS_REG_ADDR(HEVC_IQ_QUANT) -/**/ -#define HCODEC_MSP 0x1300 -#define P_HCODEC_MSP DOS_REG_ADDR(HCODEC_MSP) -#define HCODEC_MPSR 0x1301 -#define P_HCODEC_MPSR DOS_REG_ADDR(HCODEC_MPSR) -#define HCODEC_MINT_VEC_BASE 0x1302 -#define P_HCODEC_MINT_VEC_BASE DOS_REG_ADDR(HCODEC_MINT_VEC_BASE) -#define HCODEC_MCPU_INTR_GRP 0x1303 -#define P_HCODEC_MCPU_INTR_GRP DOS_REG_ADDR(HCODEC_MCPU_INTR_GRP) -#define HCODEC_MCPU_INTR_MSK 0x1304 -#define P_HCODEC_MCPU_INTR_MSK DOS_REG_ADDR(HCODEC_MCPU_INTR_MSK) -#define HCODEC_MCPU_INTR_REQ 0x1305 -#define P_HCODEC_MCPU_INTR_REQ DOS_REG_ADDR(HCODEC_MCPU_INTR_REQ) -#define HCODEC_MPC_P 0x1306 -#define P_HCODEC_MPC_P DOS_REG_ADDR(HCODEC_MPC_P) -#define HCODEC_MPC_D 0x1307 -#define P_HCODEC_MPC_D DOS_REG_ADDR(HCODEC_MPC_D) -#define HCODEC_MPC_E 0x1308 -#define P_HCODEC_MPC_E DOS_REG_ADDR(HCODEC_MPC_E) -#define HCODEC_MPC_W 0x1309 -#define P_HCODEC_MPC_W DOS_REG_ADDR(HCODEC_MPC_W) -#define HCODEC_MINDEX0_REG 0x130a -#define P_HCODEC_MINDEX0_REG DOS_REG_ADDR(HCODEC_MINDEX0_REG) -#define HCODEC_MINDEX1_REG 0x130b -#define P_HCODEC_MINDEX1_REG DOS_REG_ADDR(HCODEC_MINDEX1_REG) -#define HCODEC_MINDEX2_REG 0x130c -#define P_HCODEC_MINDEX2_REG DOS_REG_ADDR(HCODEC_MINDEX2_REG) -#define HCODEC_MINDEX3_REG 0x130d -#define P_HCODEC_MINDEX3_REG DOS_REG_ADDR(HCODEC_MINDEX3_REG) -#define HCODEC_MINDEX4_REG 0x130e -#define P_HCODEC_MINDEX4_REG DOS_REG_ADDR(HCODEC_MINDEX4_REG) -#define HCODEC_MINDEX5_REG 0x130f -#define P_HCODEC_MINDEX5_REG DOS_REG_ADDR(HCODEC_MINDEX5_REG) -#define HCODEC_MINDEX6_REG 0x1310 -#define P_HCODEC_MINDEX6_REG DOS_REG_ADDR(HCODEC_MINDEX6_REG) -#define HCODEC_MINDEX7_REG 0x1311 -#define P_HCODEC_MINDEX7_REG DOS_REG_ADDR(HCODEC_MINDEX7_REG) -#define HCODEC_MMIN_REG 0x1312 -#define P_HCODEC_MMIN_REG DOS_REG_ADDR(HCODEC_MMIN_REG) -#define HCODEC_MMAX_REG 0x1313 -#define P_HCODEC_MMAX_REG DOS_REG_ADDR(HCODEC_MMAX_REG) -#define HCODEC_MBREAK0_REG 0x1314 -#define P_HCODEC_MBREAK0_REG DOS_REG_ADDR(HCODEC_MBREAK0_REG) -#define HCODEC_MBREAK1_REG 0x1315 -#define P_HCODEC_MBREAK1_REG DOS_REG_ADDR(HCODEC_MBREAK1_REG) -#define HCODEC_MBREAK2_REG 0x1316 -#define P_HCODEC_MBREAK2_REG DOS_REG_ADDR(HCODEC_MBREAK2_REG) -#define HCODEC_MBREAK3_REG 0x1317 -#define P_HCODEC_MBREAK3_REG DOS_REG_ADDR(HCODEC_MBREAK3_REG) -#define HCODEC_MBREAK_TYPE 0x1318 -#define P_HCODEC_MBREAK_TYPE DOS_REG_ADDR(HCODEC_MBREAK_TYPE) -#define HCODEC_MBREAK_CTRL 0x1319 -#define P_HCODEC_MBREAK_CTRL DOS_REG_ADDR(HCODEC_MBREAK_CTRL) -#define HCODEC_MBREAK_STAUTS 0x131a -#define P_HCODEC_MBREAK_STAUTS DOS_REG_ADDR(HCODEC_MBREAK_STAUTS) -#define HCODEC_MDB_ADDR_REG 0x131b -#define P_HCODEC_MDB_ADDR_REG DOS_REG_ADDR(HCODEC_MDB_ADDR_REG) -#define HCODEC_MDB_DATA_REG 0x131c -#define P_HCODEC_MDB_DATA_REG DOS_REG_ADDR(HCODEC_MDB_DATA_REG) -#define HCODEC_MDB_CTRL 0x131d -#define P_HCODEC_MDB_CTRL DOS_REG_ADDR(HCODEC_MDB_CTRL) -#define HCODEC_MSFTINT0 0x131e -#define P_HCODEC_MSFTINT0 DOS_REG_ADDR(HCODEC_MSFTINT0) -#define HCODEC_MSFTINT1 0x131f -#define P_HCODEC_MSFTINT1 DOS_REG_ADDR(HCODEC_MSFTINT1) -#define HCODEC_CSP 0x1320 -#define P_HCODEC_CSP DOS_REG_ADDR(HCODEC_CSP) -#define HCODEC_CPSR 0x1321 -#define P_HCODEC_CPSR DOS_REG_ADDR(HCODEC_CPSR) -#define HCODEC_CINT_VEC_BASE 0x1322 -#define P_HCODEC_CINT_VEC_BASE DOS_REG_ADDR(HCODEC_CINT_VEC_BASE) -#define HCODEC_CCPU_INTR_GRP 0x1323 -#define P_HCODEC_CCPU_INTR_GRP DOS_REG_ADDR(HCODEC_CCPU_INTR_GRP) -#define HCODEC_CCPU_INTR_MSK 0x1324 -#define P_HCODEC_CCPU_INTR_MSK DOS_REG_ADDR(HCODEC_CCPU_INTR_MSK) -#define HCODEC_CCPU_INTR_REQ 0x1325 -#define P_HCODEC_CCPU_INTR_REQ DOS_REG_ADDR(HCODEC_CCPU_INTR_REQ) -#define HCODEC_CPC_P 0x1326 -#define P_HCODEC_CPC_P DOS_REG_ADDR(HCODEC_CPC_P) -#define HCODEC_CPC_D 0x1327 -#define P_HCODEC_CPC_D DOS_REG_ADDR(HCODEC_CPC_D) -#define HCODEC_CPC_E 0x1328 -#define P_HCODEC_CPC_E DOS_REG_ADDR(HCODEC_CPC_E) -#define HCODEC_CPC_W 0x1329 -#define P_HCODEC_CPC_W DOS_REG_ADDR(HCODEC_CPC_W) -#define HCODEC_CINDEX0_REG 0x132a -#define P_HCODEC_CINDEX0_REG DOS_REG_ADDR(HCODEC_CINDEX0_REG) -#define HCODEC_CINDEX1_REG 0x132b -#define P_HCODEC_CINDEX1_REG DOS_REG_ADDR(HCODEC_CINDEX1_REG) -#define HCODEC_CINDEX2_REG 0x132c -#define P_HCODEC_CINDEX2_REG DOS_REG_ADDR(HCODEC_CINDEX2_REG) -#define HCODEC_CINDEX3_REG 0x132d -#define P_HCODEC_CINDEX3_REG DOS_REG_ADDR(HCODEC_CINDEX3_REG) -#define HCODEC_CINDEX4_REG 0x132e -#define P_HCODEC_CINDEX4_REG DOS_REG_ADDR(HCODEC_CINDEX4_REG) -#define HCODEC_CINDEX5_REG 0x132f -#define P_HCODEC_CINDEX5_REG DOS_REG_ADDR(HCODEC_CINDEX5_REG) -#define HCODEC_CINDEX6_REG 0x1330 -#define P_HCODEC_CINDEX6_REG DOS_REG_ADDR(HCODEC_CINDEX6_REG) -#define HCODEC_CINDEX7_REG 0x1331 -#define P_HCODEC_CINDEX7_REG DOS_REG_ADDR(HCODEC_CINDEX7_REG) -#define HCODEC_CMIN_REG 0x1332 -#define P_HCODEC_CMIN_REG DOS_REG_ADDR(HCODEC_CMIN_REG) -#define HCODEC_CMAX_REG 0x1333 -#define P_HCODEC_CMAX_REG DOS_REG_ADDR(HCODEC_CMAX_REG) -#define HCODEC_CBREAK0_REG 0x1334 -#define P_HCODEC_CBREAK0_REG DOS_REG_ADDR(HCODEC_CBREAK0_REG) -#define HCODEC_CBREAK1_REG 0x1335 -#define P_HCODEC_CBREAK1_REG DOS_REG_ADDR(HCODEC_CBREAK1_REG) -#define HCODEC_CBREAK2_REG 0x1336 -#define P_HCODEC_CBREAK2_REG DOS_REG_ADDR(HCODEC_CBREAK2_REG) -#define HCODEC_CBREAK3_REG 0x1337 -#define P_HCODEC_CBREAK3_REG DOS_REG_ADDR(HCODEC_CBREAK3_REG) -#define HCODEC_CBREAK_TYPE 0x1338 -#define P_HCODEC_CBREAK_TYPE DOS_REG_ADDR(HCODEC_CBREAK_TYPE) -#define HCODEC_CBREAK_CTRL 0x1339 -#define P_HCODEC_CBREAK_CTRL DOS_REG_ADDR(HCODEC_CBREAK_CTRL) -#define HCODEC_CBREAK_STAUTS 0x133a -#define P_HCODEC_CBREAK_STAUTS DOS_REG_ADDR(HCODEC_CBREAK_STAUTS) -#define HCODEC_CDB_ADDR_REG 0x133b -#define P_HCODEC_CDB_ADDR_REG DOS_REG_ADDR(HCODEC_CDB_ADDR_REG) -#define HCODEC_CDB_DATA_REG 0x133c -#define P_HCODEC_CDB_DATA_REG DOS_REG_ADDR(HCODEC_CDB_DATA_REG) -#define HCODEC_CDB_CTRL 0x133d -#define P_HCODEC_CDB_CTRL DOS_REG_ADDR(HCODEC_CDB_CTRL) -#define HCODEC_CSFTINT0 0x133e -#define P_HCODEC_CSFTINT0 DOS_REG_ADDR(HCODEC_CSFTINT0) -#define HCODEC_CSFTINT1 0x133f -#define P_HCODEC_CSFTINT1 DOS_REG_ADDR(HCODEC_CSFTINT1) -#define HCODEC_IMEM_DMA_CTRL 0x1340 -#define P_HCODEC_IMEM_DMA_CTRL DOS_REG_ADDR(HCODEC_IMEM_DMA_CTRL) -#define HCODEC_IMEM_DMA_ADR 0x1341 -#define P_HCODEC_IMEM_DMA_ADR DOS_REG_ADDR(HCODEC_IMEM_DMA_ADR) -#define HCODEC_WRRSP_IMEM 0x1343 -#define P_HCODEC_WRRSP_IMEM DOS_REG_ADDR(HCODEC_WRRSP_IMEM) -#define HCODEC_LMEM_DMA_CTRL 0x1350 -#define P_HCODEC_LMEM_DMA_CTRL DOS_REG_ADDR(HCODEC_LMEM_DMA_CTRL) -#define HCODEC_LMEM_DMA_ADR 0x1351 -#define P_HCODEC_LMEM_DMA_ADR DOS_REG_ADDR(HCODEC_LMEM_DMA_ADR) -#define HCODEC_WRRSP_LMEM 0x1353 -#define P_HCODEC_WRRSP_LMEM DOS_REG_ADDR(HCODEC_WRRSP_LMEM) -#define HCODEC_MAC_CTRL1 0x1360 -#define P_HCODEC_MAC_CTRL1 DOS_REG_ADDR(HCODEC_MAC_CTRL1) -#define HCODEC_ACC0REG1 0x1361 -#define P_HCODEC_ACC0REG1 DOS_REG_ADDR(HCODEC_ACC0REG1) -#define HCODEC_ACC1REG1 0x1362 -#define P_HCODEC_ACC1REG1 DOS_REG_ADDR(HCODEC_ACC1REG1) -#define HCODEC_MAC_CTRL2 0x1370 -#define P_HCODEC_MAC_CTRL2 DOS_REG_ADDR(HCODEC_MAC_CTRL2) -#define HCODEC_ACC0REG2 0x1371 -#define P_HCODEC_ACC0REG2 DOS_REG_ADDR(HCODEC_ACC0REG2) -#define HCODEC_ACC1REG2 0x1372 -#define P_HCODEC_ACC1REG2 DOS_REG_ADDR(HCODEC_ACC1REG2) -#define HCODEC_CPU_TRACE 0x1380 -#define P_HCODEC_CPU_TRACE DOS_REG_ADDR(HCODEC_CPU_TRACE) -#define VDEC2_MSP 0x2300 -#define P_VDEC2_MSP DOS_REG_ADDR(VDEC2_MSP) -#define VDEC2_MPSR 0x2301 -#define P_VDEC2_MPSR DOS_REG_ADDR(VDEC2_MPSR) -#define VDEC2_MINT_VEC_BASE 0x2302 -#define P_VDEC2_MINT_VEC_BASE DOS_REG_ADDR(VDEC2_MINT_VEC_BASE) -#define VDEC2_MCPU_INTR_GRP 0x2303 -#define P_VDEC2_MCPU_INTR_GRP DOS_REG_ADDR(VDEC2_MCPU_INTR_GRP) -#define VDEC2_MCPU_INTR_MSK 0x2304 -#define P_VDEC2_MCPU_INTR_MSK DOS_REG_ADDR(VDEC2_MCPU_INTR_MSK) -#define VDEC2_MCPU_INTR_REQ 0x2305 -#define P_VDEC2_MCPU_INTR_REQ DOS_REG_ADDR(VDEC2_MCPU_INTR_REQ) -#define VDEC2_MPC_P 0x2306 -#define P_VDEC2_MPC_P DOS_REG_ADDR(VDEC2_MPC_P) -#define VDEC2_MPC_D 0x2307 -#define P_VDEC2_MPC_D DOS_REG_ADDR(VDEC2_MPC_D) -#define VDEC2_MPC_E 0x2308 -#define P_VDEC2_MPC_E DOS_REG_ADDR(VDEC2_MPC_E) -#define VDEC2_MPC_W 0x2309 -#define P_VDEC2_MPC_W DOS_REG_ADDR(VDEC2_MPC_W) -#define VDEC2_MINDEX0_REG 0x230a -#define P_VDEC2_MINDEX0_REG DOS_REG_ADDR(VDEC2_MINDEX0_REG) -#define VDEC2_MINDEX1_REG 0x230b -#define P_VDEC2_MINDEX1_REG DOS_REG_ADDR(VDEC2_MINDEX1_REG) -#define VDEC2_MINDEX2_REG 0x230c -#define P_VDEC2_MINDEX2_REG DOS_REG_ADDR(VDEC2_MINDEX2_REG) -#define VDEC2_MINDEX3_REG 0x230d -#define P_VDEC2_MINDEX3_REG DOS_REG_ADDR(VDEC2_MINDEX3_REG) -#define VDEC2_MINDEX4_REG 0x230e -#define P_VDEC2_MINDEX4_REG DOS_REG_ADDR(VDEC2_MINDEX4_REG) -#define VDEC2_MINDEX5_REG 0x230f -#define P_VDEC2_MINDEX5_REG DOS_REG_ADDR(VDEC2_MINDEX5_REG) -#define VDEC2_MINDEX6_REG 0x2310 -#define P_VDEC2_MINDEX6_REG DOS_REG_ADDR(VDEC2_MINDEX6_REG) -#define VDEC2_MINDEX7_REG 0x2311 -#define P_VDEC2_MINDEX7_REG DOS_REG_ADDR(VDEC2_MINDEX7_REG) -#define VDEC2_MMIN_REG 0x2312 -#define P_VDEC2_MMIN_REG DOS_REG_ADDR(VDEC2_MMIN_REG) -#define VDEC2_MMAX_REG 0x2313 -#define P_VDEC2_MMAX_REG DOS_REG_ADDR(VDEC2_MMAX_REG) -#define VDEC2_MBREAK0_REG 0x2314 -#define P_VDEC2_MBREAK0_REG DOS_REG_ADDR(VDEC2_MBREAK0_REG) -#define VDEC2_MBREAK1_REG 0x2315 -#define P_VDEC2_MBREAK1_REG DOS_REG_ADDR(VDEC2_MBREAK1_REG) -#define VDEC2_MBREAK2_REG 0x2316 -#define P_VDEC2_MBREAK2_REG DOS_REG_ADDR(VDEC2_MBREAK2_REG) -#define VDEC2_MBREAK3_REG 0x2317 -#define P_VDEC2_MBREAK3_REG DOS_REG_ADDR(VDEC2_MBREAK3_REG) -#define VDEC2_MBREAK_TYPE 0x2318 -#define P_VDEC2_MBREAK_TYPE DOS_REG_ADDR(VDEC2_MBREAK_TYPE) -#define VDEC2_MBREAK_CTRL 0x2319 -#define P_VDEC2_MBREAK_CTRL DOS_REG_ADDR(VDEC2_MBREAK_CTRL) -#define VDEC2_MBREAK_STAUTS 0x231a -#define P_VDEC2_MBREAK_STAUTS DOS_REG_ADDR(VDEC2_MBREAK_STAUTS) -#define VDEC2_MDB_ADDR_REG 0x231b -#define P_VDEC2_MDB_ADDR_REG DOS_REG_ADDR(VDEC2_MDB_ADDR_REG) -#define VDEC2_MDB_DATA_REG 0x231c -#define P_VDEC2_MDB_DATA_REG DOS_REG_ADDR(VDEC2_MDB_DATA_REG) -#define VDEC2_MDB_CTRL 0x231d -#define P_VDEC2_MDB_CTRL DOS_REG_ADDR(VDEC2_MDB_CTRL) -#define VDEC2_MSFTINT0 0x231e -#define P_VDEC2_MSFTINT0 DOS_REG_ADDR(VDEC2_MSFTINT0) -#define VDEC2_MSFTINT1 0x231f -#define P_VDEC2_MSFTINT1 DOS_REG_ADDR(VDEC2_MSFTINT1) -#define VDEC2_CSP 0x2320 -#define P_VDEC2_CSP DOS_REG_ADDR(VDEC2_CSP) -#define VDEC2_CPSR 0x2321 -#define P_VDEC2_CPSR DOS_REG_ADDR(VDEC2_CPSR) -#define VDEC2_CINT_VEC_BASE 0x2322 -#define P_VDEC2_CINT_VEC_BASE DOS_REG_ADDR(VDEC2_CINT_VEC_BASE) -#define VDEC2_CCPU_INTR_GRP 0x2323 -#define P_VDEC2_CCPU_INTR_GRP DOS_REG_ADDR(VDEC2_CCPU_INTR_GRP) -#define VDEC2_CCPU_INTR_MSK 0x2324 -#define P_VDEC2_CCPU_INTR_MSK DOS_REG_ADDR(VDEC2_CCPU_INTR_MSK) -#define VDEC2_CCPU_INTR_REQ 0x2325 -#define P_VDEC2_CCPU_INTR_REQ DOS_REG_ADDR(VDEC2_CCPU_INTR_REQ) -#define VDEC2_CPC_P 0x2326 -#define P_VDEC2_CPC_P DOS_REG_ADDR(VDEC2_CPC_P) -#define VDEC2_CPC_D 0x2327 -#define P_VDEC2_CPC_D DOS_REG_ADDR(VDEC2_CPC_D) -#define VDEC2_CPC_E 0x2328 -#define P_VDEC2_CPC_E DOS_REG_ADDR(VDEC2_CPC_E) -#define VDEC2_CPC_W 0x2329 -#define P_VDEC2_CPC_W DOS_REG_ADDR(VDEC2_CPC_W) -#define VDEC2_CINDEX0_REG 0x232a -#define P_VDEC2_CINDEX0_REG DOS_REG_ADDR(VDEC2_CINDEX0_REG) -#define VDEC2_CINDEX1_REG 0x232b -#define P_VDEC2_CINDEX1_REG DOS_REG_ADDR(VDEC2_CINDEX1_REG) -#define VDEC2_CINDEX2_REG 0x232c -#define P_VDEC2_CINDEX2_REG DOS_REG_ADDR(VDEC2_CINDEX2_REG) -#define VDEC2_CINDEX3_REG 0x232d -#define P_VDEC2_CINDEX3_REG DOS_REG_ADDR(VDEC2_CINDEX3_REG) -#define VDEC2_CINDEX4_REG 0x232e -#define P_VDEC2_CINDEX4_REG DOS_REG_ADDR(VDEC2_CINDEX4_REG) -#define VDEC2_CINDEX5_REG 0x232f -#define P_VDEC2_CINDEX5_REG DOS_REG_ADDR(VDEC2_CINDEX5_REG) -#define VDEC2_CINDEX6_REG 0x2330 -#define P_VDEC2_CINDEX6_REG DOS_REG_ADDR(VDEC2_CINDEX6_REG) -#define VDEC2_CINDEX7_REG 0x2331 -#define P_VDEC2_CINDEX7_REG DOS_REG_ADDR(VDEC2_CINDEX7_REG) -#define VDEC2_CMIN_REG 0x2332 -#define P_VDEC2_CMIN_REG DOS_REG_ADDR(VDEC2_CMIN_REG) -#define VDEC2_CMAX_REG 0x2333 -#define P_VDEC2_CMAX_REG DOS_REG_ADDR(VDEC2_CMAX_REG) -#define VDEC2_CBREAK0_REG 0x2334 -#define P_VDEC2_CBREAK0_REG DOS_REG_ADDR(VDEC2_CBREAK0_REG) -#define VDEC2_CBREAK1_REG 0x2335 -#define P_VDEC2_CBREAK1_REG DOS_REG_ADDR(VDEC2_CBREAK1_REG) -#define VDEC2_CBREAK2_REG 0x2336 -#define P_VDEC2_CBREAK2_REG DOS_REG_ADDR(VDEC2_CBREAK2_REG) -#define VDEC2_CBREAK3_REG 0x2337 -#define P_VDEC2_CBREAK3_REG DOS_REG_ADDR(VDEC2_CBREAK3_REG) -#define VDEC2_CBREAK_TYPE 0x2338 -#define P_VDEC2_CBREAK_TYPE DOS_REG_ADDR(VDEC2_CBREAK_TYPE) -#define VDEC2_CBREAK_CTRL 0x2339 -#define P_VDEC2_CBREAK_CTRL DOS_REG_ADDR(VDEC2_CBREAK_CTRL) -#define VDEC2_CBREAK_STAUTS 0x233a -#define P_VDEC2_CBREAK_STAUTS DOS_REG_ADDR(VDEC2_CBREAK_STAUTS) -#define VDEC2_CDB_ADDR_REG 0x233b -#define P_VDEC2_CDB_ADDR_REG DOS_REG_ADDR(VDEC2_CDB_ADDR_REG) -#define VDEC2_CDB_DATA_REG 0x233c -#define P_VDEC2_CDB_DATA_REG DOS_REG_ADDR(VDEC2_CDB_DATA_REG) -#define VDEC2_CDB_CTRL 0x233d -#define P_VDEC2_CDB_CTRL DOS_REG_ADDR(VDEC2_CDB_CTRL) -#define VDEC2_CSFTINT0 0x233e -#define P_VDEC2_CSFTINT0 DOS_REG_ADDR(VDEC2_CSFTINT0) -#define VDEC2_CSFTINT1 0x233f -#define P_VDEC2_CSFTINT1 DOS_REG_ADDR(VDEC2_CSFTINT1) -#define VDEC2_IMEM_DMA_CTRL 0x2340 -#define P_VDEC2_IMEM_DMA_CTRL DOS_REG_ADDR(VDEC2_IMEM_DMA_CTRL) -#define VDEC2_IMEM_DMA_ADR 0x2341 -#define P_VDEC2_IMEM_DMA_ADR DOS_REG_ADDR(VDEC2_IMEM_DMA_ADR) -#define VDEC2_IMEM_DMA_COUNT 0x2342 -#define P_VDEC2_IMEM_DMA_COUNT DOS_REG_ADDR(VDEC2_IMEM_DMA_COUNT) -#define VDEC2_WRRSP_IMEM 0x2343 -#define P_VDEC2_WRRSP_IMEM DOS_REG_ADDR(VDEC2_WRRSP_IMEM) -#define VDEC2_LMEM_DMA_CTRL 0x2350 -#define P_VDEC2_LMEM_DMA_CTRL DOS_REG_ADDR(VDEC2_LMEM_DMA_CTRL) -#define VDEC2_LMEM_DMA_ADR 0x2351 -#define P_VDEC2_LMEM_DMA_ADR DOS_REG_ADDR(VDEC2_LMEM_DMA_ADR) -#define VDEC2_LMEM_DMA_COUNT 0x2352 -#define P_VDEC2_LMEM_DMA_COUNT DOS_REG_ADDR(VDEC2_LMEM_DMA_COUNT) -#define VDEC2_WRRSP_LMEM 0x2353 -#define P_VDEC2_WRRSP_LMEM DOS_REG_ADDR(VDEC2_WRRSP_LMEM) -#define VDEC2_MAC_CTRL1 0x2360 -#define P_VDEC2_MAC_CTRL1 DOS_REG_ADDR(VDEC2_MAC_CTRL1) -#define VDEC2_ACC0REG1 0x2361 -#define P_VDEC2_ACC0REG1 DOS_REG_ADDR(VDEC2_ACC0REG1) -#define VDEC2_ACC1REG1 0x2362 -#define P_VDEC2_ACC1REG1 DOS_REG_ADDR(VDEC2_ACC1REG1) -#define VDEC2_MAC_CTRL2 0x2370 -#define P_VDEC2_MAC_CTRL2 DOS_REG_ADDR(VDEC2_MAC_CTRL2) -#define VDEC2_ACC0REG2 0x2371 -#define P_VDEC2_ACC0REG2 DOS_REG_ADDR(VDEC2_ACC0REG2) -#define VDEC2_ACC1REG2 0x2372 -#define P_VDEC2_ACC1REG2 DOS_REG_ADDR(VDEC2_ACC1REG2) -#define VDEC2_CPU_TRACE 0x2380 -#define P_VDEC2_CPU_TRACE DOS_REG_ADDR(VDEC2_CPU_TRACE) -/*add from M8M2*/ -#define HEVC_MSP 0x3300 -#define P_HEVC_MSP DOS_REG_ADDR(HEVC_MSP) -#define HEVC_MPSR 0x3301 -#define P_HEVC_MPSR DOS_REG_ADDR(HEVC_MPSR) -#define HEVC_MINT_VEC_BASE 0x3302 -#define P_HEVC_MINT_VEC_BASE DOS_REG_ADDR(HEVC_MINT_VEC_BASE) -#define HEVC_MCPU_INTR_GRP 0x3303 -#define P_HEVC_MCPU_INTR_GRP DOS_REG_ADDR(HEVC_MCPU_INTR_GRP) -#define HEVC_MCPU_INTR_MSK 0x3304 -#define P_HEVC_MCPU_INTR_MSK DOS_REG_ADDR(HEVC_MCPU_INTR_MSK) -#define HEVC_MCPU_INTR_REQ 0x3305 -#define P_HEVC_MCPU_INTR_REQ DOS_REG_ADDR(HEVC_MCPU_INTR_REQ) -#define HEVC_MPC_P 0x3306 -#define P_HEVC_MPC_P DOS_REG_ADDR(HEVC_MPC_P) -#define HEVC_MPC_D 0x3307 -#define P_HEVC_MPC_D DOS_REG_ADDR(HEVC_MPC_D) -#define HEVC_MPC_E 0x3308 -#define P_HEVC_MPC_E DOS_REG_ADDR(HEVC_MPC_E) -#define HEVC_MPC_W 0x3309 -#define P_HEVC_MPC_W DOS_REG_ADDR(HEVC_MPC_W) -#define HEVC_MINDEX0_REG 0x330a -#define P_HEVC_MINDEX0_REG DOS_REG_ADDR(HEVC_MINDEX0_REG) -#define HEVC_MINDEX1_REG 0x330b -#define P_HEVC_MINDEX1_REG DOS_REG_ADDR(HEVC_MINDEX1_REG) -#define HEVC_MINDEX2_REG 0x330c -#define P_HEVC_MINDEX2_REG DOS_REG_ADDR(HEVC_MINDEX2_REG) -#define HEVC_MINDEX3_REG 0x330d -#define P_HEVC_MINDEX3_REG DOS_REG_ADDR(HEVC_MINDEX3_REG) -#define HEVC_MINDEX4_REG 0x330e -#define P_HEVC_MINDEX4_REG DOS_REG_ADDR(HEVC_MINDEX4_REG) -#define HEVC_MINDEX5_REG 0x330f -#define P_HEVC_MINDEX5_REG DOS_REG_ADDR(HEVC_MINDEX5_REG) -#define HEVC_MINDEX6_REG 0x3310 -#define P_HEVC_MINDEX6_REG DOS_REG_ADDR(HEVC_MINDEX6_REG) -#define HEVC_MINDEX7_REG 0x3311 -#define P_HEVC_MINDEX7_REG DOS_REG_ADDR(HEVC_MINDEX7_REG) -#define HEVC_MMIN_REG 0x3312 -#define P_HEVC_MMIN_REG DOS_REG_ADDR(HEVC_MMIN_REG) -#define HEVC_MMAX_REG 0x3313 -#define P_HEVC_MMAX_REG DOS_REG_ADDR(HEVC_MMAX_REG) -#define HEVC_MBREAK0_REG 0x3314 -#define P_HEVC_MBREAK0_REG DOS_REG_ADDR(HEVC_MBREAK0_REG) -#define HEVC_MBREAK1_REG 0x3315 -#define P_HEVC_MBREAK1_REG DOS_REG_ADDR(HEVC_MBREAK1_REG) -#define HEVC_MBREAK2_REG 0x3316 -#define P_HEVC_MBREAK2_REG DOS_REG_ADDR(HEVC_MBREAK2_REG) -#define HEVC_MBREAK3_REG 0x3317 -#define P_HEVC_MBREAK3_REG DOS_REG_ADDR(HEVC_MBREAK3_REG) -#define HEVC_MBREAK_TYPE 0x3318 -#define P_HEVC_MBREAK_TYPE DOS_REG_ADDR(HEVC_MBREAK_TYPE) -#define HEVC_MBREAK_CTRL 0x3319 -#define P_HEVC_MBREAK_CTRL DOS_REG_ADDR(HEVC_MBREAK_CTRL) -#define HEVC_MBREAK_STAUTS 0x331a -#define P_HEVC_MBREAK_STAUTS DOS_REG_ADDR(HEVC_MBREAK_STAUTS) -#define HEVC_MDB_ADDR_REG 0x331b -#define P_HEVC_MDB_ADDR_REG DOS_REG_ADDR(HEVC_MDB_ADDR_REG) -#define HEVC_MDB_DATA_REG 0x331c -#define P_HEVC_MDB_DATA_REG DOS_REG_ADDR(HEVC_MDB_DATA_REG) -#define HEVC_MDB_CTRL 0x331d -#define P_HEVC_MDB_CTRL DOS_REG_ADDR(HEVC_MDB_CTRL) -#define HEVC_MSFTINT0 0x331e -#define P_HEVC_MSFTINT0 DOS_REG_ADDR(HEVC_MSFTINT0) -#define HEVC_MSFTINT1 0x331f -#define P_HEVC_MSFTINT1 DOS_REG_ADDR(HEVC_MSFTINT1) -#define HEVC_CSP 0x3320 -#define P_HEVC_CSP DOS_REG_ADDR(HEVC_CSP) -#define HEVC_CPSR 0x3321 -#define P_HEVC_CPSR DOS_REG_ADDR(HEVC_CPSR) -#define HEVC_CINT_VEC_BASE 0x3322 -#define P_HEVC_CINT_VEC_BASE DOS_REG_ADDR(HEVC_CINT_VEC_BASE) -#define HEVC_CCPU_INTR_GRP 0x3323 -#define P_HEVC_CCPU_INTR_GRP DOS_REG_ADDR(HEVC_CCPU_INTR_GRP) -#define HEVC_CCPU_INTR_MSK 0x3324 -#define P_HEVC_CCPU_INTR_MSK DOS_REG_ADDR(HEVC_CCPU_INTR_MSK) -#define HEVC_CCPU_INTR_REQ 0x3325 -#define P_HEVC_CCPU_INTR_REQ DOS_REG_ADDR(HEVC_CCPU_INTR_REQ) -#define HEVC_CPC_P 0x3326 -#define P_HEVC_CPC_P DOS_REG_ADDR(HEVC_CPC_P) -#define HEVC_CPC_D 0x3327 -#define P_HEVC_CPC_D DOS_REG_ADDR(HEVC_CPC_D) -#define HEVC_CPC_E 0x3328 -#define P_HEVC_CPC_E DOS_REG_ADDR(HEVC_CPC_E) -#define HEVC_CPC_W 0x3329 -#define P_HEVC_CPC_W DOS_REG_ADDR(HEVC_CPC_W) -#define HEVC_CINDEX0_REG 0x332a -#define P_HEVC_CINDEX0_REG DOS_REG_ADDR(HEVC_CINDEX0_REG) -#define HEVC_CINDEX1_REG 0x332b -#define P_HEVC_CINDEX1_REG DOS_REG_ADDR(HEVC_CINDEX1_REG) -#define HEVC_CINDEX2_REG 0x332c -#define P_HEVC_CINDEX2_REG DOS_REG_ADDR(HEVC_CINDEX2_REG) -#define HEVC_CINDEX3_REG 0x332d -#define P_HEVC_CINDEX3_REG DOS_REG_ADDR(HEVC_CINDEX3_REG) -#define HEVC_CINDEX4_REG 0x332e -#define P_HEVC_CINDEX4_REG DOS_REG_ADDR(HEVC_CINDEX4_REG) -#define HEVC_CINDEX5_REG 0x332f -#define P_HEVC_CINDEX5_REG DOS_REG_ADDR(HEVC_CINDEX5_REG) -#define HEVC_CINDEX6_REG 0x3330 -#define P_HEVC_CINDEX6_REG DOS_REG_ADDR(HEVC_CINDEX6_REG) -#define HEVC_CINDEX7_REG 0x3331 -#define P_HEVC_CINDEX7_REG DOS_REG_ADDR(HEVC_CINDEX7_REG) -#define HEVC_CMIN_REG 0x3332 -#define P_HEVC_CMIN_REG DOS_REG_ADDR(HEVC_CMIN_REG) -#define HEVC_CMAX_REG 0x3333 -#define P_HEVC_CMAX_REG DOS_REG_ADDR(HEVC_CMAX_REG) -#define HEVC_CBREAK0_REG 0x3334 -#define P_HEVC_CBREAK0_REG DOS_REG_ADDR(HEVC_CBREAK0_REG) -#define HEVC_CBREAK1_REG 0x3335 -#define P_HEVC_CBREAK1_REG DOS_REG_ADDR(HEVC_CBREAK1_REG) -#define HEVC_CBREAK2_REG 0x3336 -#define P_HEVC_CBREAK2_REG DOS_REG_ADDR(HEVC_CBREAK2_REG) -#define HEVC_CBREAK3_REG 0x3337 -#define P_HEVC_CBREAK3_REG DOS_REG_ADDR(HEVC_CBREAK3_REG) -#define HEVC_CBREAK_TYPE 0x3338 -#define P_HEVC_CBREAK_TYPE DOS_REG_ADDR(HEVC_CBREAK_TYPE) -#define HEVC_CBREAK_CTRL 0x3339 -#define P_HEVC_CBREAK_CTRL DOS_REG_ADDR(HEVC_CBREAK_CTRL) -#define HEVC_CBREAK_STAUTS 0x333a -#define P_HEVC_CBREAK_STAUTS DOS_REG_ADDR(HEVC_CBREAK_STAUTS) -#define HEVC_CDB_ADDR_REG 0x333b -#define P_HEVC_CDB_ADDR_REG DOS_REG_ADDR(HEVC_CDB_ADDR_REG) -#define HEVC_CDB_DATA_REG 0x333c -#define P_HEVC_CDB_DATA_REG DOS_REG_ADDR(HEVC_CDB_DATA_REG) -#define HEVC_CDB_CTRL 0x333d -#define P_HEVC_CDB_CTRL DOS_REG_ADDR(HEVC_CDB_CTRL) -#define HEVC_CSFTINT0 0x333e -#define P_HEVC_CSFTINT0 DOS_REG_ADDR(HEVC_CSFTINT0) -#define HEVC_CSFTINT1 0x333f -#define P_HEVC_CSFTINT1 DOS_REG_ADDR(HEVC_CSFTINT1) -#define HEVC_IMEM_DMA_CTRL 0x3340 -#define P_HEVC_IMEM_DMA_CTRL DOS_REG_ADDR(HEVC_IMEM_DMA_CTRL) -#define HEVC_IMEM_DMA_ADR 0x3341 -#define P_HEVC_IMEM_DMA_ADR DOS_REG_ADDR(HEVC_IMEM_DMA_ADR) -#define HEVC_IMEM_DMA_COUNT 0x3342 -#define P_HEVC_IMEM_DMA_COUNT DOS_REG_ADDR(HEVC_IMEM_DMA_COUNT) -#define HEVC_WRRSP_IMEM 0x3343 -#define P_HEVC_WRRSP_IMEM DOS_REG_ADDR(HEVC_WRRSP_IMEM) -#define HEVC_LMEM_DMA_CTRL 0x3350 -#define P_HEVC_LMEM_DMA_CTRL DOS_REG_ADDR(HEVC_LMEM_DMA_CTRL) -#define HEVC_LMEM_DMA_ADR 0x3351 -#define P_HEVC_LMEM_DMA_ADR DOS_REG_ADDR(HEVC_LMEM_DMA_ADR) -#define HEVC_LMEM_DMA_COUNT 0x3352 -#define P_HEVC_LMEM_DMA_COUNT DOS_REG_ADDR(HEVC_LMEM_DMA_COUNT) -#define HEVC_WRRSP_LMEM 0x3353 -#define P_HEVC_WRRSP_LMEM DOS_REG_ADDR(HEVC_WRRSP_LMEM) -#define HEVC_MAC_CTRL1 0x3360 -#define P_HEVC_MAC_CTRL1 DOS_REG_ADDR(HEVC_MAC_CTRL1) -#define HEVC_ACC0REG1 0x3361 -#define P_HEVC_ACC0REG1 DOS_REG_ADDR(HEVC_ACC0REG1) -#define HEVC_ACC1REG1 0x3362 -#define P_HEVC_ACC1REG1 DOS_REG_ADDR(HEVC_ACC1REG1) -#define HEVC_MAC_CTRL2 0x3370 -#define P_HEVC_MAC_CTRL2 DOS_REG_ADDR(HEVC_MAC_CTRL2) -#define HEVC_ACC0REG2 0x3371 -#define P_HEVC_ACC0REG2 DOS_REG_ADDR(HEVC_ACC0REG2) -#define HEVC_ACC1REG2 0x3372 -#define P_HEVC_ACC1REG2 DOS_REG_ADDR(HEVC_ACC1REG2) -#define HEVC_CPU_TRACE 0x3380 -#define P_HEVC_CPU_TRACE DOS_REG_ADDR(HEVC_CPU_TRACE) -/**/ -#define HCODEC_VLC_MB_INFO 0x1d35 -#define P_HCODEC_VLC_MB_INFO DOS_REG_ADDR(HCODEC_VLC_MB_INFO) -#define HCODEC_VLC_ENC_PEND_CMD 0x1d36 - -#define HCODEC_VLC_DC_RD_REQ 0x1d45 -#define P_HCODEC_VLC_DC_RD_REQ DOS_REG_ADDR(HCODEC_VLC_DC_RD_REQ) -#define HCODEC_VLC_DC 0x1d46 -#define P_HCODEC_VLC_DC DOS_REG_ADDR(HCODEC_VLC_DC) -#define HCODEC_VLC_DC_INFO 0x1d47 -#define P_HCODEC_VLC_DC_INFO DOS_REG_ADDR(HCODEC_VLC_DC_INFO) -#define HCODEC_VLC_MV_INDEX 0x1d48 -#define P_HCODEC_VLC_MV_INDEX DOS_REG_ADDR(HCODEC_VLC_MV_INDEX) -#define HCODEC_VLC_MV 0x1d49 -#define P_HCODEC_VLC_MV DOS_REG_ADDR(HCODEC_VLC_MV) -#define HCODEC_HENC_TOP_MV_0 0x1d4a -#define P_HCODEC_HENC_TOP_MV_0 DOS_REG_ADDR(HCODEC_HENC_TOP_MV_0) -#define HCODEC_HENC_TOP_MV_1 0x1d4b -#define P_HCODEC_HENC_TOP_MV_1 DOS_REG_ADDR(HCODEC_HENC_TOP_MV_1) -#define HCODEC_HENC_TOP_MV_2 0x1d4c -#define P_HCODEC_HENC_TOP_MV_2 DOS_REG_ADDR(HCODEC_HENC_TOP_MV_2) -#define HCODEC_HENC_TOP_MV_3 0x1d4d -#define P_HCODEC_HENC_TOP_MV_3 DOS_REG_ADDR(HCODEC_HENC_TOP_MV_3) -#define HCODEC_HENC_LEFT_MV_0 0x1d4e - -/*add from M8M2*/ -#define HCODEC_QDCT_I_PRED_REF_WR_IDX 0x1f32 -#define P_HCODEC_QDCT_I_PRED_REF_WR_IDX \ - DOS_REG_ADDR(HCODEC_QDCT_I_PRED_REF_WR_IDX) -#define HCODEC_QDCT_I_PRED_REF_WR_DATA 0x1f33 -#define P_HCODEC_QDCT_I_PRED_REF_WR_DATA \ - DOS_REG_ADDR(HCODEC_QDCT_I_PRED_REF_WR_DATA) -/**/ -#define HCODEC_IE_CONTROL 0x1f40 -#define P_HCODEC_IE_CONTROL DOS_REG_ADDR(HCODEC_IE_CONTROL) -#define HCODEC_IE_MB_POSITION 0x1f41 -#define P_HCODEC_IE_MB_POSITION \ - DOS_REG_ADDR(HCODEC_IE_MB_POSITION) -#define HCODEC_IE_ME_MB_INFO 0x1f42 -#define P_HCODEC_IE_ME_MB_INFO DOS_REG_ADDR(HCODEC_IE_ME_MB_INFO) -#define HCODEC_SAD_CONTROL 0x1f43 -#define P_HCODEC_SAD_CONTROL DOS_REG_ADDR(HCODEC_SAD_CONTROL) -#define HCODEC_IE_I4_PRED_MODE_HI 0x1f45 -#define P_HCODEC_IE_I4_PRED_MODE_HI \ - DOS_REG_ADDR(HCODEC_IE_I4_PRED_MODE_HI) -#define HCODEC_IE_I4_PRED_MODE_LO 0x1f46 -#define P_HCODEC_IE_I4_PRED_MODE_LO \ - DOS_REG_ADDR(HCODEC_IE_I4_PRED_MODE_LO) -#define HCODEC_IE_C_PRED_MODE 0x1f47 -#define P_HCODEC_IE_C_PRED_MODE \ - DOS_REG_ADDR(HCODEC_IE_C_PRED_MODE) -#define HCODEC_IE_CUR_REF_SEL 0x1f48 -#define P_HCODEC_IE_CUR_REF_SEL \ - DOS_REG_ADDR(HCODEC_IE_CUR_REF_SEL) -#define HCODEC_ME_CONTROL 0x1f49 -#define P_HCODEC_ME_CONTROL DOS_REG_ADDR(HCODEC_ME_CONTROL) -#define HCODEC_ME_START_POSITION 0x1f4a -#define P_HCODEC_ME_START_POSITION \ - DOS_REG_ADDR(HCODEC_ME_START_POSITION) -#define HCODEC_ME_STATUS 0x1f4b -#define P_HCODEC_ME_STATUS DOS_REG_ADDR(HCODEC_ME_STATUS) -#define HCODEC_ME_DEBUG 0x1f4c -#define P_HCODEC_ME_DEBUG DOS_REG_ADDR(HCODEC_ME_DEBUG) -#define HCODEC_ME_SKIP_LINE 0x1f4d -#define P_HCODEC_ME_SKIP_LINE DOS_REG_ADDR(HCODEC_ME_SKIP_LINE) -#define HCODEC_ME_AB_MEM_CTL 0x1f4e -#define P_HCODEC_ME_AB_MEM_CTL DOS_REG_ADDR(HCODEC_ME_AB_MEM_CTL) -#define HCODEC_ME_PIC_INFO 0x1f4f -#define P_HCODEC_ME_PIC_INFO DOS_REG_ADDR(HCODEC_ME_PIC_INFO) -#define HCODEC_ME_SAD_ENOUGH_01 0x1f50 -#define P_HCODEC_ME_SAD_ENOUGH_01 \ - DOS_REG_ADDR(HCODEC_ME_SAD_ENOUGH_01) -#define HCODEC_ME_SAD_ENOUGH_23 0x1f51 -#define P_HCODEC_ME_SAD_ENOUGH_23 \ - DOS_REG_ADDR(HCODEC_ME_SAD_ENOUGH_23) -#define HCODEC_ME_STEP0_CLOSE_MV 0x1f52 -#define P_HCODEC_ME_STEP0_CLOSE_MV \ - DOS_REG_ADDR(HCODEC_ME_STEP0_CLOSE_MV) -#define HCODEC_ME_F_SKIP_SAD 0x1f53 -#define P_HCODEC_ME_F_SKIP_SAD \ - DOS_REG_ADDR(HCODEC_ME_F_SKIP_SAD) -#define HCODEC_ME_F_SKIP_WEIGHT 0x1f54 -#define P_HCODEC_ME_F_SKIP_WEIGHT \ - DOS_REG_ADDR(HCODEC_ME_F_SKIP_WEIGHT) -#define HCODEC_ME_MV_MERGE_CTL 0x1f55 -#define P_HCODEC_ME_MV_MERGE_CTL \ - DOS_REG_ADDR(HCODEC_ME_MV_MERGE_CTL) -#define HCODEC_ME_MV_WEIGHT_01 0x1f56 -#define P_HCODEC_ME_MV_WEIGHT_01 \ - DOS_REG_ADDR(HCODEC_ME_MV_WEIGHT_01) -#define HCODEC_ME_MV_WEIGHT_23 0x1f57 -#define P_HCODEC_ME_MV_WEIGHT_23 \ - DOS_REG_ADDR(HCODEC_ME_MV_WEIGHT_23) -#define HCODEC_ME_SAD_RANGE_INC 0x1f58 -#define P_HCODEC_ME_SAD_RANGE_INC \ - DOS_REG_ADDR(HCODEC_ME_SAD_RANGE_INC) -#define HCODEC_ME_SUB_MERGE_CTL 0x1f59 -#define P_HCODEC_ME_SUB_MERGE_CTL \ - DOS_REG_ADDR(HCODEC_ME_SUB_MERGE_CTL) -#define HCODEC_ME_SUB_REF_MV_CTL 0x1f5a -#define P_HCODEC_ME_SUB_REF_MV_CTL \ - DOS_REG_ADDR(HCODEC_ME_SUB_REF_MV_CTL) -#define HCODEC_ME_SUB_ANY_WEIGHT_SAD 0x1f5b -#define P_HCODEC_ME_SUB_ANY_WEIGHT_SAD \ - DOS_REG_ADDR(HCODEC_ME_SUB_ANY_WEIGHT_SAD) -#define HCODEC_ME_SUB_FIX_SAD 0x1f5c -#define P_HCODEC_ME_SUB_FIX_SAD \ - DOS_REG_ADDR(HCODEC_ME_SUB_FIX_SAD) -#define HCODEC_ME_SUB_FIX_MIN_SAD 0x1f5d -#define P_HCODEC_ME_SUB_FIX_MIN_SAD \ - DOS_REG_ADDR(HCODEC_ME_SUB_FIX_MIN_SAD) -#define HCODEC_ME_SUB_SNAP_GLITCH 0x1f5e -#define P_HCODEC_ME_SUB_SNAP_GLITCH \ - DOS_REG_ADDR(HCODEC_ME_SUB_SNAP_GLITCH) -#define HCODEC_ME_SUB_ACT_CTL 0x1f5f -#define P_HCODEC_ME_SUB_ACT_CTL \ - DOS_REG_ADDR(HCODEC_ME_SUB_ACT_CTL) -#define AO_RTI_STATUS_REG0 ((0x00 << 10) | (0x00 << 2)) -#define P_AO_RTI_STATUS_REG0 AOBUS_REG_ADDR(AO_RTI_STATUS_REG0) -#define AO_RTI_STATUS_REG1 ((0x00 << 10) | (0x01 << 2)) -#define P_AO_RTI_STATUS_REG1 AOBUS_REG_ADDR(AO_RTI_STATUS_REG1) -#define AO_RTI_STATUS_REG2 ((0x00 << 10) | (0x02 << 2)) -#define P_AO_RTI_STATUS_REG2 AOBUS_REG_ADDR(AO_RTI_STATUS_REG2) -#define AO_RTI_PWR_CNTL_REG1 ((0x00 << 10) | (0x03 << 2)) -#define P_AO_RTI_PWR_CNTL_REG1 AOBUS_REG_ADDR(AO_RTI_PWR_CNTL_REG1) -#define AO_RTI_PWR_CNTL_REG0 ((0x00 << 10) | (0x04 << 2)) -#define P_AO_RTI_PWR_CNTL_REG0 AOBUS_REG_ADDR(AO_RTI_PWR_CNTL_REG0) -#define AO_RTI_PIN_MUX_REG ((0x00 << 10) | (0x05 << 2)) -#define P_AO_RTI_PIN_MUX_REG AOBUS_REG_ADDR(AO_RTI_PIN_MUX_REG) -#define AO_WD_GPIO_REG ((0x00 << 10) | (0x06 << 2)) -#define P_AO_WD_GPIO_REG AOBUS_REG_ADDR(AO_WD_GPIO_REG) -#define AO_REMAP_REG0 ((0x00 << 10) | (0x07 << 2)) -#define P_AO_REMAP_REG0 AOBUS_REG_ADDR(AO_REMAP_REG0) -#define AO_REMAP_REG1 ((0x00 << 10) | (0x08 << 2)) -#define P_AO_REMAP_REG1 AOBUS_REG_ADDR(AO_REMAP_REG1) -#define AO_GPIO_O_EN_N ((0x00 << 10) | (0x09 << 2)) -#define P_AO_GPIO_O_EN_N AOBUS_REG_ADDR(AO_GPIO_O_EN_N) -#define AO_GPIO_I ((0x00 << 10) | (0x0A << 2)) -#define P_AO_GPIO_I AOBUS_REG_ADDR(AO_GPIO_I) -#define AO_RTI_PULL_UP_REG ((0x00 << 10) | (0x0B << 2)) -#define P_AO_RTI_PULL_UP_REG AOBUS_REG_ADDR(AO_RTI_PULL_UP_REG) -#define AO_RTI_WD_MARK ((0x00 << 10) | (0x0D << 2)) -#define P_AO_RTI_WD_MARK AOBUS_REG_ADDR(AO_RTI_WD_MARK) -#define AO_CPU_CNTL ((0x00 << 10) | (0x0E << 2)) -#define P_AO_CPU_CNTL AOBUS_REG_ADDR(AO_CPU_CNTL) -#define AO_CPU_STAT ((0x00 << 10) | (0x0F << 2)) -#define P_AO_CPU_STAT AOBUS_REG_ADDR(AO_CPU_STAT) -#define AO_RTI_GEN_CNTL_REG0 ((0x00 << 10) | (0x10 << 2)) -#define P_AO_RTI_GEN_CNTL_REG0 AOBUS_REG_ADDR(AO_RTI_GEN_CNTL_REG0) -#define AO_WATCHDOG_REG ((0x00 << 10) | (0x11 << 2)) -#define P_AO_WATCHDOG_REG AOBUS_REG_ADDR(AO_WATCHDOG_REG) -#define AO_WATCHDOG_RESET ((0x00 << 10) | (0x12 << 2)) -#define P_AO_WATCHDOG_RESET AOBUS_REG_ADDR(AO_WATCHDOG_RESET) -#define AO_TIMER_REG ((0x00 << 10) | (0x13 << 2)) -#define P_AO_TIMER_REG AOBUS_REG_ADDR(AO_TIMER_REG) -#define AO_TIMERA_REG ((0x00 << 10) | (0x14 << 2)) -#define P_AO_TIMERA_REG AOBUS_REG_ADDR(AO_TIMERA_REG) -#define AO_TIMERE_REG ((0x00 << 10) | (0x15 << 2)) -#define P_AO_TIMERE_REG AOBUS_REG_ADDR(AO_TIMERE_REG) -#define AO_AHB2DDR_CNTL ((0x00 << 10) | (0x18 << 2)) -#define P_AO_AHB2DDR_CNTL AOBUS_REG_ADDR(AO_AHB2DDR_CNTL) -#define AO_IRQ_MASK_FIQ_SEL ((0x00 << 10) | (0x20 << 2)) -#define P_AO_IRQ_MASK_FIQ_SEL AOBUS_REG_ADDR(AO_IRQ_MASK_FIQ_SEL) -#define AO_IRQ_GPIO_REG ((0x00 << 10) | (0x21 << 2)) -#define P_AO_IRQ_GPIO_REG AOBUS_REG_ADDR(AO_IRQ_GPIO_REG) -#define AO_IRQ_STAT ((0x00 << 10) | (0x22 << 2)) -#define P_AO_IRQ_STAT AOBUS_REG_ADDR(AO_IRQ_STAT) -#define AO_IRQ_STAT_CLR ((0x00 << 10) | (0x23 << 2)) -#define P_AO_IRQ_STAT_CLR AOBUS_REG_ADDR(AO_IRQ_STAT_CLR) -#define AO_DEBUG_REG0 ((0x00 << 10) | (0x28 << 2)) -#define P_AO_DEBUG_REG0 AOBUS_REG_ADDR(AO_DEBUG_REG0) -#define AO_DEBUG_REG1 ((0x00 << 10) | (0x29 << 2)) -#define P_AO_DEBUG_REG1 AOBUS_REG_ADDR(AO_DEBUG_REG1) -#define AO_DEBUG_REG2 ((0x00 << 10) | (0x2a << 2)) -#define P_AO_DEBUG_REG2 AOBUS_REG_ADDR(AO_DEBUG_REG2) -#define AO_DEBUG_REG3 ((0x00 << 10) | (0x2b << 2)) -#define P_AO_DEBUG_REG3 AOBUS_REG_ADDR(AO_DEBUG_REG3) -#define AO_IR_BLASTER_ADDR0 ((0x00 << 10) | (0x30 << 2)) -#define P_AO_IR_BLASTER_ADDR0 AOBUS_REG_ADDR(AO_IR_BLASTER_ADDR0) -#define AO_IR_BLASTER_ADDR1 ((0x00 << 10) | (0x31 << 2)) -#define P_AO_IR_BLASTER_ADDR1 AOBUS_REG_ADDR(AO_IR_BLASTER_ADDR1) -#define AO_IR_BLASTER_ADDR2 ((0x00 << 10) | (0x32 << 2)) -#define P_AO_IR_BLASTER_ADDR2 AOBUS_REG_ADDR(AO_IR_BLASTER_ADDR2) -/*add from M8M2*/ -#define AO_JTAG_TRIGGER_CNTL ((0x00 << 10) | (0x34 << 2)) -#define P_AO_JTAG_TRIGGER_CNTL AOBUS_REG_ADDR(AO_JTAG_TRIGGER_CNTL) -/**/ -#define AO_RTI_PWR_A9_CNTL0 ((0x00 << 10) | (0x38 << 2)) -#define P_AO_RTI_PWR_A9_CNTL0 AOBUS_REG_ADDR(AO_RTI_PWR_A9_CNTL0) -#define AO_RTI_PWR_A9_CNTL1 ((0x00 << 10) | (0x39 << 2)) -#define P_AO_RTI_PWR_A9_CNTL1 AOBUS_REG_ADDR(AO_RTI_PWR_A9_CNTL1) +/*no set*/ #define AO_RTI_GEN_PWR_SLEEP0 ((0x00 << 10) | (0x3a << 2)) #define P_AO_RTI_GEN_PWR_SLEEP0 \ AOBUS_REG_ADDR(AO_RTI_GEN_PWR_SLEEP0) #define AO_RTI_GEN_PWR_ISO0 ((0x00 << 10) | (0x3b << 2)) #define P_AO_RTI_GEN_PWR_ISO0 AOBUS_REG_ADDR(AO_RTI_GEN_PWR_ISO0) -#define AO_CEC_GEN_CNTL ((0x00 << 10) | (0x40 << 2)) -#define P_AO_CEC_GEN_CNTL AOBUS_REG_ADDR(AO_CEC_GEN_CNTL) -#define AO_CEC_RW_REG ((0x00 << 10) | (0x41 << 2)) -#define P_AO_CEC_RW_REG AOBUS_REG_ADDR(AO_CEC_RW_REG) -#define AO_CEC_INTR_MASKN ((0x00 << 10) | (0x42 << 2)) -#define P_AO_CEC_INTR_MASKN AOBUS_REG_ADDR(AO_CEC_INTR_MASKN) -#define AO_CEC_INTR_CLR ((0x00 << 10) | (0x43 << 2)) -#define P_AO_CEC_INTR_CLR AOBUS_REG_ADDR(AO_CEC_INTR_CLR) -#define AO_CEC_INTR_STAT ((0x00 << 10) | (0x44 << 2)) -#define P_AO_CEC_INTR_STAT AOBUS_REG_ADDR(AO_CEC_INTR_STAT) -#define AO_IR_DEC_LDR_ACTIVE ((0x01 << 10) | (0x20 << 2)) -#define P_AO_IR_DEC_LDR_ACTIVE AOBUS_REG_ADDR(AO_IR_DEC_LDR_ACTIVE) -#define AO_IR_DEC_LDR_IDLE ((0x01 << 10) | (0x21 << 2)) -#define P_AO_IR_DEC_LDR_IDLE AOBUS_REG_ADDR(AO_IR_DEC_LDR_IDLE) -#define AO_IR_DEC_LDR_REPEAT ((0x01 << 10) | (0x22 << 2)) -#define P_AO_IR_DEC_LDR_REPEAT AOBUS_REG_ADDR(AO_IR_DEC_LDR_REPEAT) -#define AO_IR_DEC_BIT_0 ((0x01 << 10) | (0x23 << 2)) -#define P_AO_IR_DEC_BIT_0 AOBUS_REG_ADDR(AO_IR_DEC_BIT_0) -#define AO_IR_DEC_REG0 ((0x01 << 10) | (0x24 << 2)) -#define P_AO_IR_DEC_REG0 AOBUS_REG_ADDR(AO_IR_DEC_REG0) -#define AO_IR_DEC_FRAME ((0x01 << 10) | (0x25 << 2)) -#define P_AO_IR_DEC_FRAME AOBUS_REG_ADDR(AO_IR_DEC_FRAME) -#define AO_IR_DEC_STATUS ((0x01 << 10) | (0x26 << 2)) -#define P_AO_IR_DEC_STATUS AOBUS_REG_ADDR(AO_IR_DEC_STATUS) -#define AO_IR_DEC_REG1 ((0x01 << 10) | (0x27 << 2)) -#define P_AO_IR_DEC_REG1 AOBUS_REG_ADDR(AO_IR_DEC_REG1) -#define AO_UART_WFIFO ((0x01 << 10) | (0x30 << 2)) -#define P_AO_UART_WFIFO AOBUS_REG_ADDR(AO_UART_WFIFO) -#define AO_UART_RFIFO ((0x01 << 10) | (0x31 << 2)) -#define P_AO_UART_RFIFO AOBUS_REG_ADDR(AO_UART_RFIFO) -#define AO_UART_CONTROL ((0x01 << 10) | (0x32 << 2)) -#define P_AO_UART_CONTROL AOBUS_REG_ADDR(AO_UART_CONTROL) -#define AO_UART_STATUS ((0x01 << 10) | (0x33 << 2)) -#define P_AO_UART_STATUS AOBUS_REG_ADDR(AO_UART_STATUS) -#define AO_UART_MISC ((0x01 << 10) | (0x34 << 2)) -#define P_AO_UART_MISC AOBUS_REG_ADDR(AO_UART_MISC) -#define AO_UART_REG5 ((0x01 << 10) | (0x35 << 2)) -#define P_AO_UART_REG5 AOBUS_REG_ADDR(AO_UART_REG5) -#define AO_UART2_WFIFO ((0x01 << 10) | (0x38 << 2)) -#define P_AO_UART2_WFIFO AOBUS_REG_ADDR(AO_UART2_WFIFO) -#define AO_UART2_RFIFO ((0x01 << 10) | (0x39 << 2)) -#define P_AO_UART2_RFIFO AOBUS_REG_ADDR(AO_UART2_RFIFO) -#define AO_UART2_CONTROL ((0x01 << 10) | (0x3a << 2)) -#define P_AO_UART2_CONTROL AOBUS_REG_ADDR(AO_UART2_CONTROL) -#define AO_UART2_STATUS ((0x01 << 10) | (0x3b << 2)) -#define P_AO_UART2_STATUS AOBUS_REG_ADDR(AO_UART2_STATUS) -#define AO_UART2_MISC ((0x01 << 10) | (0x3c << 2)) -#define P_AO_UART2_MISC AOBUS_REG_ADDR(AO_UART2_MISC) -#define AO_UART2_REG5 ((0x01 << 10) | (0x3d << 2)) -#define P_AO_UART2_REG5 AOBUS_REG_ADDR(AO_UART2_REG5) -#define AO_I2C_M_0_CONTROL_REG ((0x01 << 10) | (0x40 << 2)) -#define P_AO_I2C_M_0_CONTROL_REG \ - AOBUS_REG_ADDR(AO_I2C_M_0_CONTROL_REG) -#define AO_I2C_M_0_SLAVE_ADDR ((0x01 << 10) | (0x41 << 2)) -#define P_AO_I2C_M_0_SLAVE_ADDR \ - AOBUS_REG_ADDR(AO_I2C_M_0_SLAVE_ADDR) -#define AO_I2C_M_0_TOKEN_LIST0 ((0x01 << 10) | (0x42 << 2)) -#define P_AO_I2C_M_0_TOKEN_LIST0 \ - AOBUS_REG_ADDR(AO_I2C_M_0_TOKEN_LIST0) -#define AO_I2C_M_0_TOKEN_LIST1 ((0x01 << 10) | (0x43 << 2)) -#define P_AO_I2C_M_0_TOKEN_LIST1 \ - AOBUS_REG_ADDR(AO_I2C_M_0_TOKEN_LIST1) -#define AO_I2C_M_0_WDATA_REG0 ((0x01 << 10) | (0x44 << 2)) -#define P_AO_I2C_M_0_WDATA_REG0 \ - AOBUS_REG_ADDR(AO_I2C_M_0_WDATA_REG0) -#define AO_I2C_M_0_WDATA_REG1 ((0x01 << 10) | (0x45 << 2)) -#define P_AO_I2C_M_0_WDATA_REG1 \ - AOBUS_REG_ADDR(AO_I2C_M_0_WDATA_REG1) -#define AO_I2C_M_0_RDATA_REG0 ((0x01 << 10) | (0x46 << 2)) -#define P_AO_I2C_M_0_RDATA_REG0 \ - AOBUS_REG_ADDR(AO_I2C_M_0_RDATA_REG0) -#define AO_I2C_M_0_RDATA_REG1 ((0x01 << 10) | (0x47 << 2)) -#define P_AO_I2C_M_0_RDATA_REG1 \ - AOBUS_REG_ADDR(AO_I2C_M_0_RDATA_REG1) -#define AO_I2C_S_CONTROL_REG ((0x01 << 10) | (0x50 << 2)) -#define P_AO_I2C_S_CONTROL_REG AOBUS_REG_ADDR(AO_I2C_S_CONTROL_REG) -#define AO_I2C_S_SEND_REG ((0x01 << 10) | (0x51 << 2)) -#define P_AO_I2C_S_SEND_REG AOBUS_REG_ADDR(AO_I2C_S_SEND_REG) -#define AO_I2C_S_RECV_REG ((0x01 << 10) | (0x52 << 2)) -#define P_AO_I2C_S_RECV_REG AOBUS_REG_ADDR(AO_I2C_S_RECV_REG) -#define AO_I2C_S_CNTL1_REG ((0x01 << 10) | (0x53 << 2)) -#define P_AO_I2C_S_CNTL1_REG AOBUS_REG_ADDR(AO_I2C_S_CNTL1_REG) -#define AO_RTC_ADDR0 ((0x01 << 10) | (0xd0 << 2)) -#define P_AO_RTC_ADDR0 AOBUS_REG_ADDR(AO_RTC_ADDR0) -#define AO_RTC_ADDR1 ((0x01 << 10) | (0xd1 << 2)) -#define P_AO_RTC_ADDR1 AOBUS_REG_ADDR(AO_RTC_ADDR1) -#define AO_RTC_ADDR2 ((0x01 << 10) | (0xd2 << 2)) -#define P_AO_RTC_ADDR2 AOBUS_REG_ADDR(AO_RTC_ADDR2) -#define AO_RTC_ADDR3 ((0x01 << 10) | (0xd3 << 2)) -#define P_AO_RTC_ADDR3 AOBUS_REG_ADDR(AO_RTC_ADDR3) -#define AO_RTC_ADDR4 ((0x01 << 10) | (0xd4 << 2)) -#define P_AO_RTC_ADDR4 AOBUS_REG_ADDR(AO_RTC_ADDR4) -#define AO_MF_IR_DEC_LDR_ACTIVE ((0x01 << 10) | (0x60 << 2)) -#define P_AO_MF_IR_DEC_LDR_ACTIVE \ - AOBUS_REG_ADDR(AO_MF_IR_DEC_LDR_ACTIVE) -#define AO_MF_IR_DEC_LDR_IDLE ((0x01 << 10) | (0x61 << 2)) -#define P_AO_MF_IR_DEC_LDR_IDLE \ - AOBUS_REG_ADDR(AO_MF_IR_DEC_LDR_IDLE) -#define AO_MF_IR_DEC_LDR_REPEAT ((0x01 << 10) | (0x62 << 2)) -#define P_AO_MF_IR_DEC_LDR_REPEAT \ - AOBUS_REG_ADDR(AO_MF_IR_DEC_LDR_REPEAT) -#define AO_MF_IR_DEC_BIT_0 ((0x01 << 10) | (0x63 << 2)) -#define P_AO_MF_IR_DEC_BIT_0 AOBUS_REG_ADDR(AO_MF_IR_DEC_BIT_0) -#define AO_MF_IR_DEC_REG0 ((0x01 << 10) | (0x64 << 2)) -#define P_AO_MF_IR_DEC_REG0 AOBUS_REG_ADDR(AO_MF_IR_DEC_REG0) -#define AO_MF_IR_DEC_FRAME ((0x01 << 10) | (0x65 << 2)) -#define P_AO_MF_IR_DEC_FRAME AOBUS_REG_ADDR(AO_MF_IR_DEC_FRAME) -#define AO_MF_IR_DEC_STATUS ((0x01 << 10) | (0x66 << 2)) -#define P_AO_MF_IR_DEC_STATUS AOBUS_REG_ADDR(AO_MF_IR_DEC_STATUS) -#define AO_MF_IR_DEC_REG1 ((0x01 << 10) | (0x67 << 2)) -#define P_AO_MF_IR_DEC_REG1 AOBUS_REG_ADDR(AO_MF_IR_DEC_REG1) -#define AO_MF_IR_DEC_REG2 ((0x01 << 10) | (0x68 << 2)) -#define P_AO_MF_IR_DEC_REG2 AOBUS_REG_ADDR(AO_MF_IR_DEC_REG2) -#define AO_MF_IR_DEC_DURATN2 ((0x01 << 10) | (0x69 << 2)) -#define P_AO_MF_IR_DEC_DURATN2 AOBUS_REG_ADDR(AO_MF_IR_DEC_DURATN2) -#define AO_MF_IR_DEC_DURATN3 ((0x01 << 10) | (0x6a << 2)) -#define P_AO_MF_IR_DEC_DURATN3 AOBUS_REG_ADDR(AO_MF_IR_DEC_DURATN3) -#define AO_MF_IR_DEC_FRAME1 ((0x01 << 10) | (0x6b << 2)) -#define P_AO_MF_IR_DEC_FRAME1 AOBUS_REG_ADDR(AO_MF_IR_DEC_FRAME1) -#define AM_DDR_PLL_CNTL 0x0400 -#define P_AM_DDR_PLL_CNTL MMC_REG_ADDR(AM_DDR_PLL_CNTL) -#define AM_DDR_PLL_CNTL1 0x0404 -#define P_AM_DDR_PLL_CNTL1 MMC_REG_ADDR(AM_DDR_PLL_CNTL1) -#define AM_DDR_PLL_CNTL2 0x0408 -#define P_AM_DDR_PLL_CNTL2 MMC_REG_ADDR(AM_DDR_PLL_CNTL2) -#define AM_DDR_PLL_CNTL3 0x040c -#define P_AM_DDR_PLL_CNTL3 MMC_REG_ADDR(AM_DDR_PLL_CNTL3) -#define AM_DDR_PLL_CNTL4 0x0410 -#define P_AM_DDR_PLL_CNTL4 MMC_REG_ADDR(AM_DDR_PLL_CNTL4) -#define AM_DDR_PLL_STS 0x0414 -#define P_AM_DDR_PLL_STS MMC_REG_ADDR(AM_DDR_PLL_STS) -#define AM_DDR_CLK_CNTL 0x0418 -#define P_AM_DDR_CLK_CNTL MMC_REG_ADDR(AM_DDR_CLK_CNTL) -#define DDR0_PCTL_SCFG 0x0000 -#define P_DDR0_PCTL_SCFG MMC_REG_ADDR(DDR0_PCTL_SCFG) -#define DDR0_PCTL_SCTL 0x0004 -#define P_DDR0_PCTL_SCTL MMC_REG_ADDR(DDR0_PCTL_SCTL) -#define DDR0_PCTL_STAT 0x0008 -#define P_DDR0_PCTL_STAT MMC_REG_ADDR(DDR0_PCTL_STAT) -#define DDR0_PCTL_INTRSTAT 0x000c -#define P_DDR0_PCTL_INTRSTAT MMC_REG_ADDR(DDR0_PCTL_INTRSTAT) -#define DDR0_PCTL_POWSTAT 0x0048 -#define P_DDR0_PCTL_POWSTAT MMC_REG_ADDR(DDR0_PCTL_POWSTAT) -#define DDR0_PCTL_MRRSTAT0 0x0064 -#define P_DDR0_PCTL_MRRSTAT0 MMC_REG_ADDR(DDR0_PCTL_MRRSTAT0) -#define DDR0_PCTL_CMDTSTAT 0x004c -#define P_DDR0_PCTL_CMDTSTAT MMC_REG_ADDR(DDR0_PCTL_CMDTSTAT) -#define DDR0_PCTL_MCMD 0x0040 -#define P_DDR0_PCTL_MCMD MMC_REG_ADDR(DDR0_PCTL_MCMD) -#define DDR0_PCTL_MRRSTAT1 0x0068 -#define P_DDR0_PCTL_MRRSTAT1 MMC_REG_ADDR(DDR0_PCTL_MRRSTAT1) -#define DDR0_PCTL_MRRCFG0 0x0060 -#define P_DDR0_PCTL_MRRCFG0 MMC_REG_ADDR(DDR0_PCTL_MRRCFG0) -#define DDR0_PCTL_CMDTSTATEN 0x0050 -#define P_DDR0_PCTL_CMDTSTATEN MMC_REG_ADDR(DDR0_PCTL_CMDTSTATEN) -#define DDR0_PCTL_POWCTL 0x0044 -#define P_DDR0_PCTL_POWCTL MMC_REG_ADDR(DDR0_PCTL_POWCTL) -#define DDR0_PCTL_PPCFG 0x0084 -#define P_DDR0_PCTL_PPCFG MMC_REG_ADDR(DDR0_PCTL_PPCFG) -#define DDR0_PCTL_MCFG1 0x007c -#define P_DDR0_PCTL_MCFG1 MMC_REG_ADDR(DDR0_PCTL_MCFG1) -#define DDR0_PCTL_MSTAT 0x0088 -#define P_DDR0_PCTL_MSTAT MMC_REG_ADDR(DDR0_PCTL_MSTAT) -#define DDR0_PCTL_MCFG 0x0080 -#define P_DDR0_PCTL_MCFG MMC_REG_ADDR(DDR0_PCTL_MCFG) -#define DDR0_PCTL_DTUAWDT 0x00b0 -#define P_DDR0_PCTL_DTUAWDT MMC_REG_ADDR(DDR0_PCTL_DTUAWDT) -#define DDR0_PCTL_DTUPRD2 0x00a8 -#define P_DDR0_PCTL_DTUPRD2 MMC_REG_ADDR(DDR0_PCTL_DTUPRD2) -#define DDR0_PCTL_DTUPRD3 0x00ac -#define P_DDR0_PCTL_DTUPRD3 MMC_REG_ADDR(DDR0_PCTL_DTUPRD3) -#define DDR0_PCTL_DTUNE 0x009c -#define P_DDR0_PCTL_DTUNE MMC_REG_ADDR(DDR0_PCTL_DTUNE) -#define DDR0_PCTL_DTUPDES 0x0094 -#define P_DDR0_PCTL_DTUPDES MMC_REG_ADDR(DDR0_PCTL_DTUPDES) -#define DDR0_PCTL_DTUNA 0x0098 -#define P_DDR0_PCTL_DTUNA MMC_REG_ADDR(DDR0_PCTL_DTUNA) -#define DDR0_PCTL_DTUPRD0 0x00a0 -#define P_DDR0_PCTL_DTUPRD0 MMC_REG_ADDR(DDR0_PCTL_DTUPRD0) -#define DDR0_PCTL_DTUPRD1 0x00a4 -#define P_DDR0_PCTL_DTUPRD1 MMC_REG_ADDR(DDR0_PCTL_DTUPRD1) -#define DDR0_PCTL_TCKSRE 0x0124 -#define P_DDR0_PCTL_TCKSRE MMC_REG_ADDR(DDR0_PCTL_TCKSRE) -#define DDR0_PCTL_TZQCSI 0x011c -#define P_DDR0_PCTL_TZQCSI MMC_REG_ADDR(DDR0_PCTL_TZQCSI) -#define DDR0_PCTL_TINIT 0x00c4 -#define P_DDR0_PCTL_TINIT MMC_REG_ADDR(DDR0_PCTL_TINIT) -#define DDR0_PCTL_TDPD 0x0144 -#define P_DDR0_PCTL_TDPD MMC_REG_ADDR(DDR0_PCTL_TDPD) -#define DDR0_PCTL_TOGCNT1U 0x00c0 -#define P_DDR0_PCTL_TOGCNT1U MMC_REG_ADDR(DDR0_PCTL_TOGCNT1U) -#define DDR0_PCTL_TCKE 0x012c -#define P_DDR0_PCTL_TCKE MMC_REG_ADDR(DDR0_PCTL_TCKE) -#define DDR0_PCTL_TMOD 0x0130 -#define P_DDR0_PCTL_TMOD MMC_REG_ADDR(DDR0_PCTL_TMOD) -#define DDR0_PCTL_TEXSR 0x010c -#define P_DDR0_PCTL_TEXSR MMC_REG_ADDR(DDR0_PCTL_TEXSR) -#define DDR0_PCTL_TAL 0x00e4 -#define P_DDR0_PCTL_TAL MMC_REG_ADDR(DDR0_PCTL_TAL) -#define DDR0_PCTL_TRTP 0x0100 -#define P_DDR0_PCTL_TRTP MMC_REG_ADDR(DDR0_PCTL_TRTP) -#define DDR0_PCTL_TCKSRX 0x0128 -#define P_DDR0_PCTL_TCKSRX MMC_REG_ADDR(DDR0_PCTL_TCKSRX) -#define DDR0_PCTL_TRTW 0x00e0 -#define P_DDR0_PCTL_TRTW MMC_REG_ADDR(DDR0_PCTL_TRTW) -#define DDR0_PCTL_TCWL 0x00ec -#define P_DDR0_PCTL_TCWL MMC_REG_ADDR(DDR0_PCTL_TCWL) -#define DDR0_PCTL_TWR 0x0104 -#define P_DDR0_PCTL_TWR MMC_REG_ADDR(DDR0_PCTL_TWR) -#define DDR0_PCTL_TCL 0x00e8 -#define P_DDR0_PCTL_TCL MMC_REG_ADDR(DDR0_PCTL_TCL) -#define DDR0_PCTL_TDQS 0x0120 -#define P_DDR0_PCTL_TDQS MMC_REG_ADDR(DDR0_PCTL_TDQS) -#define DDR0_PCTL_TRSTH 0x00c8 -#define P_DDR0_PCTL_TRSTH MMC_REG_ADDR(DDR0_PCTL_TRSTH) -#define DDR0_PCTL_TRCD 0x00f8 -#define P_DDR0_PCTL_TRCD MMC_REG_ADDR(DDR0_PCTL_TRCD) -#define DDR0_PCTL_TXP 0x0110 -#define P_DDR0_PCTL_TXP MMC_REG_ADDR(DDR0_PCTL_TXP) -#define DDR0_PCTL_TOGCNT100N 0x00cc -#define P_DDR0_PCTL_TOGCNT100N MMC_REG_ADDR(DDR0_PCTL_TOGCNT100N) -#define DDR0_PCTL_TMRD 0x00d4 -#define P_DDR0_PCTL_TMRD MMC_REG_ADDR(DDR0_PCTL_TMRD) -#define DDR0_PCTL_TRSTL 0x0134 -#define P_DDR0_PCTL_TRSTL MMC_REG_ADDR(DDR0_PCTL_TRSTL) -#define DDR0_PCTL_TREFI 0x00d0 -#define P_DDR0_PCTL_TREFI MMC_REG_ADDR(DDR0_PCTL_TREFI) -#define DDR0_PCTL_TRAS 0x00f0 -#define P_DDR0_PCTL_TRAS MMC_REG_ADDR(DDR0_PCTL_TRAS) -#define DDR0_PCTL_TREFI_MEM_DDR3 0x0148 -#define P_DDR0_PCTL_TWTR MMC_REG_ADDR(DDR0_PCTL_TWTR) -#define DDR0_PCTL_TRC 0x00f4 -#define P_DDR0_PCTL_TRC MMC_REG_ADDR(DDR0_PCTL_TRC) -#define DDR0_PCTL_TRFC 0x00d8 -#define P_DDR0_PCTL_TRFC MMC_REG_ADDR(DDR0_PCTL_TRFC) -#define DDR0_PCTL_TMRR 0x013c -#define P_DDR0_PCTL_TMRR MMC_REG_ADDR(DDR0_PCTL_TMRR) -#define DDR0_PCTL_TCKESR 0x0140 -#define P_DDR0_PCTL_TCKESR MMC_REG_ADDR(DDR0_PCTL_TCKESR) -#define DDR0_PCTL_TZQCL 0x0138 -#define P_DDR0_PCTL_TZQCL MMC_REG_ADDR(DDR0_PCTL_TZQCL) -#define DDR0_PCTL_TRRD 0x00fc -#define P_DDR0_PCTL_TRRD MMC_REG_ADDR(DDR0_PCTL_TRRD) -#define DDR0_PCTL_TRP 0x00dc -#define P_DDR0_PCTL_TRP MMC_REG_ADDR(DDR0_PCTL_TRP) -#define DDR0_PCTL_TZQCS 0x0118 -#define P_DDR0_PCTL_TZQCS MMC_REG_ADDR(DDR0_PCTL_TZQCS) -#define DDR0_PCTL_TXPDLL 0x0114 -#define P_DDR0_PCTL_TXPDLL MMC_REG_ADDR(DDR0_PCTL_TXPDLL) -#define DDR0_PCTL_ECCCFG 0x0180 -#define P_DDR0_PCTL_ECCCFG MMC_REG_ADDR(DDR0_PCTL_ECCCFG) -#define DDR0_PCTL_ECCLOG 0x018c -#define P_DDR0_PCTL_ECCLOG MMC_REG_ADDR(DDR0_PCTL_ECCLOG) -#define DDR0_PCTL_ECCCLR 0x0188 -#define P_DDR0_PCTL_ECCCLR MMC_REG_ADDR(DDR0_PCTL_ECCCLR) -#define DDR0_PCTL_ECCTST 0x0184 -#define P_DDR0_PCTL_ECCTST MMC_REG_ADDR(DDR0_PCTL_ECCTST) -#define DDR0_PCTL_DTUWD0 0x0210 -#define P_DDR0_PCTL_DTUWD0 MMC_REG_ADDR(DDR0_PCTL_DTUWD0) -#define DDR0_PCTL_DTUWD1 0x0214 -#define P_DDR0_PCTL_DTUWD1 MMC_REG_ADDR(DDR0_PCTL_DTUWD1) -#define DDR0_PCTL_DTUWACTL 0x0200 -#define P_DDR0_PCTL_DTUWACTL MMC_REG_ADDR(DDR0_PCTL_DTUWACTL) -#define DDR0_PCTL_DTULFSRRD 0x0238 -#define P_DDR0_PCTL_DTULFSRRD MMC_REG_ADDR(DDR0_PCTL_DTULFSRRD) -#define DDR0_PCTL_DTUWD2 0x0218 -#define P_DDR0_PCTL_DTUWD2 MMC_REG_ADDR(DDR0_PCTL_DTUWD2) -#define DDR0_PCTL_DTUWD3 0x021c -#define P_DDR0_PCTL_DTUWD3 MMC_REG_ADDR(DDR0_PCTL_DTUWD3) -#define DDR0_PCTL_DTULFSRWD 0x0234 -#define P_DDR0_PCTL_DTULFSRWD MMC_REG_ADDR(DDR0_PCTL_DTULFSRWD) -#define DDR0_PCTL_DTURACTL 0x0204 -#define P_DDR0_PCTL_DTURACTL MMC_REG_ADDR(DDR0_PCTL_DTURACTL) -#define DDR0_PCTL_DTUWDM 0x0220 -#define P_DDR0_PCTL_DTUWDM MMC_REG_ADDR(DDR0_PCTL_DTUWDM) -#define DDR0_PCTL_DTURD0 0x0224 -#define P_DDR0_PCTL_DTURD0 MMC_REG_ADDR(DDR0_PCTL_DTURD0) -#define DDR0_PCTL_DTURD1 0x0228 -#define P_DDR0_PCTL_DTURD1 MMC_REG_ADDR(DDR0_PCTL_DTURD1) -#define DDR0_PCTL_DTURD2 0x022c -#define P_DDR0_PCTL_DTURD2 MMC_REG_ADDR(DDR0_PCTL_DTURD2) -#define DDR0_PCTL_DTURD3 0x0230 -#define P_DDR0_PCTL_DTURD3 MMC_REG_ADDR(DDR0_PCTL_DTURD3) -#define DDR0_PCTL_DTUCFG 0x0208 -#define P_DDR0_PCTL_DTUCFG MMC_REG_ADDR(DDR0_PCTL_DTUCFG) -#define DDR0_PCTL_DTUEAF 0x023c -#define P_DDR0_PCTL_DTUEAF MMC_REG_ADDR(DDR0_PCTL_DTUEAF) -#define DDR0_PCTL_DTUECTL 0x020c -#define P_DDR0_PCTL_DTUECTL MMC_REG_ADDR(DDR0_PCTL_DTUECTL) -#define DDR0_PCTL_DFIODTCFG1 0x0248 -#define DDR0_PCTL_DFITDRAMCLKDIS 0x02d4 -#define P_DDR0_PCTL_DFITDRAMCLKDIS \ - MMC_REG_ADDR(DDR0_PCTL_DFITDRAMCLKDIS) -#define DDR0_PCTL_DFILPCFG0 0x02f0 -#define P_DDR0_PCTL_DFILPCFG0 \ - MMC_REG_ADDR(DDR0_PCTL_DFILPCFG0) -#define DDR0_PCTL_DFITRWRLVLDELAY0 0x0318 -#define P_DDR0_PCTL_DFITRWRLVLDELAY0 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLDELAY0) -#define DDR0_PCTL_DFITRWRLVLDELAY1 0x031c -#define P_DDR0_PCTL_DFITRWRLVLDELAY1 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLDELAY1) -#define DDR0_PCTL_DFITRWRLVLDELAY2 0x0320 -#define P_DDR0_PCTL_DFITRWRLVLDELAY2 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLDELAY2) -#define DDR0_PCTL_DFITRRDLVLRESP0 0x030c -#define P_DDR0_PCTL_DFITRRDLVLRESP0 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLRESP0) -#define DDR0_PCTL_DFITRRDLVLRESP1 0x0310 -#define P_DDR0_PCTL_DFITRRDLVLRESP1 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLRESP1) -#define DDR0_PCTL_DFITRRDLVLRESP2 0x0314 -#define P_DDR0_PCTL_DFITRRDLVLRESP2 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLRESP2) -#define DDR0_PCTL_DFITRWRLVLRESP0 0x0300 -#define P_DDR0_PCTL_DFITRWRLVLRESP0 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLRESP0) -#define DDR0_PCTL_DFITRRDLVLDELAY0 0x0324 -#define P_DDR0_PCTL_DFITRRDLVLDELAY0 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLDELAY0) -#define DDR0_PCTL_DFITRRDLVLDELAY1 0x0328 -#define P_DDR0_PCTL_DFITRRDLVLDELAY1 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLDELAY1) -#define DDR0_PCTL_DFITRWRLVLRESP1 0x0304 -#define P_DDR0_PCTL_DFITRWRLVLRESP1 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLRESP1) -#define DDR0_PCTL_DFITRRDLVLDELAY2 0x032c -#define P_DDR0_PCTL_DFITRRDLVLDELAY2 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLDELAY2) -#define DDR0_PCTL_DFITRWRLVLRESP2 0x0308 -#define P_DDR0_PCTL_DFITRWRLVLRESP2 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLRESP2) -#define DDR0_PCTL_DFITRRDLVLGATEDELAY0 0x0330 -#define P_DDR0_PCTL_DFITRRDLVLGATEDELAY0 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLGATEDELAY0) -#define DDR0_PCTL_DFITRCMD 0x033c -#define P_DDR0_PCTL_DFITRCMD MMC_REG_ADDR(DDR0_PCTL_DFITRCMD) -#define DDR0_PCTL_DFITRRDLVLGATEDELAY1 0x0334 -#define P_DDR0_PCTL_DFITRRDLVLGATEDELAY1 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLGATEDELAY1) -#define DDR0_PCTL_DFITRRDLVLGATEDELAY2 0x0338 -#define P_DDR0_PCTL_DFITRRDLVLGATEDELAY2 \ - MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLGATEDELAY2) -#define DDR0_PCTL_IPTR 0x03fc -#define P_DDR0_PCTL_IPTR MMC_REG_ADDR(DDR0_PCTL_IPTR) -#define DDR0_PCTL_IPVR 0x03f8 -#define P_DDR0_PCTL_IPVR MMC_REG_ADDR(DDR0_PCTL_IPVR) -#define DDR0_PUB_RIDR (0x1000 + (0x00 << 2)) -#define P_DDR0_PUB_RIDR MMC_REG_ADDR(DDR0_PUB_RIDR) -#define DDR0_PUB_PIR (0x1000 + (0x01 << 2)) -#define P_DDR0_PUB_PIR MMC_REG_ADDR(DDR0_PUB_PIR) -#define DDR0_PUB_PGCR0 (0x1000 + (0x02 << 2)) -#define P_DDR0_PUB_PGCR0 MMC_REG_ADDR(DDR0_PUB_PGCR0) -#define DDR0_PUB_PGCR1 (0x1000 + (0x03 << 2)) -#define P_DDR0_PUB_PGCR1 MMC_REG_ADDR(DDR0_PUB_PGCR1) -#define DDR0_PUB_PGCR2 (0x1000 + (0x04 << 2)) -#define P_DDR0_PUB_PGCR2 MMC_REG_ADDR(DDR0_PUB_PGCR2) -#define DDR0_PUB_PGCR3 (0x1000 + (0x05 << 2)) -#define P_DDR0_PUB_PGCR3 MMC_REG_ADDR(DDR0_PUB_PGCR3) -#define DDR0_PUB_PGSR0 (0x1000 + (0x06 << 2)) -#define P_DDR0_PUB_PGSR0 MMC_REG_ADDR(DDR0_PUB_PGSR0) -#define DDR0_PUB_PGSR1 (0x1000 + (0x07 << 2)) -#define P_DDR0_PUB_PGSR1 MMC_REG_ADDR(DDR0_PUB_PGSR1) -#define DDR0_PUB_PLLCR (0x1000 + (0x08 << 2)) -#define P_DDR0_PUB_PLLCR MMC_REG_ADDR(DDR0_PUB_PLLCR) -#define DDR0_PUB_PTR0 (0x1000 + (0x09 << 2)) -#define P_DDR0_PUB_PTR0 MMC_REG_ADDR(DDR0_PUB_PTR0) -#define DDR0_PUB_PTR1 (0x1000 + (0x0A << 2)) -#define P_DDR0_PUB_PTR1 MMC_REG_ADDR(DDR0_PUB_PTR1) -#define DDR0_PUB_PTR2 (0x1000 + (0x0B << 2)) -#define P_DDR0_PUB_PTR2 MMC_REG_ADDR(DDR0_PUB_PTR2) -#define DDR0_PUB_PTR3 (0x1000 + (0x0C << 2)) -#define P_DDR0_PUB_PTR3 MMC_REG_ADDR(DDR0_PUB_PTR3) -#define DDR0_PUB_PTR4 (0x1000 + (0x0D << 2)) -#define P_DDR0_PUB_PTR4 MMC_REG_ADDR(DDR0_PUB_PTR4) -#define DDR0_PUB_ACMDLR (0x1000 + (0x0E << 2)) -#define P_DDR0_PUB_ACMDLR MMC_REG_ADDR(DDR0_PUB_ACMDLR) -#define DDR0_PUB_ACLCDLR (0x1000 + (0x0F << 2)) -#define P_DDR0_PUB_ACLCDLR MMC_REG_ADDR(DDR0_PUB_ACLCDLR) -#define DDR0_PUB_ACBDLR0 (0x1000 + (0x10 << 2)) -#define P_DDR0_PUB_ACBDLR0 MMC_REG_ADDR(DDR0_PUB_ACBDLR0) -#define DDR0_PUB_ACBDLR1 (0x1000 + (0x11 << 2)) -#define P_DDR0_PUB_ACBDLR1 MMC_REG_ADDR(DDR0_PUB_ACBDLR1) -#define DDR0_PUB_ACBDLR2 (0x1000 + (0x12 << 2)) -#define P_DDR0_PUB_ACBDLR2 MMC_REG_ADDR(DDR0_PUB_ACBDLR2) -#define DDR0_PUB_ACBDLR3 (0x1000 + (0x13 << 2)) -#define P_DDR0_PUB_ACBDLR3 MMC_REG_ADDR(DDR0_PUB_ACBDLR3) -#define DDR0_PUB_ACBDLR4 (0x1000 + (0x14 << 2)) -#define P_DDR0_PUB_ACBDLR4 MMC_REG_ADDR(DDR0_PUB_ACBDLR4) -#define DDR0_PUB_ACBDLR5 (0x1000 + (0x15 << 2)) -#define P_DDR0_PUB_ACBDLR5 MMC_REG_ADDR(DDR0_PUB_ACBDLR5) -#define DDR0_PUB_ACBDLR6 (0x1000 + (0x16 << 2)) -#define P_DDR0_PUB_ACBDLR6 MMC_REG_ADDR(DDR0_PUB_ACBDLR6) -#define DDR0_PUB_ACBDLR7 (0x1000 + (0x17 << 2)) -#define P_DDR0_PUB_ACBDLR7 MMC_REG_ADDR(DDR0_PUB_ACBDLR7) -#define DDR0_PUB_ACBDLR8 (0x1000 + (0x18 << 2)) -#define P_DDR0_PUB_ACBDLR8 MMC_REG_ADDR(DDR0_PUB_ACBDLR8) -#define DDR0_PUB_ACBDLR9 (0x1000 + (0x19 << 2)) -#define P_DDR0_PUB_ACBDLR9 MMC_REG_ADDR(DDR0_PUB_ACBDLR9) -#define DDR0_PUB_ACIOCR0 (0x1000 + (0x1A << 2)) -#define P_DDR0_PUB_ACIOCR0 MMC_REG_ADDR(DDR0_PUB_ACIOCR0) -#define DDR0_PUB_ACIOCR1 (0x1000 + (0x1B << 2)) -#define P_DDR0_PUB_ACIOCR1 MMC_REG_ADDR(DDR0_PUB_ACIOCR1) -#define DDR0_PUB_ACIOCR2 (0x1000 + (0x1C << 2)) -#define P_DDR0_PUB_ACIOCR2 MMC_REG_ADDR(DDR0_PUB_ACIOCR2) -#define DDR0_PUB_ACIOCR3 (0x1000 + (0x1D << 2)) -#define P_DDR0_PUB_ACIOCR3 MMC_REG_ADDR(DDR0_PUB_ACIOCR3) -#define DDR0_PUB_ACIOCR4 (0x1000 + (0x1E << 2)) -#define P_DDR0_PUB_ACIOCR4 MMC_REG_ADDR(DDR0_PUB_ACIOCR4) -#define DDR0_PUB_ACIOCR5 (0x1000 + (0x1F << 2)) -#define P_DDR0_PUB_ACIOCR5 MMC_REG_ADDR(DDR0_PUB_ACIOCR5) -#define DDR0_PUB_DXCCR (0x1000 + (0x20 << 2)) -#define P_DDR0_PUB_DXCCR MMC_REG_ADDR(DDR0_PUB_DXCCR) -#define DDR0_PUB_DSGCR (0x1000 + (0x21 << 2)) -#define P_DDR0_PUB_DSGCR MMC_REG_ADDR(DDR0_PUB_DSGCR) -#define DDR0_PUB_DCR (0x1000 + (0x22 << 2)) -#define P_DDR0_PUB_DCR MMC_REG_ADDR(DDR0_PUB_DCR) -#define DDR0_PUB_DTPR0 (0x1000 + (0x23 << 2)) -#define P_DDR0_PUB_DTPR0 MMC_REG_ADDR(DDR0_PUB_DTPR0) -#define DDR0_PUB_DTPR1 (0x1000 + (0x24 << 2)) -#define P_DDR0_PUB_DTPR1 MMC_REG_ADDR(DDR0_PUB_DTPR1) -#define DDR0_PUB_DTPR2 (0x1000 + (0x25 << 2)) -#define P_DDR0_PUB_DTPR2 MMC_REG_ADDR(DDR0_PUB_DTPR2) -#define DDR0_PUB_DTPR3 (0x1000 + (0x26 << 2)) -#define P_DDR0_PUB_DTPR3 MMC_REG_ADDR(DDR0_PUB_DTPR3) -#define DDR0_PUB_MR0 (0x1000 + (0x27 << 2)) -#define P_DDR0_PUB_MR0 MMC_REG_ADDR(DDR0_PUB_MR0) -#define DDR0_PUB_MR1 (0x1000 + (0x28 << 2)) -#define P_DDR0_PUB_MR1 MMC_REG_ADDR(DDR0_PUB_MR1) -#define DDR0_PUB_MR2 (0x1000 + (0x29 << 2)) -#define P_DDR0_PUB_MR2 MMC_REG_ADDR(DDR0_PUB_MR2) -#define DDR0_PUB_MR3 (0x1000 + (0x2A << 2)) -#define P_DDR0_PUB_MR3 MMC_REG_ADDR(DDR0_PUB_MR3) -#define DDR0_PUB_ODTCR (0x1000 + (0x2B << 2)) -#define P_DDR0_PUB_ODTCR MMC_REG_ADDR(DDR0_PUB_ODTCR) -#define DDR0_PUB_DTCR (0x1000 + (0x2C << 2)) -#define P_DDR0_PUB_DTCR MMC_REG_ADDR(DDR0_PUB_DTCR) -#define DDR0_PUB_DTAR0 (0x1000 + (0x2D << 2)) -#define P_DDR0_PUB_DTAR0 MMC_REG_ADDR(DDR0_PUB_DTAR0) -#define DDR0_PUB_DTAR1 (0x1000 + (0x2E << 2)) -#define P_DDR0_PUB_DTAR1 MMC_REG_ADDR(DDR0_PUB_DTAR1) -#define DDR0_PUB_DTAR2 (0x1000 + (0x2F << 2)) -#define P_DDR0_PUB_DTAR2 MMC_REG_ADDR(DDR0_PUB_DTAR2) -#define DDR0_PUB_DTAR3 (0x1000 + (0x30 << 2)) -#define P_DDR0_PUB_DTAR3 MMC_REG_ADDR(DDR0_PUB_DTAR3) -#define DDR0_PUB_DTDR0 (0x1000 + (0x31 << 2)) -#define P_DDR0_PUB_DTDR0 MMC_REG_ADDR(DDR0_PUB_DTDR0) -#define DDR0_PUB_DTDR1 (0x1000 + (0x32 << 2)) -#define P_DDR0_PUB_DTDR1 MMC_REG_ADDR(DDR0_PUB_DTDR1) -#define DDR0_PUB_DTEDR0 (0x1000 + (0x33 << 2)) -#define P_DDR0_PUB_DTEDR0 MMC_REG_ADDR(DDR0_PUB_DTEDR0) -#define DDR0_PUB_DTEDR1 (0x1000 + (0x34 << 2)) -#define P_DDR0_PUB_DTEDR1 MMC_REG_ADDR(DDR0_PUB_DTEDR1) -#define DDR0_PUB_RDIMMGCR0 (0x1000 + (0x35 << 2)) -#define P_DDR0_PUB_RDIMMGCR0 MMC_REG_ADDR(DDR0_PUB_RDIMMGCR0) -#define DDR0_PUB_RDIMMGCR1 (0x1000 + (0x36 << 2)) -#define P_DDR0_PUB_RDIMMGCR1 MMC_REG_ADDR(DDR0_PUB_RDIMMGCR1) -#define DDR0_PUB_RDIMMCR0 (0x1000 + (0x37 << 2)) -#define P_DDR0_PUB_RDIMMCR0 MMC_REG_ADDR(DDR0_PUB_RDIMMCR0) -#define DDR0_PUB_RDIMMCR1 (0x1000 + (0x38 << 2)) -#define P_DDR0_PUB_RDIMMCR1 MMC_REG_ADDR(DDR0_PUB_RDIMMCR1) -#define DDR0_PUB_GPR0 (0x1000 + (0x39 << 2)) -#define P_DDR0_PUB_GPR0 MMC_REG_ADDR(DDR0_PUB_GPR0) -#define DDR0_PUB_GPR1 (0x1000 + (0x3A << 2)) -#define P_DDR0_PUB_GPR1 MMC_REG_ADDR(DDR0_PUB_GPR1) -#define DDR0_PUB_CATR0 (0x1000 + (0x3B << 2)) -#define P_DDR0_PUB_CATR0 MMC_REG_ADDR(DDR0_PUB_CATR0) -#define DDR0_PUB_CATR1 (0x1000 + (0x3C << 2)) -#define P_DDR0_PUB_CATR1 MMC_REG_ADDR(DDR0_PUB_CATR1) -#define DDR0_PUB_DCUAR (0x1000 + (0x60 << 2)) -#define P_DDR0_PUB_DCUAR MMC_REG_ADDR(DDR0_PUB_DCUAR) -#define DDR0_PUB_DCUDR (0x1000 + (0x61 << 2)) -#define P_DDR0_PUB_DCUDR MMC_REG_ADDR(DDR0_PUB_DCUDR) -#define DDR0_PUB_DCURR (0x1000 + (0x62 << 2)) -#define P_DDR0_PUB_DCURR MMC_REG_ADDR(DDR0_PUB_DCURR) -#define DDR0_PUB_DCULR (0x1000 + (0x63 << 2)) -#define P_DDR0_PUB_DCULR MMC_REG_ADDR(DDR0_PUB_DCULR) -#define DDR0_PUB_DCUGCR (0x1000 + (0x64 << 2)) -#define P_DDR0_PUB_DCUGCR MMC_REG_ADDR(DDR0_PUB_DCUGCR) -#define DDR0_PUB_DCUTPR (0x1000 + (0x65 << 2)) -#define P_DDR0_PUB_DCUTPR MMC_REG_ADDR(DDR0_PUB_DCUTPR) -#define DDR0_PUB_DCUSR0 (0x1000 + (0x66 << 2)) -#define P_DDR0_PUB_DCUSR0 MMC_REG_ADDR(DDR0_PUB_DCUSR0) -#define DDR0_PUB_DCUSR1 (0x1000 + (0x67 << 2)) -#define P_DDR0_PUB_DCUSR1 MMC_REG_ADDR(DDR0_PUB_DCUSR1) -#define DDR0_PUB_BISTRR (0x1000 + (0x70 << 2)) -#define P_DDR0_PUB_BISTRR MMC_REG_ADDR(DDR0_PUB_BISTRR) -#define DDR0_PUB_BISTWCR (0x1000 + (0x71 << 2)) -#define P_DDR0_PUB_BISTWCR MMC_REG_ADDR(DDR0_PUB_BISTWCR) -#define DDR0_PUB_BISTMSKR0 (0x1000 + (0x72 << 2)) -#define P_DDR0_PUB_BISTMSKR0 MMC_REG_ADDR(DDR0_PUB_BISTMSKR0) -#define DDR0_PUB_BISTMSKR1 (0x1000 + (0x73 << 2)) -#define P_DDR0_PUB_BISTMSKR1 MMC_REG_ADDR(DDR0_PUB_BISTMSKR1) -#define DDR0_PUB_BISTMSKR2 (0x1000 + (0x74 << 2)) -#define P_DDR0_PUB_BISTMSKR2 MMC_REG_ADDR(DDR0_PUB_BISTMSKR2) -#define DDR0_PUB_BISTLSR (0x1000 + (0x75 << 2)) -#define P_DDR0_PUB_BISTLSR MMC_REG_ADDR(DDR0_PUB_BISTLSR) -#define DDR0_PUB_BISTAR0 (0x1000 + (0x76 << 2)) -#define P_DDR0_PUB_BISTAR0 MMC_REG_ADDR(DDR0_PUB_BISTAR0) -#define DDR0_PUB_BISTAR1 (0x1000 + (0x77 << 2)) -#define P_DDR0_PUB_BISTAR1 MMC_REG_ADDR(DDR0_PUB_BISTAR1) -#define DDR0_PUB_BISTAR2 (0x1000 + (0x78 << 2)) -#define P_DDR0_PUB_BISTAR2 MMC_REG_ADDR(DDR0_PUB_BISTAR2) -#define DDR0_PUB_BISTUDPR (0x1000 + (0x79 << 2)) -#define P_DDR0_PUB_BISTUDPR MMC_REG_ADDR(DDR0_PUB_BISTUDPR) -#define DDR0_PUB_BISTGSR (0x1000 + (0x7A << 2)) -#define P_DDR0_PUB_BISTGSR MMC_REG_ADDR(DDR0_PUB_BISTGSR) -#define DDR0_PUB_BISTWER (0x1000 + (0x7B << 2)) -#define P_DDR0_PUB_BISTWER MMC_REG_ADDR(DDR0_PUB_BISTWER) -#define DDR0_PUB_BISTBER0 (0x1000 + (0x7C << 2)) -#define P_DDR0_PUB_BISTBER0 MMC_REG_ADDR(DDR0_PUB_BISTBER0) -#define DDR0_PUB_BISTBER1 (0x1000 + (0x7D << 2)) -#define P_DDR0_PUB_BISTBER1 MMC_REG_ADDR(DDR0_PUB_BISTBER1) -#define DDR0_PUB_BISTBER2 (0x1000 + (0x7E << 2)) -#define P_DDR0_PUB_BISTBER2 MMC_REG_ADDR(DDR0_PUB_BISTBER2) -#define DDR0_PUB_BISTBER3 (0x1000 + (0x7F << 2)) -#define P_DDR0_PUB_BISTBER3 MMC_REG_ADDR(DDR0_PUB_BISTBER3) -#define DDR0_PUB_BISTWCSR (0x1000 + (0x80 << 2)) -#define P_DDR0_PUB_BISTWCSR MMC_REG_ADDR(DDR0_PUB_BISTWCSR) -#define DDR0_PUB_BISTFWR0 (0x1000 + (0x81 << 2)) -#define P_DDR0_PUB_BISTFWR0 MMC_REG_ADDR(DDR0_PUB_BISTFWR0) -#define DDR0_PUB_BISTFWR1 (0x1000 + (0x82 << 2)) -#define P_DDR0_PUB_BISTFWR1 MMC_REG_ADDR(DDR0_PUB_BISTFWR1) -#define DDR0_PUB_BISTFWR2 (0x1000 + (0x83 << 2)) -#define P_DDR0_PUB_BISTFWR2 MMC_REG_ADDR(DDR0_PUB_BISTFWR2) -#define DDR0_PUB_IOVCR0 (0x1000 + (0x8E << 2)) -#define P_DDR0_PUB_IOVCR0 MMC_REG_ADDR(DDR0_PUB_IOVCR0) -#define DDR0_PUB_IOVCR1 (0x1000 + (0x8F << 2)) -#define P_DDR0_PUB_IOVCR1 MMC_REG_ADDR(DDR0_PUB_IOVCR1) -#define DDR0_PUB_ZQCR (0x1000 + (0x90 << 2)) -#define P_DDR0_PUB_ZQCR MMC_REG_ADDR(DDR0_PUB_ZQCR) -#define DDR0_PUB_ZQ0PR (0x1000 + (0x91 << 2)) -#define P_DDR0_PUB_ZQ0PR MMC_REG_ADDR(DDR0_PUB_ZQ0PR) -#define DDR0_PUB_ZQ0DR (0x1000 + (0x92 << 2)) -#define P_DDR0_PUB_ZQ0DR MMC_REG_ADDR(DDR0_PUB_ZQ0DR) -#define DDR0_PUB_ZQ0SR (0x1000 + (0x93 << 2)) -#define P_DDR0_PUB_ZQ0SR MMC_REG_ADDR(DDR0_PUB_ZQ0SR) -#define DDR0_PUB_ZQ1PR (0x1000 + (0x95 << 2)) -#define P_DDR0_PUB_ZQ1PR MMC_REG_ADDR(DDR0_PUB_ZQ1PR) -#define DDR0_PUB_ZQ1DR (0x1000 + (0x96 << 2)) -#define P_DDR0_PUB_ZQ1DR MMC_REG_ADDR(DDR0_PUB_ZQ1DR) -#define DDR0_PUB_ZQ1SR (0x1000 + (0x97 << 2)) -#define P_DDR0_PUB_ZQ1SR MMC_REG_ADDR(DDR0_PUB_ZQ1SR) -#define DDR0_PUB_ZQ2PR (0x1000 + (0x99 << 2)) -#define P_DDR0_PUB_ZQ2PR MMC_REG_ADDR(DDR0_PUB_ZQ2PR) -#define DDR0_PUB_ZQ2DR (0x1000 + (0x9A << 2)) -#define P_DDR0_PUB_ZQ2DR MMC_REG_ADDR(DDR0_PUB_ZQ2DR) -#define DDR0_PUB_ZQ2SR (0x1000 + (0x9B << 2)) -#define P_DDR0_PUB_ZQ2SR MMC_REG_ADDR(DDR0_PUB_ZQ2SR) -#define DDR0_PUB_ZQ3PR (0x1000 + (0x9D << 2)) -#define P_DDR0_PUB_ZQ3PR MMC_REG_ADDR(DDR0_PUB_ZQ3PR) -#define DDR0_PUB_ZQ3DR (0x1000 + (0x9E << 2)) -#define P_DDR0_PUB_ZQ3DR MMC_REG_ADDR(DDR0_PUB_ZQ3DR) -#define DDR0_PUB_ZQ3SR (0x1000 + (0x9F << 2)) -#define P_DDR0_PUB_ZQ3SR MMC_REG_ADDR(DDR0_PUB_ZQ3SR) -#define DDR0_PUB_DX0GCR0 (0x1000 + (0xA0 << 2)) -#define P_DDR0_PUB_DX0GCR0 MMC_REG_ADDR(DDR0_PUB_DX0GCR0) -#define DDR0_PUB_DX0GCR1 (0x1000 + (0xA1 << 2)) -#define P_DDR0_PUB_DX0GCR1 MMC_REG_ADDR(DDR0_PUB_DX0GCR1) -#define DDR0_PUB_DX0GCR2 (0x1000 + (0xA2 << 2)) -#define P_DDR0_PUB_DX0GCR2 MMC_REG_ADDR(DDR0_PUB_DX0GCR2) -#define DDR0_PUB_DX0GCR3 (0x1000 + (0xA3 << 2)) -#define P_DDR0_PUB_DX0GCR3 MMC_REG_ADDR(DDR0_PUB_DX0GCR3) -#define DDR0_PUB_DX0GSR0 (0x1000 + (0xA4 << 2)) -#define P_DDR0_PUB_DX0GSR0 MMC_REG_ADDR(DDR0_PUB_DX0GSR0) -#define DDR0_PUB_DX0GSR1 (0x1000 + (0xA5 << 2)) -#define P_DDR0_PUB_DX0GSR1 MMC_REG_ADDR(DDR0_PUB_DX0GSR1) -#define DDR0_PUB_DX0GSR2 (0x1000 + (0xA6 << 2)) -#define P_DDR0_PUB_DX0GSR2 MMC_REG_ADDR(DDR0_PUB_DX0GSR2) -#define DDR0_PUB_DX0BDLR0 (0x1000 + (0xA7 << 2)) -#define P_DDR0_PUB_DX0BDLR0 MMC_REG_ADDR(DDR0_PUB_DX0BDLR0) -#define DDR0_PUB_DX0BDLR1 (0x1000 + (0xA8 << 2)) -#define P_DDR0_PUB_DX0BDLR1 MMC_REG_ADDR(DDR0_PUB_DX0BDLR1) -#define DDR0_PUB_DX0BDLR2 (0x1000 + (0xA9 << 2)) -#define P_DDR0_PUB_DX0BDLR2 MMC_REG_ADDR(DDR0_PUB_DX0BDLR2) -#define DDR0_PUB_DX0BDLR3 (0x1000 + (0xAA << 2)) -#define P_DDR0_PUB_DX0BDLR3 MMC_REG_ADDR(DDR0_PUB_DX0BDLR3) -#define DDR0_PUB_DX0BDLR4 (0x1000 + (0xAB << 2)) -#define P_DDR0_PUB_DX0BDLR4 MMC_REG_ADDR(DDR0_PUB_DX0BDLR4) -#define DDR0_PUB_DX0BDLR5 (0x1000 + (0xAC << 2)) -#define P_DDR0_PUB_DX0BDLR5 MMC_REG_ADDR(DDR0_PUB_DX0BDLR5) -#define DDR0_PUB_DX0BDLR6 (0x1000 + (0xAD << 2)) -#define P_DDR0_PUB_DX0BDLR6 MMC_REG_ADDR(DDR0_PUB_DX0BDLR6) -#define DDR0_PUB_DX0LCDLR0 (0x1000 + (0xAE << 2)) -#define P_DDR0_PUB_DX0LCDLR0 MMC_REG_ADDR(DDR0_PUB_DX0LCDLR0) -#define DDR0_PUB_DX0LCDLR1 (0x1000 + (0xAF << 2)) -#define P_DDR0_PUB_DX0LCDLR1 MMC_REG_ADDR(DDR0_PUB_DX0LCDLR1) -#define DDR0_PUB_DX0LCDLR2 (0x1000 + (0xB0 << 2)) -#define P_DDR0_PUB_DX0LCDLR2 MMC_REG_ADDR(DDR0_PUB_DX0LCDLR2) -#define DDR0_PUB_DX0MDLR (0x1000 + (0xB1 << 2)) -#define P_DDR0_PUB_DX0MDLR MMC_REG_ADDR(DDR0_PUB_DX0MDLR) -#define DDR0_PUB_DX0GTR (0x1000 + (0xB2 << 2)) -#define P_DDR0_PUB_DX0GTR MMC_REG_ADDR(DDR0_PUB_DX0GTR) -#define DDR0_PUB_DX1GCR0 (0x1000 + (0xC0 << 2)) -#define P_DDR0_PUB_DX1GCR0 MMC_REG_ADDR(DDR0_PUB_DX1GCR0) -#define DDR0_PUB_DX1GCR1 (0x1000 + (0xC1 << 2)) -#define P_DDR0_PUB_DX1GCR1 MMC_REG_ADDR(DDR0_PUB_DX1GCR1) -#define DDR0_PUB_DX1GCR2 (0x1000 + (0xC2 << 2)) -#define P_DDR0_PUB_DX1GCR2 MMC_REG_ADDR(DDR0_PUB_DX1GCR2) -#define DDR0_PUB_DX1GCR3 (0x1000 + (0xC3 << 2)) -#define P_DDR0_PUB_DX1GCR3 MMC_REG_ADDR(DDR0_PUB_DX1GCR3) -#define DDR0_PUB_DX1GSR0 (0x1000 + (0xC4 << 2)) -#define P_DDR0_PUB_DX1GSR0 MMC_REG_ADDR(DDR0_PUB_DX1GSR0) -#define DDR0_PUB_DX1GSR1 (0x1000 + (0xC5 << 2)) -#define P_DDR0_PUB_DX1GSR1 MMC_REG_ADDR(DDR0_PUB_DX1GSR1) -#define DDR0_PUB_DX1GSR2 (0x1000 + (0xC6 << 2)) -#define P_DDR0_PUB_DX1GSR2 MMC_REG_ADDR(DDR0_PUB_DX1GSR2) -#define DDR0_PUB_DX1BDLR0 (0x1000 + (0xC7 << 2)) -#define P_DDR0_PUB_DX1BDLR0 MMC_REG_ADDR(DDR0_PUB_DX1BDLR0) -#define DDR0_PUB_DX1BDLR1 (0x1000 + (0xC8 << 2)) -#define P_DDR0_PUB_DX1BDLR1 MMC_REG_ADDR(DDR0_PUB_DX1BDLR1) -#define DDR0_PUB_DX1BDLR2 (0x1000 + (0xC9 << 2)) -#define P_DDR0_PUB_DX1BDLR2 MMC_REG_ADDR(DDR0_PUB_DX1BDLR2) -#define DDR0_PUB_DX1BDLR3 (0x1000 + (0xCA << 2)) -#define P_DDR0_PUB_DX1BDLR3 MMC_REG_ADDR(DDR0_PUB_DX1BDLR3) -#define DDR0_PUB_DX1BDLR4 (0x1000 + (0xCB << 2)) -#define P_DDR0_PUB_DX1BDLR4 MMC_REG_ADDR(DDR0_PUB_DX1BDLR4) -#define DDR0_PUB_DX1BDLR5 (0x1000 + (0xCC << 2)) -#define P_DDR0_PUB_DX1BDLR5 MMC_REG_ADDR(DDR0_PUB_DX1BDLR5) -#define DDR0_PUB_DX1BDLR6 (0x1000 + (0xCD << 2)) -#define P_DDR0_PUB_DX1BDLR6 MMC_REG_ADDR(DDR0_PUB_DX1BDLR6) -#define DDR0_PUB_DX1LCDLR0 (0x1000 + (0xCE << 2)) -#define P_DDR0_PUB_DX1LCDLR0 MMC_REG_ADDR(DDR0_PUB_DX1LCDLR0) -#define DDR0_PUB_DX1LCDLR1 (0x1000 + (0xCF << 2)) -#define P_DDR0_PUB_DX1LCDLR1 MMC_REG_ADDR(DDR0_PUB_DX1LCDLR1) -#define DDR0_PUB_DX1LCDLR2 (0x1000 + (0xD0 << 2)) -#define P_DDR0_PUB_DX1LCDLR2 MMC_REG_ADDR(DDR0_PUB_DX1LCDLR2) -#define DDR0_PUB_DX1MDLR (0x1000 + (0xD1 << 2)) -#define P_DDR0_PUB_DX1MDLR MMC_REG_ADDR(DDR0_PUB_DX1MDLR) -#define DDR0_PUB_DX1GTR (0x1000 + (0xD2 << 2)) -#define P_DDR0_PUB_DX1GTR MMC_REG_ADDR(DDR0_PUB_DX1GTR) -#define DDR0_PUB_DX2GCR0 (0x1000 + (0xE0 << 2)) -#define P_DDR0_PUB_DX2GCR0 MMC_REG_ADDR(DDR0_PUB_DX2GCR0) -#define DDR0_PUB_DX2GCR1 (0x1000 + (0xE1 << 2)) -#define P_DDR0_PUB_DX2GCR1 MMC_REG_ADDR(DDR0_PUB_DX2GCR1) -#define DDR0_PUB_DX2GCR2 (0x1000 + (0xE2 << 2)) -#define P_DDR0_PUB_DX2GCR2 MMC_REG_ADDR(DDR0_PUB_DX2GCR2) -#define DDR0_PUB_DX2GCR3 (0x1000 + (0xE3 << 2)) -#define P_DDR0_PUB_DX2GCR3 MMC_REG_ADDR(DDR0_PUB_DX2GCR3) -#define DDR0_PUB_DX2GSR0 (0x1000 + (0xE4 << 2)) -#define P_DDR0_PUB_DX2GSR0 MMC_REG_ADDR(DDR0_PUB_DX2GSR0) -#define DDR0_PUB_DX2GSR1 (0x1000 + (0xE5 << 2)) -#define P_DDR0_PUB_DX2GSR1 MMC_REG_ADDR(DDR0_PUB_DX2GSR1) -#define DDR0_PUB_DX2GSR2 (0x1000 + (0xE6 << 2)) -#define P_DDR0_PUB_DX2GSR2 MMC_REG_ADDR(DDR0_PUB_DX2GSR2) -#define DDR0_PUB_DX2BDLR0 (0x1000 + (0xE7 << 2)) -#define P_DDR0_PUB_DX2BDLR0 MMC_REG_ADDR(DDR0_PUB_DX2BDLR0) -#define DDR0_PUB_DX2BDLR1 (0x1000 + (0xE8 << 2)) -#define P_DDR0_PUB_DX2BDLR1 MMC_REG_ADDR(DDR0_PUB_DX2BDLR1) -#define DDR0_PUB_DX2BDLR2 (0x1000 + (0xE9 << 2)) -#define P_DDR0_PUB_DX2BDLR2 MMC_REG_ADDR(DDR0_PUB_DX2BDLR2) -#define DDR0_PUB_DX2BDLR3 (0x1000 + (0xEA << 2)) -#define P_DDR0_PUB_DX2BDLR3 MMC_REG_ADDR(DDR0_PUB_DX2BDLR3) -#define DDR0_PUB_DX2BDLR4 (0x1000 + (0xEB << 2)) -#define P_DDR0_PUB_DX2BDLR4 MMC_REG_ADDR(DDR0_PUB_DX2BDLR4) -#define DDR0_PUB_DX2BDLR5 (0x1000 + (0xEC << 2)) -#define P_DDR0_PUB_DX2BDLR5 MMC_REG_ADDR(DDR0_PUB_DX2BDLR5) -#define DDR0_PUB_DX2BDLR6 (0x1000 + (0xED << 2)) -#define P_DDR0_PUB_DX2BDLR6 MMC_REG_ADDR(DDR0_PUB_DX2BDLR6) -#define DDR0_PUB_DX2LCDLR0 (0x1000 + (0xEE << 2)) -#define P_DDR0_PUB_DX2LCDLR0 MMC_REG_ADDR(DDR0_PUB_DX2LCDLR0) -#define DDR0_PUB_DX2LCDLR1 (0x1000 + (0xEF << 2)) -#define P_DDR0_PUB_DX2LCDLR1 MMC_REG_ADDR(DDR0_PUB_DX2LCDLR1) -#define DDR0_PUB_DX2LCDLR2 (0x1000 + (0xF0 << 2)) -#define P_DDR0_PUB_DX2LCDLR2 MMC_REG_ADDR(DDR0_PUB_DX2LCDLR2) -#define DDR0_PUB_DX2MDLR (0x1000 + (0xF1 << 2)) -#define P_DDR0_PUB_DX2MDLR MMC_REG_ADDR(DDR0_PUB_DX2MDLR) -#define DDR0_PUB_DX2GTR (0x1000 + (0xF2 << 2)) -#define P_DDR0_PUB_DX2GTR MMC_REG_ADDR(DDR0_PUB_DX2GTR) -#define DDR0_PUB_DX3GCR0 (0x1000 + (0x100 << 2)) -#define P_DDR0_PUB_DX3GCR0 MMC_REG_ADDR(DDR0_PUB_DX3GCR0) -#define DDR0_PUB_DX3GCR1 (0x1000 + (0x101 << 2)) -#define P_DDR0_PUB_DX3GCR1 MMC_REG_ADDR(DDR0_PUB_DX3GCR1) -#define DDR0_PUB_DX3GCR2 (0x1000 + (0x102 << 2)) -#define P_DDR0_PUB_DX3GCR2 MMC_REG_ADDR(DDR0_PUB_DX3GCR2) -#define DDR0_PUB_DX3GCR3 (0x1000 + (0x103 << 2)) -#define P_DDR0_PUB_DX3GCR3 MMC_REG_ADDR(DDR0_PUB_DX3GCR3) -#define DDR0_PUB_DX3GSR0 (0x1000 + (0x104 << 2)) -#define P_DDR0_PUB_DX3GSR0 MMC_REG_ADDR(DDR0_PUB_DX3GSR0) -#define DDR0_PUB_DX3GSR1 (0x1000 + (0x105 << 2)) -#define P_DDR0_PUB_DX3GSR1 MMC_REG_ADDR(DDR0_PUB_DX3GSR1) -#define DDR0_PUB_DX3GSR2 (0x1000 + (0x106 << 2)) -#define P_DDR0_PUB_DX3GSR2 MMC_REG_ADDR(DDR0_PUB_DX3GSR2) -#define DDR0_PUB_DX3BDLR0 (0x1000 + (0x107 << 2)) -#define P_DDR0_PUB_DX3BDLR0 MMC_REG_ADDR(DDR0_PUB_DX3BDLR0) -#define DDR0_PUB_DX3BDLR1 (0x1000 + (0x108 << 2)) -#define P_DDR0_PUB_DX3BDLR1 MMC_REG_ADDR(DDR0_PUB_DX3BDLR1) -#define DDR0_PUB_DX3BDLR2 (0x1000 + (0x109 << 2)) -#define P_DDR0_PUB_DX3BDLR2 MMC_REG_ADDR(DDR0_PUB_DX3BDLR2) -#define DDR0_PUB_DX3BDLR3 (0x1000 + (0x10A << 2)) -#define P_DDR0_PUB_DX3BDLR3 MMC_REG_ADDR(DDR0_PUB_DX3BDLR3) -#define DDR0_PUB_DX3BDLR4 (0x1000 + (0x10B << 2)) -#define P_DDR0_PUB_DX3BDLR4 MMC_REG_ADDR(DDR0_PUB_DX3BDLR4) -#define DDR0_PUB_DX3BDLR5 (0x1000 + (0x10C << 2)) -#define P_DDR0_PUB_DX3BDLR5 MMC_REG_ADDR(DDR0_PUB_DX3BDLR5) -#define DDR0_PUB_DX3BDLR6 (0x1000 + (0x10D << 2)) -#define P_DDR0_PUB_DX3BDLR6 MMC_REG_ADDR(DDR0_PUB_DX3BDLR6) -#define DDR0_PUB_DX3LCDLR0 (0x1000 + (0x10E << 2)) -#define P_DDR0_PUB_DX3LCDLR0 MMC_REG_ADDR(DDR0_PUB_DX3LCDLR0) -#define DDR0_PUB_DX3LCDLR1 (0x1000 + (0x10F << 2)) -#define P_DDR0_PUB_DX3LCDLR1 MMC_REG_ADDR(DDR0_PUB_DX3LCDLR1) -#define DDR0_PUB_DX3LCDLR2 (0x1000 + (0x110 << 2)) -#define P_DDR0_PUB_DX3LCDLR2 MMC_REG_ADDR(DDR0_PUB_DX3LCDLR2) -#define DDR0_PUB_DX3MDLR (0x1000 + (0x111 << 2)) -#define P_DDR0_PUB_DX3MDLR MMC_REG_ADDR(DDR0_PUB_DX3MDLR) -#define DDR0_PUB_DX3GTR (0x1000 + (0x112 << 2)) -#define P_DDR0_PUB_DX3GTR MMC_REG_ADDR(DDR0_PUB_DX3GTR) -#define DDR0_PUB_DX4GCR0 (0x1000 + (0x120 << 2)) -#define P_DDR0_PUB_DX4GCR0 MMC_REG_ADDR(DDR0_PUB_DX4GCR0) -#define DDR0_PUB_DX4GCR1 (0x1000 + (0x121 << 2)) -#define P_DDR0_PUB_DX4GCR1 MMC_REG_ADDR(DDR0_PUB_DX4GCR1) -#define DDR0_PUB_DX4GCR2 (0x1000 + (0x122 << 2)) -#define P_DDR0_PUB_DX4GCR2 MMC_REG_ADDR(DDR0_PUB_DX4GCR2) -#define DDR0_PUB_DX4GCR3 (0x1000 + (0x123 << 2)) -#define P_DDR0_PUB_DX4GCR3 MMC_REG_ADDR(DDR0_PUB_DX4GCR3) -#define DDR0_PUB_DX4GSR0 (0x1000 + (0x124 << 2)) -#define P_DDR0_PUB_DX4GSR0 MMC_REG_ADDR(DDR0_PUB_DX4GSR0) -#define DDR0_PUB_DX4GSR1 (0x1000 + (0x125 << 2)) -#define P_DDR0_PUB_DX4GSR1 MMC_REG_ADDR(DDR0_PUB_DX4GSR1) -#define DDR0_PUB_DX4GSR2 (0x1000 + (0x126 << 2)) -#define P_DDR0_PUB_DX4GSR2 MMC_REG_ADDR(DDR0_PUB_DX4GSR2) -#define DDR0_PUB_DX4BDLR0 (0x1000 + (0x127 << 2)) -#define P_DDR0_PUB_DX4BDLR0 MMC_REG_ADDR(DDR0_PUB_DX4BDLR0) -#define DDR0_PUB_DX4BDLR1 (0x1000 + (0x128 << 2)) -#define P_DDR0_PUB_DX4BDLR1 MMC_REG_ADDR(DDR0_PUB_DX4BDLR1) -#define DDR0_PUB_DX4BDLR2 (0x1000 + (0x129 << 2)) -#define P_DDR0_PUB_DX4BDLR2 MMC_REG_ADDR(DDR0_PUB_DX4BDLR2) -#define DDR0_PUB_DX4BDLR3 (0x1000 + (0x12A << 2)) -#define P_DDR0_PUB_DX4BDLR3 MMC_REG_ADDR(DDR0_PUB_DX4BDLR3) -#define DDR0_PUB_DX4BDLR4 (0x1000 + (0x12B << 2)) -#define P_DDR0_PUB_DX4BDLR4 MMC_REG_ADDR(DDR0_PUB_DX4BDLR4) -#define DDR0_PUB_DX4BDLR5 (0x1000 + (0x12C << 2)) -#define P_DDR0_PUB_DX4BDLR5 MMC_REG_ADDR(DDR0_PUB_DX4BDLR5) -#define DDR0_PUB_DX4BDLR6 (0x1000 + (0x12D << 2)) -#define P_DDR0_PUB_DX4BDLR6 MMC_REG_ADDR(DDR0_PUB_DX4BDLR6) -#define DDR0_PUB_DX4LCDLR0 (0x1000 + (0x12E << 2)) -#define P_DDR0_PUB_DX4LCDLR0 MMC_REG_ADDR(DDR0_PUB_DX4LCDLR0) -#define DDR0_PUB_DX4LCDLR1 (0x1000 + (0x12F << 2)) -#define P_DDR0_PUB_DX4LCDLR1 MMC_REG_ADDR(DDR0_PUB_DX4LCDLR1) -#define DDR0_PUB_DX4LCDLR2 (0x1000 + (0x130 << 2)) -#define P_DDR0_PUB_DX4LCDLR2 MMC_REG_ADDR(DDR0_PUB_DX4LCDLR2) -#define DDR0_PUB_DX4MDLR (0x1000 + (0x131 << 2)) -#define P_DDR0_PUB_DX4MDLR MMC_REG_ADDR(DDR0_PUB_DX4MDLR) -#define DDR0_PUB_DX4GTR (0x1000 + (0x132 << 2)) -#define P_DDR0_PUB_DX4GTR MMC_REG_ADDR(DDR0_PUB_DX4GTR) -#define DDR0_PUB_DX5GCR0 (0x1000 + (0x140 << 2)) -#define P_DDR0_PUB_DX5GCR0 MMC_REG_ADDR(DDR0_PUB_DX5GCR0) -#define DDR0_PUB_DX5GCR1 (0x1000 + (0x141 << 2)) -#define P_DDR0_PUB_DX5GCR1 MMC_REG_ADDR(DDR0_PUB_DX5GCR1) -#define DDR0_PUB_DX5GCR2 (0x1000 + (0x142 << 2)) -#define P_DDR0_PUB_DX5GCR2 MMC_REG_ADDR(DDR0_PUB_DX5GCR2) -#define DDR0_PUB_DX5GCR3 (0x1000 + (0x143 << 2)) -#define P_DDR0_PUB_DX5GCR3 MMC_REG_ADDR(DDR0_PUB_DX5GCR3) -#define DDR0_PUB_DX5GSR0 (0x1000 + (0x144 << 2)) -#define P_DDR0_PUB_DX5GSR0 MMC_REG_ADDR(DDR0_PUB_DX5GSR0) -#define DDR0_PUB_DX5GSR1 (0x1000 + (0x145 << 2)) -#define P_DDR0_PUB_DX5GSR1 MMC_REG_ADDR(DDR0_PUB_DX5GSR1) -#define DDR0_PUB_DX5GSR2 (0x1000 + (0x146 << 2)) -#define P_DDR0_PUB_DX5GSR2 MMC_REG_ADDR(DDR0_PUB_DX5GSR2) -#define DDR0_PUB_DX5BDLR0 (0x1000 + (0x147 << 2)) -#define P_DDR0_PUB_DX5BDLR0 MMC_REG_ADDR(DDR0_PUB_DX5BDLR0) -#define DDR0_PUB_DX5BDLR1 (0x1000 + (0x148 << 2)) -#define P_DDR0_PUB_DX5BDLR1 MMC_REG_ADDR(DDR0_PUB_DX5BDLR1) -#define DDR0_PUB_DX5BDLR2 (0x1000 + (0x149 << 2)) -#define P_DDR0_PUB_DX5BDLR2 MMC_REG_ADDR(DDR0_PUB_DX5BDLR2) -#define DDR0_PUB_DX5BDLR3 (0x1000 + (0x14A << 2)) -#define P_DDR0_PUB_DX5BDLR3 MMC_REG_ADDR(DDR0_PUB_DX5BDLR3) -#define DDR0_PUB_DX5BDLR4 (0x1000 + (0x14B << 2)) -#define P_DDR0_PUB_DX5BDLR4 MMC_REG_ADDR(DDR0_PUB_DX5BDLR4) -#define DDR0_PUB_DX5BDLR5 (0x1000 + (0x14C << 2)) -#define P_DDR0_PUB_DX5BDLR5 MMC_REG_ADDR(DDR0_PUB_DX5BDLR5) -#define DDR0_PUB_DX5BDLR6 (0x1000 + (0x14D << 2)) -#define P_DDR0_PUB_DX5BDLR6 MMC_REG_ADDR(DDR0_PUB_DX5BDLR6) -#define DDR0_PUB_DX5LCDLR0 (0x1000 + (0x14E << 2)) -#define P_DDR0_PUB_DX5LCDLR0 MMC_REG_ADDR(DDR0_PUB_DX5LCDLR0) -#define DDR0_PUB_DX5LCDLR1 (0x1000 + (0x14F << 2)) -#define P_DDR0_PUB_DX5LCDLR1 MMC_REG_ADDR(DDR0_PUB_DX5LCDLR1) -#define DDR0_PUB_DX5LCDLR2 (0x1000 + (0x150 << 2)) -#define P_DDR0_PUB_DX5LCDLR2 MMC_REG_ADDR(DDR0_PUB_DX5LCDLR2) -#define DDR0_PUB_DX5MDLR (0x1000 + (0x151 << 2)) -#define P_DDR0_PUB_DX5MDLR MMC_REG_ADDR(DDR0_PUB_DX5MDLR) -#define DDR0_PUB_DX5GTR (0x1000 + (0x152 << 2)) -#define P_DDR0_PUB_DX5GTR MMC_REG_ADDR(DDR0_PUB_DX5GTR) -#define DDR0_PUB_DX6GCR0 (0x1000 + (0x160 << 2)) -#define P_DDR0_PUB_DX6GCR0 MMC_REG_ADDR(DDR0_PUB_DX6GCR0) -#define DDR0_PUB_DX6GCR1 (0x1000 + (0x161 << 2)) -#define P_DDR0_PUB_DX6GCR1 MMC_REG_ADDR(DDR0_PUB_DX6GCR1) -#define DDR0_PUB_DX6GCR2 (0x1000 + (0x162 << 2)) -#define P_DDR0_PUB_DX6GCR2 MMC_REG_ADDR(DDR0_PUB_DX6GCR2) -#define DDR0_PUB_DX6GCR3 (0x1000 + (0x163 << 2)) -#define P_DDR0_PUB_DX6GCR3 MMC_REG_ADDR(DDR0_PUB_DX6GCR3) -#define DDR0_PUB_DX6GSR0 (0x1000 + (0x164 << 2)) -#define P_DDR0_PUB_DX6GSR0 MMC_REG_ADDR(DDR0_PUB_DX6GSR0) -#define DDR0_PUB_DX6GSR1 (0x1000 + (0x165 << 2)) -#define P_DDR0_PUB_DX6GSR1 MMC_REG_ADDR(DDR0_PUB_DX6GSR1) -#define DDR0_PUB_DX6GSR2 (0x1000 + (0x166 << 2)) -#define P_DDR0_PUB_DX6GSR2 MMC_REG_ADDR(DDR0_PUB_DX6GSR2) -#define DDR0_PUB_DX6BDLR0 (0x1000 + (0x167 << 2)) -#define P_DDR0_PUB_DX6BDLR0 MMC_REG_ADDR(DDR0_PUB_DX6BDLR0) -#define DDR0_PUB_DX6BDLR1 (0x1000 + (0x168 << 2)) -#define P_DDR0_PUB_DX6BDLR1 MMC_REG_ADDR(DDR0_PUB_DX6BDLR1) -#define DDR0_PUB_DX6BDLR2 (0x1000 + (0x169 << 2)) -#define P_DDR0_PUB_DX6BDLR2 MMC_REG_ADDR(DDR0_PUB_DX6BDLR2) -#define DDR0_PUB_DX6BDLR3 (0x1000 + (0x16A << 2)) -#define P_DDR0_PUB_DX6BDLR3 MMC_REG_ADDR(DDR0_PUB_DX6BDLR3) -#define DDR0_PUB_DX6BDLR4 (0x1000 + (0x16B << 2)) -#define P_DDR0_PUB_DX6BDLR4 MMC_REG_ADDR(DDR0_PUB_DX6BDLR4) -#define DDR0_PUB_DX6BDLR5 (0x1000 + (0x16C << 2)) -#define P_DDR0_PUB_DX6BDLR5 MMC_REG_ADDR(DDR0_PUB_DX6BDLR5) -#define DDR0_PUB_DX6BDLR6 (0x1000 + (0x16D << 2)) -#define P_DDR0_PUB_DX6BDLR6 MMC_REG_ADDR(DDR0_PUB_DX6BDLR6) -#define DDR0_PUB_DX6LCDLR0 (0x1000 + (0x16E << 2)) -#define P_DDR0_PUB_DX6LCDLR0 MMC_REG_ADDR(DDR0_PUB_DX6LCDLR0) -#define DDR0_PUB_DX6LCDLR1 (0x1000 + (0x16F << 2)) -#define P_DDR0_PUB_DX6LCDLR1 MMC_REG_ADDR(DDR0_PUB_DX6LCDLR1) -#define DDR0_PUB_DX6LCDLR2 (0x1000 + (0x170 << 2)) -#define P_DDR0_PUB_DX6LCDLR2 MMC_REG_ADDR(DDR0_PUB_DX6LCDLR2) -#define DDR0_PUB_DX6MDLR (0x1000 + (0x171 << 2)) -#define P_DDR0_PUB_DX6MDLR MMC_REG_ADDR(DDR0_PUB_DX6MDLR) -#define DDR0_PUB_DX6GTR (0x1000 + (0x172 << 2)) -#define P_DDR0_PUB_DX6GTR MMC_REG_ADDR(DDR0_PUB_DX6GTR) -#define DDR0_PUB_DX7GCR0 (0x1000 + (0x180 << 2)) -#define P_DDR0_PUB_DX7GCR0 MMC_REG_ADDR(DDR0_PUB_DX7GCR0) -#define DDR0_PUB_DX7GCR1 (0x1000 + (0x181 << 2)) -#define P_DDR0_PUB_DX7GCR1 MMC_REG_ADDR(DDR0_PUB_DX7GCR1) -#define DDR0_PUB_DX7GCR2 (0x1000 + (0x182 << 2)) -#define P_DDR0_PUB_DX7GCR2 MMC_REG_ADDR(DDR0_PUB_DX7GCR2) -#define DDR0_PUB_DX7GCR3 (0x1000 + (0x183 << 2)) -#define P_DDR0_PUB_DX7GCR3 MMC_REG_ADDR(DDR0_PUB_DX7GCR3) -#define DDR0_PUB_DX7GSR0 (0x1000 + (0x184 << 2)) -#define P_DDR0_PUB_DX7GSR0 MMC_REG_ADDR(DDR0_PUB_DX7GSR0) -#define DDR0_PUB_DX7GSR1 (0x1000 + (0x185 << 2)) -#define P_DDR0_PUB_DX7GSR1 MMC_REG_ADDR(DDR0_PUB_DX7GSR1) -#define DDR0_PUB_DX7GSR2 (0x1000 + (0x186 << 2)) -#define P_DDR0_PUB_DX7GSR2 MMC_REG_ADDR(DDR0_PUB_DX7GSR2) -#define DDR0_PUB_DX7BDLR0 (0x1000 + (0x187 << 2)) -#define P_DDR0_PUB_DX7BDLR0 MMC_REG_ADDR(DDR0_PUB_DX7BDLR0) -#define DDR0_PUB_DX7BDLR1 (0x1000 + (0x188 << 2)) -#define P_DDR0_PUB_DX7BDLR1 MMC_REG_ADDR(DDR0_PUB_DX7BDLR1) -#define DDR0_PUB_DX7BDLR2 (0x1000 + (0x189 << 2)) -#define P_DDR0_PUB_DX7BDLR2 MMC_REG_ADDR(DDR0_PUB_DX7BDLR2) -#define DDR0_PUB_DX7BDLR3 (0x1000 + (0x18A << 2)) -#define P_DDR0_PUB_DX7BDLR3 MMC_REG_ADDR(DDR0_PUB_DX7BDLR3) -#define DDR0_PUB_DX7BDLR4 (0x1000 + (0x18B << 2)) -#define P_DDR0_PUB_DX7BDLR4 MMC_REG_ADDR(DDR0_PUB_DX7BDLR4) -#define DDR0_PUB_DX7BDLR5 (0x1000 + (0x18C << 2)) -#define P_DDR0_PUB_DX7BDLR5 MMC_REG_ADDR(DDR0_PUB_DX7BDLR5) -#define DDR0_PUB_DX7BDLR6 (0x1000 + (0x18D << 2)) -#define P_DDR0_PUB_DX7BDLR6 MMC_REG_ADDR(DDR0_PUB_DX7BDLR6) -#define DDR0_PUB_DX7LCDLR0 (0x1000 + (0x18E << 2)) -#define P_DDR0_PUB_DX7LCDLR0 MMC_REG_ADDR(DDR0_PUB_DX7LCDLR0) -#define DDR0_PUB_DX7LCDLR1 (0x1000 + (0x18F << 2)) -#define P_DDR0_PUB_DX7LCDLR1 MMC_REG_ADDR(DDR0_PUB_DX7LCDLR1) -#define DDR0_PUB_DX7LCDLR2 (0x1000 + (0x190 << 2)) -#define P_DDR0_PUB_DX7LCDLR2 MMC_REG_ADDR(DDR0_PUB_DX7LCDLR2) -#define DDR0_PUB_DX7MDLR (0x1000 + (0x191 << 2)) -#define P_DDR0_PUB_DX7MDLR MMC_REG_ADDR(DDR0_PUB_DX7MDLR) -#define DDR0_PUB_DX7GTR (0x1000 + (0x192 << 2)) -#define P_DDR0_PUB_DX7GTR MMC_REG_ADDR(DDR0_PUB_DX7GTR) -#define DDR0_PUB_DX8GCR0 (0x1000 + (0x1A0 << 2)) -#define P_DDR0_PUB_DX8GCR0 MMC_REG_ADDR(DDR0_PUB_DX8GCR0) -#define DDR0_PUB_DX8GCR1 (0x1000 + (0x1A1 << 2)) -#define P_DDR0_PUB_DX8GCR1 MMC_REG_ADDR(DDR0_PUB_DX8GCR1) -#define DDR0_PUB_DX8GCR2 (0x1000 + (0x1A2 << 2)) -#define P_DDR0_PUB_DX8GCR2 MMC_REG_ADDR(DDR0_PUB_DX8GCR2) -#define DDR0_PUB_DX8GCR3 (0x1000 + (0x1A3 << 2)) -#define P_DDR0_PUB_DX8GCR3 MMC_REG_ADDR(DDR0_PUB_DX8GCR3) -#define DDR0_PUB_DX8GSR0 (0x1000 + (0x1A4 << 2)) -#define P_DDR0_PUB_DX8GSR0 MMC_REG_ADDR(DDR0_PUB_DX8GSR0) -#define DDR0_PUB_DX8GSR1 (0x1000 + (0x1A5 << 2)) -#define P_DDR0_PUB_DX8GSR1 MMC_REG_ADDR(DDR0_PUB_DX8GSR1) -#define DDR0_PUB_DX8GSR2 (0x1000 + (0x1A6 << 2)) -#define P_DDR0_PUB_DX8GSR2 MMC_REG_ADDR(DDR0_PUB_DX8GSR2) -#define DDR0_PUB_DX8BDLR0 (0x1000 + (0x1A7 << 2)) -#define P_DDR0_PUB_DX8BDLR0 MMC_REG_ADDR(DDR0_PUB_DX8BDLR0) -#define DDR0_PUB_DX8BDLR1 (0x1000 + (0x1A8 << 2)) -#define P_DDR0_PUB_DX8BDLR1 MMC_REG_ADDR(DDR0_PUB_DX8BDLR1) -#define DDR0_PUB_DX8BDLR2 (0x1000 + (0x1A9 << 2)) -#define P_DDR0_PUB_DX8BDLR2 MMC_REG_ADDR(DDR0_PUB_DX8BDLR2) -#define DDR0_PUB_DX8BDLR3 (0x1000 + (0x1AA << 2)) -#define P_DDR0_PUB_DX8BDLR3 MMC_REG_ADDR(DDR0_PUB_DX8BDLR3) -#define DDR0_PUB_DX8BDLR4 (0x1000 + (0x1AB << 2)) -#define P_DDR0_PUB_DX8BDLR4 MMC_REG_ADDR(DDR0_PUB_DX8BDLR4) -#define DDR0_PUB_DX8BDLR5 (0x1000 + (0x1AC << 2)) -#define P_DDR0_PUB_DX8BDLR5 MMC_REG_ADDR(DDR0_PUB_DX8BDLR5) -#define DDR0_PUB_DX8BDLR6 (0x1000 + (0x1AD << 2)) -#define P_DDR0_PUB_DX8BDLR6 MMC_REG_ADDR(DDR0_PUB_DX8BDLR6) -#define DDR0_PUB_DX8LCDLR0 (0x1000 + (0x1AE << 2)) -#define P_DDR0_PUB_DX8LCDLR0 MMC_REG_ADDR(DDR0_PUB_DX8LCDLR0) -#define DDR0_PUB_DX8LCDLR1 (0x1000 + (0x1AF << 2)) -#define P_DDR0_PUB_DX8LCDLR1 MMC_REG_ADDR(DDR0_PUB_DX8LCDLR1) -#define DDR0_PUB_DX8LCDLR2 (0x1000 + (0x1B0 << 2)) -#define P_DDR0_PUB_DX8LCDLR2 MMC_REG_ADDR(DDR0_PUB_DX8LCDLR2) -#define DDR0_PUB_DX8MDLR (0x1000 + (0x1B1 << 2)) -#define P_DDR0_PUB_DX8MDLR MMC_REG_ADDR(DDR0_PUB_DX8MDLR) -#define DDR0_PUB_DX8GTR (0x1000 + (0x1B2 << 2)) -#define P_DDR0_PUB_DX8GTR MMC_REG_ADDR(DDR0_PUB_DX8GTR) - -#define DDR1_PCTL_DFILPCFG0 0x22f0 -#define P_DDR1_PCTL_DFILPCFG0 MMC_REG_ADDR(DDR1_PCTL_DFILPCFG0) -#define DDR1_PCTL_DFITRWRLVLDELAY0 0x2318 -#define P_DDR1_PCTL_DFITRWRLVLDELAY0 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLDELAY0) -#define DDR1_PCTL_DFITRWRLVLDELAY1 0x231c -#define P_DDR1_PCTL_DFITRWRLVLDELAY1 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLDELAY1) -#define DDR1_PCTL_DFITRWRLVLDELAY2 0x2320 -#define P_DDR1_PCTL_DFITRWRLVLDELAY2 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLDELAY2) -#define DDR1_PCTL_DFITRRDLVLRESP0 0x230c -#define P_DDR1_PCTL_DFITRRDLVLRESP0 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLRESP0) -#define DDR1_PCTL_DFITRRDLVLRESP1 0x2310 -#define P_DDR1_PCTL_DFITRRDLVLRESP1 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLRESP1) -#define DDR1_PCTL_DFITRRDLVLRESP2 0x2314 -#define P_DDR1_PCTL_DFITRRDLVLRESP2 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLRESP2) -#define DDR1_PCTL_DFITRWRLVLRESP0 0x2300 -#define P_DDR1_PCTL_DFITRWRLVLRESP0 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLRESP0) -#define DDR1_PCTL_DFITRRDLVLDELAY0 0x2324 -#define P_DDR1_PCTL_DFITRRDLVLDELAY0 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLDELAY0) -#define DDR1_PCTL_DFITRWRLVLRESP1 0x2304 -#define P_DDR1_PCTL_DFITRWRLVLRESP1 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLRESP1) -#define DDR1_PCTL_DFITRRDLVLDELAY2 0x232c -#define P_DDR1_PCTL_DFITRRDLVLDELAY2 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLDELAY2) -#define DDR1_PCTL_DFITRWRLVLRESP2 0x2308 -#define P_DDR1_PCTL_DFITRWRLVLRESP2 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLRESP2) -#define DDR1_PCTL_DFITRRDLVLGATEDELAY0 0x2330 -#define P_DDR1_PCTL_DFITRRDLVLGATEDELAY0 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLGATEDELAY0) -#define DDR1_PCTL_DFITRCMD 0x233c -#define P_DDR1_PCTL_DFITRCMD MMC_REG_ADDR(DDR1_PCTL_DFITRCMD) -#define DDR1_PCTL_DFITRRDLVLGATEDELAY1 0x2334 -#define P_DDR1_PCTL_DFITRRDLVLGATEDELAY1 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLGATEDELAY1) -#define DDR1_PCTL_DFITRRDLVLGATEDELAY2 0x2338 -#define P_DDR1_PCTL_DFITRRDLVLGATEDELAY2 \ - MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLGATEDELAY2) -#define DDR1_PCTL_IPTR 0x23fc -#define P_DDR1_PCTL_IPTR MMC_REG_ADDR(DDR1_PCTL_IPTR) -#define DDR1_PCTL_IPVR 0x23f8 -#define P_DDR1_PCTL_IPVR MMC_REG_ADDR(DDR1_PCTL_IPVR) -#define DDR1_PUB_RIDR (0x3000 + (0x00 << 2)) -#define P_DDR1_PUB_RIDR MMC_REG_ADDR(DDR1_PUB_RIDR) -#define DDR1_PUB_PIR (0x3000 + (0x01 << 2)) -#define P_DDR1_PUB_PIR MMC_REG_ADDR(DDR1_PUB_PIR) -#define DDR1_PUB_PGCR0 (0x3000 + (0x02 << 2)) -#define P_DDR1_PUB_PGCR0 MMC_REG_ADDR(DDR1_PUB_PGCR0) -#define DDR1_PUB_PGCR1 (0x3000 + (0x03 << 2)) -#define P_DDR1_PUB_PGCR1 MMC_REG_ADDR(DDR1_PUB_PGCR1) -#define DDR1_PUB_PGCR2 (0x3000 + (0x04 << 2)) -#define P_DDR1_PUB_PGCR2 MMC_REG_ADDR(DDR1_PUB_PGCR2) -#define DDR1_PUB_PGCR3 (0x3000 + (0x05 << 2)) -#define P_DDR1_PUB_PGCR3 MMC_REG_ADDR(DDR1_PUB_PGCR3) -#define DDR1_PUB_PGSR0 (0x3000 + (0x06 << 2)) -#define P_DDR1_PUB_PGSR0 MMC_REG_ADDR(DDR1_PUB_PGSR0) -#define DDR1_PUB_PGSR1 (0x3000 + (0x07 << 2)) -#define P_DDR1_PUB_PGSR1 MMC_REG_ADDR(DDR1_PUB_PGSR1) -#define DDR1_PUB_PLLCR (0x3000 + (0x08 << 2)) -#define P_DDR1_PUB_PLLCR MMC_REG_ADDR(DDR1_PUB_PLLCR) -#define DDR1_PUB_PTR0 (0x3000 + (0x09 << 2)) -#define P_DDR1_PUB_PTR0 MMC_REG_ADDR(DDR1_PUB_PTR0) -#define DDR1_PUB_PTR1 (0x3000 + (0x0A << 2)) -#define P_DDR1_PUB_PTR1 MMC_REG_ADDR(DDR1_PUB_PTR1) -#define DDR1_PUB_PTR2 (0x3000 + (0x0B << 2)) -#define P_DDR1_PUB_PTR2 MMC_REG_ADDR(DDR1_PUB_PTR2) -#define DDR1_PUB_PTR3 (0x3000 + (0x0C << 2)) -#define P_DDR1_PUB_PTR3 MMC_REG_ADDR(DDR1_PUB_PTR3) -#define DDR1_PUB_PTR4 (0x3000 + (0x0D << 2)) -#define P_DDR1_PUB_PTR4 MMC_REG_ADDR(DDR1_PUB_PTR4) -#define DDR1_PUB_ACMDLR (0x3000 + (0x0E << 2)) -#define P_DDR1_PUB_ACMDLR MMC_REG_ADDR(DDR1_PUB_ACMDLR) -#define DDR1_PUB_ACLCDLR (0x3000 + (0x0F << 2)) -#define P_DDR1_PUB_ACLCDLR MMC_REG_ADDR(DDR1_PUB_ACLCDLR) -#define DDR1_PUB_ACBDLR0 (0x3000 + (0x10 << 2)) -#define P_DDR1_PUB_ACBDLR0 MMC_REG_ADDR(DDR1_PUB_ACBDLR0) -#define DDR1_PUB_ACBDLR1 (0x3000 + (0x11 << 2)) -#define P_DDR1_PUB_ACBDLR1 MMC_REG_ADDR(DDR1_PUB_ACBDLR1) -#define DDR1_PUB_ACBDLR2 (0x3000 + (0x12 << 2)) -#define P_DDR1_PUB_ACBDLR2 MMC_REG_ADDR(DDR1_PUB_ACBDLR2) -#define DDR1_PUB_ACBDLR3 (0x3000 + (0x13 << 2)) -#define P_DDR1_PUB_ACBDLR3 MMC_REG_ADDR(DDR1_PUB_ACBDLR3) -#define DDR1_PUB_ACBDLR4 (0x3000 + (0x14 << 2)) -#define P_DDR1_PUB_ACBDLR4 MMC_REG_ADDR(DDR1_PUB_ACBDLR4) -#define DDR1_PUB_ACBDLR5 (0x3000 + (0x15 << 2)) -#define P_DDR1_PUB_ACBDLR5 MMC_REG_ADDR(DDR1_PUB_ACBDLR5) -#define DDR1_PUB_ACBDLR6 (0x3000 + (0x16 << 2)) -#define P_DDR1_PUB_ACBDLR6 MMC_REG_ADDR(DDR1_PUB_ACBDLR6) -#define DDR1_PUB_ACBDLR7 (0x3000 + (0x17 << 2)) -#define P_DDR1_PUB_ACBDLR7 MMC_REG_ADDR(DDR1_PUB_ACBDLR7) -#define DDR1_PUB_ACBDLR8 (0x3000 + (0x18 << 2)) -#define P_DDR1_PUB_ACBDLR8 MMC_REG_ADDR(DDR1_PUB_ACBDLR8) -#define DDR1_PUB_ACBDLR9 (0x3000 + (0x19 << 2)) -#define P_DDR1_PUB_ACBDLR9 MMC_REG_ADDR(DDR1_PUB_ACBDLR9) -#define DDR1_PUB_ACIOCR0 (0x3000 + (0x1A << 2)) -#define P_DDR1_PUB_ACIOCR0 MMC_REG_ADDR(DDR1_PUB_ACIOCR0) -#define DDR1_PUB_ACIOCR1 (0x3000 + (0x1B << 2)) -#define P_DDR1_PUB_ACIOCR1 MMC_REG_ADDR(DDR1_PUB_ACIOCR1) -#define DDR1_PUB_ACIOCR2 (0x3000 + (0x1C << 2)) -#define P_DDR1_PUB_ACIOCR2 MMC_REG_ADDR(DDR1_PUB_ACIOCR2) -#define DDR1_PUB_ACIOCR3 (0x3000 + (0x1D << 2)) -#define P_DDR1_PUB_ACIOCR3 MMC_REG_ADDR(DDR1_PUB_ACIOCR3) -#define DDR1_PUB_ACIOCR4 (0x3000 + (0x1E << 2)) -#define P_DDR1_PUB_ACIOCR4 MMC_REG_ADDR(DDR1_PUB_ACIOCR4) -#define DDR1_PUB_ACIOCR5 (0x3000 + (0x1F << 2)) -#define P_DDR1_PUB_ACIOCR5 MMC_REG_ADDR(DDR1_PUB_ACIOCR5) -#define DDR1_PUB_DXCCR (0x3000 + (0x20 << 2)) -#define P_DDR1_PUB_DXCCR MMC_REG_ADDR(DDR1_PUB_DXCCR) -#define DDR1_PUB_DSGCR (0x3000 + (0x21 << 2)) -#define P_DDR1_PUB_DSGCR MMC_REG_ADDR(DDR1_PUB_DSGCR) -#define DDR1_PUB_DCR (0x3000 + (0x22 << 2)) -#define P_DDR1_PUB_DCR MMC_REG_ADDR(DDR1_PUB_DCR) -#define DDR1_PUB_DTPR0 (0x3000 + (0x23 << 2)) -#define P_DDR1_PUB_DTPR0 MMC_REG_ADDR(DDR1_PUB_DTPR0) -#define DDR1_PUB_DTPR1 (0x3000 + (0x24 << 2)) -#define P_DDR1_PUB_DTPR1 MMC_REG_ADDR(DDR1_PUB_DTPR1) -#define DDR1_PUB_DTPR2 (0x3000 + (0x25 << 2)) -#define P_DDR1_PUB_DTPR2 MMC_REG_ADDR(DDR1_PUB_DTPR2) -#define DDR1_PUB_DTPR3 (0x3000 + (0x26 << 2)) -#define P_DDR1_PUB_DTPR3 MMC_REG_ADDR(DDR1_PUB_DTPR3) -#define DDR1_PUB_MR0 (0x3000 + (0x27 << 2)) -#define P_DDR1_PUB_MR0 MMC_REG_ADDR(DDR1_PUB_MR0) -#define DDR1_PUB_MR1 (0x3000 + (0x28 << 2)) -#define P_DDR1_PUB_MR1 MMC_REG_ADDR(DDR1_PUB_MR1) -#define DDR1_PUB_MR2 (0x3000 + (0x29 << 2)) -#define P_DDR1_PUB_MR2 MMC_REG_ADDR(DDR1_PUB_MR2) -#define DDR1_PUB_MR3 (0x3000 + (0x2A << 2)) -#define P_DDR1_PUB_MR3 MMC_REG_ADDR(DDR1_PUB_MR3) -#define DDR1_PUB_ODTCR (0x3000 + (0x2B << 2)) -#define P_DDR1_PUB_ODTCR MMC_REG_ADDR(DDR1_PUB_ODTCR) -#define DDR1_PUB_DTCR (0x3000 + (0x2C << 2)) -#define P_DDR1_PUB_DTCR MMC_REG_ADDR(DDR1_PUB_DTCR) -#define DDR1_PUB_DTAR0 (0x3000 + (0x2D << 2)) -#define P_DDR1_PUB_DTAR0 MMC_REG_ADDR(DDR1_PUB_DTAR0) -#define DDR1_PUB_DTAR1 (0x3000 + (0x2E << 2)) -#define P_DDR1_PUB_DTAR1 MMC_REG_ADDR(DDR1_PUB_DTAR1) -#define DDR1_PUB_DTAR2 (0x3000 + (0x2F << 2)) -#define P_DDR1_PUB_DTAR2 MMC_REG_ADDR(DDR1_PUB_DTAR2) -#define DDR1_PUB_DTAR3 (0x3000 + (0x30 << 2)) -#define P_DDR1_PUB_DTAR3 MMC_REG_ADDR(DDR1_PUB_DTAR3) -#define DDR1_PUB_DTDR0 (0x3000 + (0x31 << 2)) -#define P_DDR1_PUB_DTDR0 MMC_REG_ADDR(DDR1_PUB_DTDR0) -#define DDR1_PUB_DTDR1 (0x3000 + (0x32 << 2)) -#define P_DDR1_PUB_DTDR1 MMC_REG_ADDR(DDR1_PUB_DTDR1) -#define DDR1_PUB_DTEDR0 (0x3000 + (0x33 << 2)) -#define P_DDR1_PUB_DTEDR0 MMC_REG_ADDR(DDR1_PUB_DTEDR0) -#define DDR1_PUB_DTEDR1 (0x3000 + (0x34 << 2)) -#define P_DDR1_PUB_DTEDR1 MMC_REG_ADDR(DDR1_PUB_DTEDR1) -#define DDR1_PUB_RDIMMGCR0 (0x3000 + (0x35 << 2)) -#define P_DDR1_PUB_RDIMMGCR0 MMC_REG_ADDR(DDR1_PUB_RDIMMGCR0) -#define DDR1_PUB_RDIMMGCR1 (0x3000 + (0x36 << 2)) -#define P_DDR1_PUB_RDIMMGCR1 MMC_REG_ADDR(DDR1_PUB_RDIMMGCR1) -#define DDR1_PUB_RDIMMCR0 (0x3000 + (0x37 << 2)) -#define P_DDR1_PUB_RDIMMCR0 MMC_REG_ADDR(DDR1_PUB_RDIMMCR0) -#define DDR1_PUB_RDIMMCR1 (0x3000 + (0x38 << 2)) -#define P_DDR1_PUB_RDIMMCR1 MMC_REG_ADDR(DDR1_PUB_RDIMMCR1) -#define DDR1_PUB_GPR0 (0x3000 + (0x39 << 2)) -#define P_DDR1_PUB_GPR0 MMC_REG_ADDR(DDR1_PUB_GPR0) -#define DDR1_PUB_GPR1 (0x3000 + (0x3A << 2)) -#define P_DDR1_PUB_GPR1 MMC_REG_ADDR(DDR1_PUB_GPR1) -#define DDR1_PUB_CATR0 (0x3000 + (0x3B << 2)) -#define P_DDR1_PUB_CATR0 MMC_REG_ADDR(DDR1_PUB_CATR0) -#define DDR1_PUB_CATR1 (0x3000 + (0x3C << 2)) -#define P_DDR1_PUB_CATR1 MMC_REG_ADDR(DDR1_PUB_CATR1) -#define DDR1_PUB_DCUAR (0x3000 + (0x60 << 2)) -#define P_DDR1_PUB_DCUAR MMC_REG_ADDR(DDR1_PUB_DCUAR) -#define DDR1_PUB_DCUDR (0x3000 + (0x61 << 2)) -#define P_DDR1_PUB_DCUDR MMC_REG_ADDR(DDR1_PUB_DCUDR) -#define DDR1_PUB_DCURR (0x3000 + (0x62 << 2)) -#define P_DDR1_PUB_DCURR MMC_REG_ADDR(DDR1_PUB_DCURR) -#define DDR1_PUB_DCULR (0x3000 + (0x63 << 2)) -#define P_DDR1_PUB_DCULR MMC_REG_ADDR(DDR1_PUB_DCULR) -#define DDR1_PUB_DCUGCR (0x3000 + (0x64 << 2)) -#define P_DDR1_PUB_DCUGCR MMC_REG_ADDR(DDR1_PUB_DCUGCR) -#define DDR1_PUB_DCUTPR (0x3000 + (0x65 << 2)) -#define P_DDR1_PUB_DCUTPR MMC_REG_ADDR(DDR1_PUB_DCUTPR) -#define DDR1_PUB_DCUSR0 (0x3000 + (0x66 << 2)) -#define P_DDR1_PUB_DCUSR0 MMC_REG_ADDR(DDR1_PUB_DCUSR0) -#define DDR1_PUB_DCUSR1 (0x3000 + (0x67 << 2)) -#define P_DDR1_PUB_DCUSR1 MMC_REG_ADDR(DDR1_PUB_DCUSR1) -#define DDR1_PUB_BISTRR (0x3000 + (0x70 << 2)) -#define P_DDR1_PUB_BISTRR MMC_REG_ADDR(DDR1_PUB_BISTRR) -#define DDR1_PUB_BISTWCR (0x3000 + (0x71 << 2)) -#define P_DDR1_PUB_BISTWCR MMC_REG_ADDR(DDR1_PUB_BISTWCR) -#define DDR1_PUB_BISTMSKR0 (0x3000 + (0x72 << 2)) -#define P_DDR1_PUB_BISTMSKR0 MMC_REG_ADDR(DDR1_PUB_BISTMSKR0) -#define DDR1_PUB_BISTMSKR1 (0x3000 + (0x73 << 2)) -#define P_DDR1_PUB_BISTMSKR1 MMC_REG_ADDR(DDR1_PUB_BISTMSKR1) -#define DDR1_PUB_BISTMSKR2 (0x3000 + (0x74 << 2)) -#define P_DDR1_PUB_BISTMSKR2 MMC_REG_ADDR(DDR1_PUB_BISTMSKR2) -#define DDR1_PUB_BISTLSR (0x3000 + (0x75 << 2)) -#define P_DDR1_PUB_BISTLSR MMC_REG_ADDR(DDR1_PUB_BISTLSR) -#define DDR1_PUB_BISTAR0 (0x3000 + (0x76 << 2)) -#define P_DDR1_PUB_BISTAR0 MMC_REG_ADDR(DDR1_PUB_BISTAR0) -#define DDR1_PUB_BISTAR1 (0x3000 + (0x77 << 2)) -#define P_DDR1_PUB_BISTAR1 MMC_REG_ADDR(DDR1_PUB_BISTAR1) -#define DDR1_PUB_BISTAR2 (0x3000 + (0x78 << 2)) -#define P_DDR1_PUB_BISTAR2 MMC_REG_ADDR(DDR1_PUB_BISTAR2) -#define DDR1_PUB_BISTUDPR (0x3000 + (0x79 << 2)) -#define P_DDR1_PUB_BISTUDPR MMC_REG_ADDR(DDR1_PUB_BISTUDPR) -#define DDR1_PUB_BISTGSR (0x3000 + (0x7A << 2)) -#define P_DDR1_PUB_BISTGSR MMC_REG_ADDR(DDR1_PUB_BISTGSR) -#define DDR1_PUB_BISTWER (0x3000 + (0x7B << 2)) -#define P_DDR1_PUB_BISTWER MMC_REG_ADDR(DDR1_PUB_BISTWER) -#define DDR1_PUB_BISTBER0 (0x3000 + (0x7C << 2)) -#define P_DDR1_PUB_BISTBER0 MMC_REG_ADDR(DDR1_PUB_BISTBER0) -#define DDR1_PUB_BISTBER1 (0x3000 + (0x7D << 2)) -#define P_DDR1_PUB_BISTBER1 MMC_REG_ADDR(DDR1_PUB_BISTBER1) -#define DDR1_PUB_BISTBER2 (0x3000 + (0x7E << 2)) -#define P_DDR1_PUB_BISTBER2 MMC_REG_ADDR(DDR1_PUB_BISTBER2) -#define DDR1_PUB_BISTBER3 (0x3000 + (0x7F << 2)) -#define P_DDR1_PUB_BISTBER3 MMC_REG_ADDR(DDR1_PUB_BISTBER3) -#define DDR1_PUB_BISTWCSR (0x3000 + (0x80 << 2)) -#define P_DDR1_PUB_BISTWCSR MMC_REG_ADDR(DDR1_PUB_BISTWCSR) -#define DDR1_PUB_BISTFWR0 (0x3000 + (0x81 << 2)) -#define P_DDR1_PUB_BISTFWR0 MMC_REG_ADDR(DDR1_PUB_BISTFWR0) -#define DDR1_PUB_BISTFWR1 (0x3000 + (0x82 << 2)) -#define P_DDR1_PUB_BISTFWR1 MMC_REG_ADDR(DDR1_PUB_BISTFWR1) -#define DDR1_PUB_BISTFWR2 (0x3000 + (0x83 << 2)) -#define P_DDR1_PUB_BISTFWR2 MMC_REG_ADDR(DDR1_PUB_BISTFWR2) -#define DDR1_PUB_IOVCR0 (0x3000 + (0x8E << 2)) -#define P_DDR1_PUB_IOVCR0 MMC_REG_ADDR(DDR1_PUB_IOVCR0) -#define DDR1_PUB_IOVCR1 (0x3000 + (0x8F << 2)) -#define P_DDR1_PUB_IOVCR1 MMC_REG_ADDR(DDR1_PUB_IOVCR1) -#define DDR1_PUB_ZQCR (0x3000 + (0x90 << 2)) -#define P_DDR1_PUB_ZQCR MMC_REG_ADDR(DDR1_PUB_ZQCR) -#define DDR1_PUB_ZQ0PR (0x3000 + (0x91 << 2)) -#define P_DDR1_PUB_ZQ0PR MMC_REG_ADDR(DDR1_PUB_ZQ0PR) -#define DDR1_PUB_ZQ0DR (0x3000 + (0x92 << 2)) -#define P_DDR1_PUB_ZQ0DR MMC_REG_ADDR(DDR1_PUB_ZQ0DR) -#define DDR1_PUB_ZQ0SR (0x3000 + (0x93 << 2)) -#define P_DDR1_PUB_ZQ0SR MMC_REG_ADDR(DDR1_PUB_ZQ0SR) -#define DDR1_PUB_ZQ1PR (0x3000 + (0x95 << 2)) -#define P_DDR1_PUB_ZQ1PR MMC_REG_ADDR(DDR1_PUB_ZQ1PR) -#define DDR1_PUB_ZQ1DR (0x3000 + (0x96 << 2)) -#define P_DDR1_PUB_ZQ1DR MMC_REG_ADDR(DDR1_PUB_ZQ1DR) -#define DDR1_PUB_ZQ1SR (0x3000 + (0x97 << 2)) -#define P_DDR1_PUB_ZQ1SR MMC_REG_ADDR(DDR1_PUB_ZQ1SR) -#define DDR1_PUB_ZQ2PR (0x3000 + (0x99 << 2)) -#define P_DDR1_PUB_ZQ2PR MMC_REG_ADDR(DDR1_PUB_ZQ2PR) -#define DDR1_PUB_ZQ2DR (0x3000 + (0x9A << 2)) -#define P_DDR1_PUB_ZQ2DR MMC_REG_ADDR(DDR1_PUB_ZQ2DR) -#define DDR1_PUB_ZQ2SR (0x3000 + (0x9B << 2)) -#define P_DDR1_PUB_ZQ2SR MMC_REG_ADDR(DDR1_PUB_ZQ2SR) -#define DDR1_PUB_ZQ3PR (0x3000 + (0x9D << 2)) -#define P_DDR1_PUB_ZQ3PR MMC_REG_ADDR(DDR1_PUB_ZQ3PR) -#define DDR1_PUB_ZQ3DR (0x3000 + (0x9E << 2)) -#define P_DDR1_PUB_ZQ3DR MMC_REG_ADDR(DDR1_PUB_ZQ3DR) -#define DDR1_PUB_ZQ3SR (0x3000 + (0x9F << 2)) -#define P_DDR1_PUB_ZQ3SR MMC_REG_ADDR(DDR1_PUB_ZQ3SR) -#define DDR1_PUB_DX0GCR0 (0x3000 + (0xA0 << 2)) -#define P_DDR1_PUB_DX0GCR0 MMC_REG_ADDR(DDR1_PUB_DX0GCR0) -#define DDR1_PUB_DX0GCR1 (0x3000 + (0xA1 << 2)) -#define P_DDR1_PUB_DX0GCR1 MMC_REG_ADDR(DDR1_PUB_DX0GCR1) -#define DDR1_PUB_DX0GCR2 (0x3000 + (0xA2 << 2)) -#define P_DDR1_PUB_DX0GCR2 MMC_REG_ADDR(DDR1_PUB_DX0GCR2) -#define DDR1_PUB_DX0GCR3 (0x3000 + (0xA3 << 2)) -#define P_DDR1_PUB_DX0GCR3 MMC_REG_ADDR(DDR1_PUB_DX0GCR3) -#define DDR1_PUB_DX0GSR0 (0x3000 + (0xA4 << 2)) -#define P_DDR1_PUB_DX0GSR0 MMC_REG_ADDR(DDR1_PUB_DX0GSR0) -#define DDR1_PUB_DX0GSR1 (0x3000 + (0xA5 << 2)) -#define P_DDR1_PUB_DX0GSR1 MMC_REG_ADDR(DDR1_PUB_DX0GSR1) -#define DDR1_PUB_DX0GSR2 (0x3000 + (0xA6 << 2)) -#define P_DDR1_PUB_DX0GSR2 MMC_REG_ADDR(DDR1_PUB_DX0GSR2) -#define DDR1_PUB_DX0BDLR0 (0x3000 + (0xA7 << 2)) -#define P_DDR1_PUB_DX0BDLR0 MMC_REG_ADDR(DDR1_PUB_DX0BDLR0) -#define DDR1_PUB_DX0BDLR1 (0x3000 + (0xA8 << 2)) -#define P_DDR1_PUB_DX0BDLR1 MMC_REG_ADDR(DDR1_PUB_DX0BDLR1) -#define DDR1_PUB_DX0BDLR2 (0x3000 + (0xA9 << 2)) -#define P_DDR1_PUB_DX0BDLR2 MMC_REG_ADDR(DDR1_PUB_DX0BDLR2) -#define DDR1_PUB_DX0BDLR3 (0x3000 + (0xAA << 2)) -#define P_DDR1_PUB_DX0BDLR3 MMC_REG_ADDR(DDR1_PUB_DX0BDLR3) -#define DDR1_PUB_DX0BDLR4 (0x3000 + (0xAB << 2)) -#define P_DDR1_PUB_DX0BDLR4 MMC_REG_ADDR(DDR1_PUB_DX0BDLR4) -#define DDR1_PUB_DX0BDLR5 (0x3000 + (0xAC << 2)) -#define P_DDR1_PUB_DX0BDLR5 MMC_REG_ADDR(DDR1_PUB_DX0BDLR5) -#define DDR1_PUB_DX0BDLR6 (0x3000 + (0xAD << 2)) -#define P_DDR1_PUB_DX0BDLR6 MMC_REG_ADDR(DDR1_PUB_DX0BDLR6) -#define DDR1_PUB_DX0LCDLR0 (0x3000 + (0xAE << 2)) -#define P_DDR1_PUB_DX0LCDLR0 MMC_REG_ADDR(DDR1_PUB_DX0LCDLR0) -#define DDR1_PUB_DX0LCDLR1 (0x3000 + (0xAF << 2)) -#define P_DDR1_PUB_DX0LCDLR1 MMC_REG_ADDR(DDR1_PUB_DX0LCDLR1) -#define DDR1_PUB_DX0LCDLR2 (0x3000 + (0xB0 << 2)) -#define P_DDR1_PUB_DX0LCDLR2 MMC_REG_ADDR(DDR1_PUB_DX0LCDLR2) -#define DDR1_PUB_DX0MDLR (0x3000 + (0xB1 << 2)) -#define P_DDR1_PUB_DX0MDLR MMC_REG_ADDR(DDR1_PUB_DX0MDLR) -#define DDR1_PUB_DX0GTR (0x3000 + (0xB2 << 2)) -#define P_DDR1_PUB_DX0GTR MMC_REG_ADDR(DDR1_PUB_DX0GTR) -#define DDR1_PUB_DX1GCR0 (0x3000 + (0xC0 << 2)) -#define P_DDR1_PUB_DX1GCR0 MMC_REG_ADDR(DDR1_PUB_DX1GCR0) -#define DDR1_PUB_DX1GCR1 (0x3000 + (0xC1 << 2)) -#define P_DDR1_PUB_DX1GCR1 MMC_REG_ADDR(DDR1_PUB_DX1GCR1) -#define DDR1_PUB_DX1GCR2 (0x3000 + (0xC2 << 2)) -#define P_DDR1_PUB_DX1GCR2 MMC_REG_ADDR(DDR1_PUB_DX1GCR2) -#define DDR1_PUB_DX1GCR3 (0x3000 + (0xC3 << 2)) -#define P_DDR1_PUB_DX1GCR3 MMC_REG_ADDR(DDR1_PUB_DX1GCR3) -#define DDR1_PUB_DX1GSR0 (0x3000 + (0xC4 << 2)) -#define P_DDR1_PUB_DX1GSR0 MMC_REG_ADDR(DDR1_PUB_DX1GSR0) -#define DDR1_PUB_DX1GSR1 (0x3000 + (0xC5 << 2)) -#define P_DDR1_PUB_DX1GSR1 MMC_REG_ADDR(DDR1_PUB_DX1GSR1) -#define DDR1_PUB_DX1GSR2 (0x3000 + (0xC6 << 2)) -#define P_DDR1_PUB_DX1GSR2 MMC_REG_ADDR(DDR1_PUB_DX1GSR2) -#define DDR1_PUB_DX1BDLR0 (0x3000 + (0xC7 << 2)) -#define P_DDR1_PUB_DX1BDLR0 MMC_REG_ADDR(DDR1_PUB_DX1BDLR0) -#define DDR1_PUB_DX1BDLR1 (0x3000 + (0xC8 << 2)) -#define P_DDR1_PUB_DX1BDLR1 MMC_REG_ADDR(DDR1_PUB_DX1BDLR1) -#define DDR1_PUB_DX1BDLR2 (0x3000 + (0xC9 << 2)) -#define P_DDR1_PUB_DX1BDLR2 MMC_REG_ADDR(DDR1_PUB_DX1BDLR2) -#define DDR1_PUB_DX1BDLR3 (0x3000 + (0xCA << 2)) -#define P_DDR1_PUB_DX1BDLR3 MMC_REG_ADDR(DDR1_PUB_DX1BDLR3) -#define DDR1_PUB_DX1BDLR4 (0x3000 + (0xCB << 2)) -#define P_DDR1_PUB_DX1BDLR4 MMC_REG_ADDR(DDR1_PUB_DX1BDLR4) -#define DDR1_PUB_DX1BDLR5 (0x3000 + (0xCC << 2)) -#define P_DDR1_PUB_DX1BDLR5 MMC_REG_ADDR(DDR1_PUB_DX1BDLR5) -#define DDR1_PUB_DX1BDLR6 (0x3000 + (0xCD << 2)) -#define P_DDR1_PUB_DX1BDLR6 MMC_REG_ADDR(DDR1_PUB_DX1BDLR6) -#define DDR1_PUB_DX1LCDLR0 (0x3000 + (0xCE << 2)) -#define P_DDR1_PUB_DX1LCDLR0 MMC_REG_ADDR(DDR1_PUB_DX1LCDLR0) -#define DDR1_PUB_DX1LCDLR1 (0x3000 + (0xCF << 2)) -#define P_DDR1_PUB_DX1LCDLR1 MMC_REG_ADDR(DDR1_PUB_DX1LCDLR1) -#define DDR1_PUB_DX1LCDLR2 (0x3000 + (0xD0 << 2)) -#define P_DDR1_PUB_DX1LCDLR2 MMC_REG_ADDR(DDR1_PUB_DX1LCDLR2) -#define DDR1_PUB_DX1MDLR (0x3000 + (0xD1 << 2)) -#define P_DDR1_PUB_DX1MDLR MMC_REG_ADDR(DDR1_PUB_DX1MDLR) -#define DDR1_PUB_DX1GTR (0x3000 + (0xD2 << 2)) -#define P_DDR1_PUB_DX1GTR MMC_REG_ADDR(DDR1_PUB_DX1GTR) -#define DDR1_PUB_DX2GCR0 (0x3000 + (0xE0 << 2)) -#define P_DDR1_PUB_DX2GCR0 MMC_REG_ADDR(DDR1_PUB_DX2GCR0) -#define DDR1_PUB_DX2GCR1 (0x3000 + (0xE1 << 2)) -#define P_DDR1_PUB_DX2GCR1 MMC_REG_ADDR(DDR1_PUB_DX2GCR1) -#define DDR1_PUB_DX2GCR2 (0x3000 + (0xE2 << 2)) -#define P_DDR1_PUB_DX2GCR2 MMC_REG_ADDR(DDR1_PUB_DX2GCR2) -#define DDR1_PUB_DX2GCR3 (0x3000 + (0xE3 << 2)) -#define P_DDR1_PUB_DX2GCR3 MMC_REG_ADDR(DDR1_PUB_DX2GCR3) -#define DDR1_PUB_DX2GSR0 (0x3000 + (0xE4 << 2)) -#define P_DDR1_PUB_DX2GSR0 MMC_REG_ADDR(DDR1_PUB_DX2GSR0) -#define DDR1_PUB_DX2GSR1 (0x3000 + (0xE5 << 2)) -#define P_DDR1_PUB_DX2GSR1 MMC_REG_ADDR(DDR1_PUB_DX2GSR1) -#define DDR1_PUB_DX2GSR2 (0x3000 + (0xE6 << 2)) -#define P_DDR1_PUB_DX2GSR2 MMC_REG_ADDR(DDR1_PUB_DX2GSR2) -#define DDR1_PUB_DX2BDLR0 (0x3000 + (0xE7 << 2)) -#define P_DDR1_PUB_DX2BDLR0 MMC_REG_ADDR(DDR1_PUB_DX2BDLR0) -#define DDR1_PUB_DX2BDLR1 (0x3000 + (0xE8 << 2)) -#define P_DDR1_PUB_DX2BDLR1 MMC_REG_ADDR(DDR1_PUB_DX2BDLR1) -#define DDR1_PUB_DX2BDLR2 (0x3000 + (0xE9 << 2)) -#define P_DDR1_PUB_DX2BDLR2 MMC_REG_ADDR(DDR1_PUB_DX2BDLR2) -#define DDR1_PUB_DX2BDLR3 (0x3000 + (0xEA << 2)) -#define P_DDR1_PUB_DX2BDLR3 MMC_REG_ADDR(DDR1_PUB_DX2BDLR3) -#define DDR1_PUB_DX2BDLR4 (0x3000 + (0xEB << 2)) -#define P_DDR1_PUB_DX2BDLR4 MMC_REG_ADDR(DDR1_PUB_DX2BDLR4) -#define DDR1_PUB_DX2BDLR5 (0x3000 + (0xEC << 2)) -#define P_DDR1_PUB_DX2BDLR5 MMC_REG_ADDR(DDR1_PUB_DX2BDLR5) -#define DDR1_PUB_DX2BDLR6 (0x3000 + (0xED << 2)) -#define P_DDR1_PUB_DX2BDLR6 MMC_REG_ADDR(DDR1_PUB_DX2BDLR6) -#define DDR1_PUB_DX2LCDLR0 (0x3000 + (0xEE << 2)) -#define P_DDR1_PUB_DX2LCDLR0 MMC_REG_ADDR(DDR1_PUB_DX2LCDLR0) -#define DDR1_PUB_DX2LCDLR1 (0x3000 + (0xEF << 2)) -#define P_DDR1_PUB_DX2LCDLR1 MMC_REG_ADDR(DDR1_PUB_DX2LCDLR1) -#define DDR1_PUB_DX2LCDLR2 (0x3000 + (0xF0 << 2)) -#define P_DDR1_PUB_DX2LCDLR2 MMC_REG_ADDR(DDR1_PUB_DX2LCDLR2) -#define DDR1_PUB_DX2MDLR (0x3000 + (0xF1 << 2)) -#define P_DDR1_PUB_DX2MDLR MMC_REG_ADDR(DDR1_PUB_DX2MDLR) -#define DDR1_PUB_DX2GTR (0x3000 + (0xF2 << 2)) -#define P_DDR1_PUB_DX2GTR MMC_REG_ADDR(DDR1_PUB_DX2GTR) -#define DDR1_PUB_DX3GCR0 (0x3000 + (0x100 << 2)) -#define P_DDR1_PUB_DX3GCR0 MMC_REG_ADDR(DDR1_PUB_DX3GCR0) -#define DDR1_PUB_DX3GCR1 (0x3000 + (0x101 << 2)) -#define P_DDR1_PUB_DX3GCR1 MMC_REG_ADDR(DDR1_PUB_DX3GCR1) -#define DDR1_PUB_DX3GCR2 (0x3000 + (0x102 << 2)) -#define P_DDR1_PUB_DX3GCR2 MMC_REG_ADDR(DDR1_PUB_DX3GCR2) -#define DDR1_PUB_DX3GCR3 (0x3000 + (0x103 << 2)) -#define P_DDR1_PUB_DX3GCR3 MMC_REG_ADDR(DDR1_PUB_DX3GCR3) -#define DDR1_PUB_DX3GSR0 (0x3000 + (0x104 << 2)) -#define P_DDR1_PUB_DX3GSR0 MMC_REG_ADDR(DDR1_PUB_DX3GSR0) -#define DDR1_PUB_DX3GSR1 (0x3000 + (0x105 << 2)) -#define P_DDR1_PUB_DX3GSR1 MMC_REG_ADDR(DDR1_PUB_DX3GSR1) -#define DDR1_PUB_DX3GSR2 (0x3000 + (0x106 << 2)) -#define P_DDR1_PUB_DX3GSR2 MMC_REG_ADDR(DDR1_PUB_DX3GSR2) -#define DDR1_PUB_DX3BDLR0 (0x3000 + (0x107 << 2)) -#define P_DDR1_PUB_DX3BDLR0 MMC_REG_ADDR(DDR1_PUB_DX3BDLR0) -#define DDR1_PUB_DX3BDLR1 (0x3000 + (0x108 << 2)) -#define P_DDR1_PUB_DX3BDLR1 MMC_REG_ADDR(DDR1_PUB_DX3BDLR1) -#define DDR1_PUB_DX3BDLR2 (0x3000 + (0x109 << 2)) -#define P_DDR1_PUB_DX3BDLR2 MMC_REG_ADDR(DDR1_PUB_DX3BDLR2) -#define DDR1_PUB_DX3BDLR3 (0x3000 + (0x10A << 2)) -#define P_DDR1_PUB_DX3BDLR3 MMC_REG_ADDR(DDR1_PUB_DX3BDLR3) -#define DDR1_PUB_DX3BDLR4 (0x3000 + (0x10B << 2)) -#define P_DDR1_PUB_DX3BDLR4 MMC_REG_ADDR(DDR1_PUB_DX3BDLR4) -#define DDR1_PUB_DX3BDLR5 (0x3000 + (0x10C << 2)) -#define P_DDR1_PUB_DX3BDLR5 MMC_REG_ADDR(DDR1_PUB_DX3BDLR5) -#define DDR1_PUB_DX3BDLR6 (0x3000 + (0x10D << 2)) -#define P_DDR1_PUB_DX3BDLR6 MMC_REG_ADDR(DDR1_PUB_DX3BDLR6) -#define DDR1_PUB_DX3LCDLR0 (0x3000 + (0x10E << 2)) -#define P_DDR1_PUB_DX3LCDLR0 MMC_REG_ADDR(DDR1_PUB_DX3LCDLR0) -#define DDR1_PUB_DX3LCDLR1 (0x3000 + (0x10F << 2)) -#define P_DDR1_PUB_DX3LCDLR1 MMC_REG_ADDR(DDR1_PUB_DX3LCDLR1) -#define DDR1_PUB_DX3LCDLR2 (0x3000 + (0x110 << 2)) -#define P_DDR1_PUB_DX3LCDLR2 MMC_REG_ADDR(DDR1_PUB_DX3LCDLR2) -#define DDR1_PUB_DX3MDLR (0x3000 + (0x111 << 2)) -#define P_DDR1_PUB_DX3MDLR MMC_REG_ADDR(DDR1_PUB_DX3MDLR) -#define DDR1_PUB_DX3GTR (0x3000 + (0x112 << 2)) -#define P_DDR1_PUB_DX3GTR MMC_REG_ADDR(DDR1_PUB_DX3GTR) -#define DDR1_PUB_DX4GCR0 (0x3000 + (0x120 << 2)) -#define P_DDR1_PUB_DX4GCR0 MMC_REG_ADDR(DDR1_PUB_DX4GCR0) -#define DDR1_PUB_DX4GCR1 (0x3000 + (0x121 << 2)) -#define P_DDR1_PUB_DX4GCR1 MMC_REG_ADDR(DDR1_PUB_DX4GCR1) -#define DDR1_PUB_DX4GCR2 (0x3000 + (0x122 << 2)) -#define P_DDR1_PUB_DX4GCR2 MMC_REG_ADDR(DDR1_PUB_DX4GCR2) -#define DDR1_PUB_DX4GCR3 (0x3000 + (0x123 << 2)) -#define P_DDR1_PUB_DX4GCR3 MMC_REG_ADDR(DDR1_PUB_DX4GCR3) -#define DDR1_PUB_DX4GSR0 (0x3000 + (0x124 << 2)) -#define P_DDR1_PUB_DX4GSR0 MMC_REG_ADDR(DDR1_PUB_DX4GSR0) -#define DDR1_PUB_DX4GSR1 (0x3000 + (0x125 << 2)) -#define P_DDR1_PUB_DX4GSR1 MMC_REG_ADDR(DDR1_PUB_DX4GSR1) -#define DDR1_PUB_DX4GSR2 (0x3000 + (0x126 << 2)) -#define P_DDR1_PUB_DX4GSR2 MMC_REG_ADDR(DDR1_PUB_DX4GSR2) -#define DDR1_PUB_DX4BDLR0 (0x3000 + (0x127 << 2)) -#define P_DDR1_PUB_DX4BDLR0 MMC_REG_ADDR(DDR1_PUB_DX4BDLR0) -#define DDR1_PUB_DX4BDLR1 (0x3000 + (0x128 << 2)) -#define P_DDR1_PUB_DX4BDLR1 MMC_REG_ADDR(DDR1_PUB_DX4BDLR1) -#define DDR1_PUB_DX4BDLR2 (0x3000 + (0x129 << 2)) -#define P_DDR1_PUB_DX4BDLR2 MMC_REG_ADDR(DDR1_PUB_DX4BDLR2) -#define DDR1_PUB_DX4BDLR3 (0x3000 + (0x12A << 2)) -#define P_DDR1_PUB_DX4BDLR3 MMC_REG_ADDR(DDR1_PUB_DX4BDLR3) -#define DDR1_PUB_DX4BDLR4 (0x3000 + (0x12B << 2)) -#define P_DDR1_PUB_DX4BDLR4 MMC_REG_ADDR(DDR1_PUB_DX4BDLR4) -#define DDR1_PUB_DX4BDLR5 (0x3000 + (0x12C << 2)) -#define P_DDR1_PUB_DX4BDLR5 MMC_REG_ADDR(DDR1_PUB_DX4BDLR5) -#define DDR1_PUB_DX4BDLR6 (0x3000 + (0x12D << 2)) -#define P_DDR1_PUB_DX4BDLR6 MMC_REG_ADDR(DDR1_PUB_DX4BDLR6) -#define DDR1_PUB_DX4LCDLR0 (0x3000 + (0x12E << 2)) -#define P_DDR1_PUB_DX4LCDLR0 MMC_REG_ADDR(DDR1_PUB_DX4LCDLR0) -#define DDR1_PUB_DX4LCDLR1 (0x3000 + (0x12F << 2)) -#define P_DDR1_PUB_DX4LCDLR1 MMC_REG_ADDR(DDR1_PUB_DX4LCDLR1) -#define DDR1_PUB_DX4LCDLR2 (0x3000 + (0x130 << 2)) -#define P_DDR1_PUB_DX4LCDLR2 MMC_REG_ADDR(DDR1_PUB_DX4LCDLR2) -#define DDR1_PUB_DX4MDLR (0x3000 + (0x131 << 2)) -#define P_DDR1_PUB_DX4MDLR MMC_REG_ADDR(DDR1_PUB_DX4MDLR) -#define DDR1_PUB_DX4GTR (0x3000 + (0x132 << 2)) -#define P_DDR1_PUB_DX4GTR MMC_REG_ADDR(DDR1_PUB_DX4GTR) -#define DDR1_PUB_DX5GCR0 (0x3000 + (0x140 << 2)) -#define P_DDR1_PUB_DX5GCR0 MMC_REG_ADDR(DDR1_PUB_DX5GCR0) -#define DDR1_PUB_DX5GCR1 (0x3000 + (0x141 << 2)) -#define P_DDR1_PUB_DX5GCR1 MMC_REG_ADDR(DDR1_PUB_DX5GCR1) -#define DDR1_PUB_DX5GCR2 (0x3000 + (0x142 << 2)) -#define P_DDR1_PUB_DX5GCR2 MMC_REG_ADDR(DDR1_PUB_DX5GCR2) -#define DDR1_PUB_DX5GCR3 (0x3000 + (0x143 << 2)) -#define P_DDR1_PUB_DX5GCR3 MMC_REG_ADDR(DDR1_PUB_DX5GCR3) -#define DDR1_PUB_DX5GSR0 (0x3000 + (0x144 << 2)) -#define P_DDR1_PUB_DX5GSR0 MMC_REG_ADDR(DDR1_PUB_DX5GSR0) -#define DDR1_PUB_DX5GSR1 (0x3000 + (0x145 << 2)) -#define P_DDR1_PUB_DX5GSR1 MMC_REG_ADDR(DDR1_PUB_DX5GSR1) -#define DDR1_PUB_DX5GSR2 (0x3000 + (0x146 << 2)) -#define P_DDR1_PUB_DX5GSR2 MMC_REG_ADDR(DDR1_PUB_DX5GSR2) -#define DDR1_PUB_DX5BDLR0 (0x3000 + (0x147 << 2)) -#define P_DDR1_PUB_DX5BDLR0 MMC_REG_ADDR(DDR1_PUB_DX5BDLR0) -#define DDR1_PUB_DX5BDLR1 (0x3000 + (0x148 << 2)) -#define P_DDR1_PUB_DX5BDLR1 MMC_REG_ADDR(DDR1_PUB_DX5BDLR1) -#define DDR1_PUB_DX5BDLR2 (0x3000 + (0x149 << 2)) -#define P_DDR1_PUB_DX5BDLR2 MMC_REG_ADDR(DDR1_PUB_DX5BDLR2) -#define DDR1_PUB_DX5BDLR3 (0x3000 + (0x14A << 2)) -#define P_DDR1_PUB_DX5BDLR3 MMC_REG_ADDR(DDR1_PUB_DX5BDLR3) -#define DDR1_PUB_DX5BDLR4 (0x3000 + (0x14B << 2)) -#define P_DDR1_PUB_DX5BDLR4 MMC_REG_ADDR(DDR1_PUB_DX5BDLR4) -#define DDR1_PUB_DX5BDLR5 (0x3000 + (0x14C << 2)) -#define P_DDR1_PUB_DX5BDLR5 MMC_REG_ADDR(DDR1_PUB_DX5BDLR5) -#define DDR1_PUB_DX5BDLR6 (0x3000 + (0x14D << 2)) -#define P_DDR1_PUB_DX5BDLR6 MMC_REG_ADDR(DDR1_PUB_DX5BDLR6) -#define DDR1_PUB_DX5LCDLR0 (0x3000 + (0x14E << 2)) -#define P_DDR1_PUB_DX5LCDLR0 MMC_REG_ADDR(DDR1_PUB_DX5LCDLR0) -#define DDR1_PUB_DX5LCDLR1 (0x3000 + (0x14F << 2)) -#define P_DDR1_PUB_DX5LCDLR1 MMC_REG_ADDR(DDR1_PUB_DX5LCDLR1) -#define DDR1_PUB_DX5LCDLR2 (0x3000 + (0x150 << 2)) -#define P_DDR1_PUB_DX5LCDLR2 MMC_REG_ADDR(DDR1_PUB_DX5LCDLR2) -#define DDR1_PUB_DX5MDLR (0x3000 + (0x151 << 2)) -#define P_DDR1_PUB_DX5MDLR MMC_REG_ADDR(DDR1_PUB_DX5MDLR) -#define DDR1_PUB_DX5GTR (0x3000 + (0x152 << 2)) -#define P_DDR1_PUB_DX5GTR MMC_REG_ADDR(DDR1_PUB_DX5GTR) -#define DDR1_PUB_DX6GCR0 (0x3000 + (0x160 << 2)) -#define P_DDR1_PUB_DX6GCR0 MMC_REG_ADDR(DDR1_PUB_DX6GCR0) -#define DDR1_PUB_DX6GCR1 (0x3000 + (0x161 << 2)) -#define P_DDR1_PUB_DX6GCR1 MMC_REG_ADDR(DDR1_PUB_DX6GCR1) -#define DDR1_PUB_DX6GCR2 (0x3000 + (0x162 << 2)) -#define P_DDR1_PUB_DX6GCR2 MMC_REG_ADDR(DDR1_PUB_DX6GCR2) -#define DDR1_PUB_DX6GCR3 (0x3000 + (0x163 << 2)) -#define P_DDR1_PUB_DX6GCR3 MMC_REG_ADDR(DDR1_PUB_DX6GCR3) -#define DDR1_PUB_DX6GSR0 (0x3000 + (0x164 << 2)) -#define P_DDR1_PUB_DX6GSR0 MMC_REG_ADDR(DDR1_PUB_DX6GSR0) -#define DDR1_PUB_DX6GSR1 (0x3000 + (0x165 << 2)) -#define P_DDR1_PUB_DX6GSR1 MMC_REG_ADDR(DDR1_PUB_DX6GSR1) -#define DDR1_PUB_DX6GSR2 (0x3000 + (0x166 << 2)) -#define P_DDR1_PUB_DX6GSR2 MMC_REG_ADDR(DDR1_PUB_DX6GSR2) -#define DDR1_PUB_DX6BDLR0 (0x3000 + (0x167 << 2)) -#define P_DDR1_PUB_DX6BDLR0 MMC_REG_ADDR(DDR1_PUB_DX6BDLR0) -#define DDR1_PUB_DX6BDLR1 (0x3000 + (0x168 << 2)) -#define P_DDR1_PUB_DX6BDLR1 MMC_REG_ADDR(DDR1_PUB_DX6BDLR1) -#define DDR1_PUB_DX6BDLR2 (0x3000 + (0x169 << 2)) -#define P_DDR1_PUB_DX6BDLR2 MMC_REG_ADDR(DDR1_PUB_DX6BDLR2) -#define DDR1_PUB_DX6BDLR3 (0x3000 + (0x16A << 2)) -#define P_DDR1_PUB_DX6BDLR3 MMC_REG_ADDR(DDR1_PUB_DX6BDLR3) -#define DDR1_PUB_DX6BDLR4 (0x3000 + (0x16B << 2)) -#define P_DDR1_PUB_DX6BDLR4 MMC_REG_ADDR(DDR1_PUB_DX6BDLR4) -#define DDR1_PUB_DX6BDLR5 (0x3000 + (0x16C << 2)) -#define P_DDR1_PUB_DX6BDLR5 MMC_REG_ADDR(DDR1_PUB_DX6BDLR5) -#define DDR1_PUB_DX6BDLR6 (0x3000 + (0x16D << 2)) -#define P_DDR1_PUB_DX6BDLR6 MMC_REG_ADDR(DDR1_PUB_DX6BDLR6) -#define DDR1_PUB_DX6LCDLR0 (0x3000 + (0x16E << 2)) -#define P_DDR1_PUB_DX6LCDLR0 MMC_REG_ADDR(DDR1_PUB_DX6LCDLR0) -#define DDR1_PUB_DX6LCDLR1 (0x3000 + (0x16F << 2)) -#define P_DDR1_PUB_DX6LCDLR1 MMC_REG_ADDR(DDR1_PUB_DX6LCDLR1) -#define DDR1_PUB_DX6LCDLR2 (0x3000 + (0x170 << 2)) -#define P_DDR1_PUB_DX6LCDLR2 MMC_REG_ADDR(DDR1_PUB_DX6LCDLR2) -#define DDR1_PUB_DX6MDLR (0x3000 + (0x171 << 2)) -#define P_DDR1_PUB_DX6MDLR MMC_REG_ADDR(DDR1_PUB_DX6MDLR) -#define DDR1_PUB_DX6GTR (0x3000 + (0x172 << 2)) -#define P_DDR1_PUB_DX6GTR MMC_REG_ADDR(DDR1_PUB_DX6GTR) -#define DDR1_PUB_DX7GCR0 (0x3000 + (0x180 << 2)) -#define P_DDR1_PUB_DX7GCR0 MMC_REG_ADDR(DDR1_PUB_DX7GCR0) -#define DDR1_PUB_DX7GCR1 (0x3000 + (0x181 << 2)) -#define P_DDR1_PUB_DX7GCR1 MMC_REG_ADDR(DDR1_PUB_DX7GCR1) -#define DDR1_PUB_DX7GCR2 (0x3000 + (0x182 << 2)) -#define P_DDR1_PUB_DX7GCR2 MMC_REG_ADDR(DDR1_PUB_DX7GCR2) -#define DDR1_PUB_DX7GCR3 (0x3000 + (0x183 << 2)) -#define P_DDR1_PUB_DX7GCR3 MMC_REG_ADDR(DDR1_PUB_DX7GCR3) -#define DDR1_PUB_DX7GSR0 (0x3000 + (0x184 << 2)) -#define P_DDR1_PUB_DX7GSR0 MMC_REG_ADDR(DDR1_PUB_DX7GSR0) -#define DDR1_PUB_DX7GSR1 (0x3000 + (0x185 << 2)) -#define P_DDR1_PUB_DX7GSR1 MMC_REG_ADDR(DDR1_PUB_DX7GSR1) -#define DDR1_PUB_DX7GSR2 (0x3000 + (0x186 << 2)) -#define P_DDR1_PUB_DX7GSR2 MMC_REG_ADDR(DDR1_PUB_DX7GSR2) -#define DDR1_PUB_DX7BDLR0 (0x3000 + (0x187 << 2)) -#define P_DDR1_PUB_DX7BDLR0 MMC_REG_ADDR(DDR1_PUB_DX7BDLR0) -#define DDR1_PUB_DX7BDLR1 (0x3000 + (0x188 << 2)) -#define P_DDR1_PUB_DX7BDLR1 MMC_REG_ADDR(DDR1_PUB_DX7BDLR1) -#define DDR1_PUB_DX7BDLR2 (0x3000 + (0x189 << 2)) -#define P_DDR1_PUB_DX7BDLR2 MMC_REG_ADDR(DDR1_PUB_DX7BDLR2) -#define DDR1_PUB_DX7BDLR3 (0x3000 + (0x18A << 2)) -#define P_DDR1_PUB_DX7BDLR3 MMC_REG_ADDR(DDR1_PUB_DX7BDLR3) -#define DDR1_PUB_DX7BDLR4 (0x3000 + (0x18B << 2)) -#define P_DDR1_PUB_DX7BDLR4 MMC_REG_ADDR(DDR1_PUB_DX7BDLR4) -#define DDR1_PUB_DX7BDLR5 (0x3000 + (0x18C << 2)) -#define P_DDR1_PUB_DX7BDLR5 MMC_REG_ADDR(DDR1_PUB_DX7BDLR5) -#define DDR1_PUB_DX7BDLR6 (0x3000 + (0x18D << 2)) -#define P_DDR1_PUB_DX7BDLR6 MMC_REG_ADDR(DDR1_PUB_DX7BDLR6) -#define DDR1_PUB_DX7LCDLR0 (0x3000 + (0x18E << 2)) -#define P_DDR1_PUB_DX7LCDLR0 MMC_REG_ADDR(DDR1_PUB_DX7LCDLR0) -#define DDR1_PUB_DX7LCDLR1 (0x3000 + (0x18F << 2)) -#define P_DDR1_PUB_DX7LCDLR1 MMC_REG_ADDR(DDR1_PUB_DX7LCDLR1) -#define DDR1_PUB_DX7LCDLR2 (0x3000 + (0x190 << 2)) -#define P_DDR1_PUB_DX7LCDLR2 MMC_REG_ADDR(DDR1_PUB_DX7LCDLR2) -#define DDR1_PUB_DX7MDLR (0x3000 + (0x191 << 2)) -#define P_DDR1_PUB_DX7MDLR MMC_REG_ADDR(DDR1_PUB_DX7MDLR) -#define DDR1_PUB_DX7GTR (0x3000 + (0x192 << 2)) -#define P_DDR1_PUB_DX7GTR MMC_REG_ADDR(DDR1_PUB_DX7GTR) -#define DDR1_PUB_DX8GCR0 (0x3000 + (0x1A0 << 2)) -#define P_DDR1_PUB_DX8GCR0 MMC_REG_ADDR(DDR1_PUB_DX8GCR0) -#define DDR1_PUB_DX8GCR1 (0x3000 + (0x1A1 << 2)) -#define P_DDR1_PUB_DX8GCR1 MMC_REG_ADDR(DDR1_PUB_DX8GCR1) -#define DDR1_PUB_DX8GCR2 (0x3000 + (0x1A2 << 2)) -#define P_DDR1_PUB_DX8GCR2 MMC_REG_ADDR(DDR1_PUB_DX8GCR2) -#define DDR1_PUB_DX8GCR3 (0x3000 + (0x1A3 << 2)) -#define P_DDR1_PUB_DX8GCR3 MMC_REG_ADDR(DDR1_PUB_DX8GCR3) -#define DDR1_PUB_DX8GSR0 (0x3000 + (0x1A4 << 2)) -#define P_DDR1_PUB_DX8GSR0 MMC_REG_ADDR(DDR1_PUB_DX8GSR0) -#define DDR1_PUB_DX8GSR1 (0x3000 + (0x1A5 << 2)) -#define P_DDR1_PUB_DX8GSR1 MMC_REG_ADDR(DDR1_PUB_DX8GSR1) -#define DDR1_PUB_DX8GSR2 (0x3000 + (0x1A6 << 2)) -#define P_DDR1_PUB_DX8GSR2 MMC_REG_ADDR(DDR1_PUB_DX8GSR2) -#define DDR1_PUB_DX8BDLR0 (0x3000 + (0x1A7 << 2)) -#define P_DDR1_PUB_DX8BDLR0 MMC_REG_ADDR(DDR1_PUB_DX8BDLR0) -#define DDR1_PUB_DX8BDLR1 (0x3000 + (0x1A8 << 2)) -#define P_DDR1_PUB_DX8BDLR1 MMC_REG_ADDR(DDR1_PUB_DX8BDLR1) -#define DDR1_PUB_DX8BDLR2 (0x3000 + (0x1A9 << 2)) -#define P_DDR1_PUB_DX8BDLR2 MMC_REG_ADDR(DDR1_PUB_DX8BDLR2) -#define DDR1_PUB_DX8BDLR3 (0x3000 + (0x1AA << 2)) -#define P_DDR1_PUB_DX8BDLR3 MMC_REG_ADDR(DDR1_PUB_DX8BDLR3) -#define DDR1_PUB_DX8BDLR4 (0x3000 + (0x1AB << 2)) -#define P_DDR1_PUB_DX8BDLR4 MMC_REG_ADDR(DDR1_PUB_DX8BDLR4) -#define DDR1_PUB_DX8BDLR5 (0x3000 + (0x1AC << 2)) -#define P_DDR1_PUB_DX8BDLR5 MMC_REG_ADDR(DDR1_PUB_DX8BDLR5) -#define DDR1_PUB_DX8BDLR6 (0x3000 + (0x1AD << 2)) -#define P_DDR1_PUB_DX8BDLR6 MMC_REG_ADDR(DDR1_PUB_DX8BDLR6) -#define DDR1_PUB_DX8LCDLR0 (0x3000 + (0x1AE << 2)) -#define P_DDR1_PUB_DX8LCDLR0 MMC_REG_ADDR(DDR1_PUB_DX8LCDLR0) -#define DDR1_PUB_DX8LCDLR1 (0x3000 + (0x1AF << 2)) -#define P_DDR1_PUB_DX8LCDLR1 MMC_REG_ADDR(DDR1_PUB_DX8LCDLR1) -#define DDR1_PUB_DX8LCDLR2 (0x3000 + (0x1B0 << 2)) -#define P_DDR1_PUB_DX8LCDLR2 MMC_REG_ADDR(DDR1_PUB_DX8LCDLR2) -#define DDR1_PUB_DX8MDLR (0x3000 + (0x1B1 << 2)) -#define P_DDR1_PUB_DX8MDLR MMC_REG_ADDR(DDR1_PUB_DX8MDLR) -#define DDR1_PUB_DX8GTR (0x3000 + (0x1B2 << 2)) -#define P_DDR1_PUB_DX8GTR MMC_REG_ADDR(DDR1_PUB_DX8GTR) -/*add from M8m2*/ -#define S_DMC_REG_BASE 0x6000 -#define DMC_REQ_CTRL (S_DMC_REG_BASE + (0x00 << 2)) -#define P_DMC_REQ_CTRL MMC_REG_ADDR(DMC_REQ_CTRL) -#define DMC_SOFT_RST (S_DMC_REG_BASE + (0x01 << 2)) -#define P_DMC_SOFT_RST MMC_REG_ADDR(DMC_SOFT_RST) -#define DMC_SOFT_RST1 (S_DMC_REG_BASE + (0x02 << 2)) -#define P_DMC_SOFT_RST1 MMC_REG_ADDR(DMC_SOFT_RST1) -#define DMC_RST_STS (S_DMC_REG_BASE + (0x03 << 2)) -#define P_DMC_RST_STS MMC_REG_ADDR(DMC_RST_STS) -#define DMC_RST_STS1 (S_DMC_REG_BASE + (0x04 << 2)) -#define P_DMC_RST_STS1 MMC_REG_ADDR(DMC_RST_STS1) -#define DMC_VERSION (S_DMC_REG_BASE + (0x05 << 2)) -#define P_DMC_VERSION MMC_REG_ADDR(DMC_VERSION) -#define DMC_DDR_CTRL (S_DMC_REG_BASE + (0x10 << 2)) -#define P_DMC_DDR_CTRL MMC_REG_ADDR(DMC_DDR_CTRL) -#define DMC_DDR_CTRL1 (S_DMC_REG_BASE + (0x11 << 2)) -#define P_DMC_DDR_CTRL1 MMC_REG_ADDR(DMC_DDR_CTRL1) -#define DC_CAV_LUT_DATAL_M8M2 (S_DMC_REG_BASE + (0x12 << 2)) -#define P_DC_CAV_LUT_DATAL_M8M2 MMC_REG_ADDR(DC_CAV_LUT_DATAL_M8M2) -#define DC_CAV_LUT_DATAH_M8M2 (S_DMC_REG_BASE + (0x13 << 2)) -#define P_DC_CAV_LUT_DATAH_M8M2 MMC_REG_ADDR(DC_CAV_LUT_DATAH_M8M2) -#define DC_CAV_LUT_ADDR_M8M2 (S_DMC_REG_BASE + (0x14 << 2)) -#define P_DC_CAV_LUT_ADDR_M8M2 MMC_REG_ADDR(DC_CAV_LUT_ADDR_M8M2) -#define DC_CAV_LUT_RDATAL_M8M2 (S_DMC_REG_BASE + (0x15 << 2)) -#define P_DC_CAV_LUT_RDATAL_M8M2 MMC_REG_ADDR(DC_CAV_LUT_RDATAL_M8M2) -#define DC_CAV_LUT_RDATAH_M8M2 (S_DMC_REG_BASE + (0x16 << 2)) -#define P_DC_CAV_LUT_RDATAH_M8M2 MMC_REG_ADDR(DC_CAV_LUT_RDATAH_M8M2) -#define DMC_2ARB_CTRL (S_DMC_REG_BASE + (0x20 << 2)) -#define P_DMC_2ARB_CTRL MMC_REG_ADDR(DMC_2ARB_CTRL) -#define DMC_REFR_CTRL1 (S_DMC_REG_BASE + (0x23 << 2)) -#define P_DMC_REFR_CTRL1 MMC_REG_ADDR(DMC_REFR_CTRL1) -#define DMC_REFR_CTRL2 (S_DMC_REG_BASE + (0x24 << 2)) -#define P_DMC_REFR_CTRL2 MMC_REG_ADDR(DMC_REFR_CTRL2) -#define DMC_PARB_CTRL (S_DMC_REG_BASE + (0x25 << 2)) -#define P_DMC_PARB_CTRL MMC_REG_ADDR(DMC_PARB_CTRL) -#define DMC_MON_CTRL2 (S_DMC_REG_BASE + (0x26 << 2)) -#define P_DMC_MON_CTRL2 MMC_REG_ADDR(DMC_MON_CTRL2) -#define DMC_MON_CTRL3 (S_DMC_REG_BASE + (0x27 << 2)) -#define P_DMC_MON_CTRL3 MMC_REG_ADDR(DMC_MON_CTRL3) -#define DMC_MON_ALL_REQ_CNT (S_DMC_REG_BASE + (0x28 << 2)) -#define P_DMC_MON_ALL_REQ_CNT MMC_REG_ADDR(DMC_MON_ALL_REQ_CNT) -#define DMC_MON_ALL_GRANT_CNT (S_DMC_REG_BASE + (0x29 << 2)) -#define P_DMC_MON_ALL_GRANT_CNT \ - MMC_REG_ADDR(DMC_MON_ALL_GRANT_CNT) -#define DMC_MON_ONE_GRANT_CNT (S_DMC_REG_BASE + (0x2a << 2)) -#define P_DMC_MON_ONE_GRANT_CNT \ - MMC_REG_ADDR(DMC_MON_ONE_GRANT_CNT) -#define DMC_CLKG_CTRL0 (S_DMC_REG_BASE + (0x30 << 2)) -#define P_DMC_CLKG_CTRL0 MMC_REG_ADDR(DMC_CLKG_CTRL0) -#define DMC_CLKG_CTRL1 (S_DMC_REG_BASE + (0x31 << 2)) -#define P_DMC_CLKG_CTRL1 MMC_REG_ADDR(DMC_CLKG_CTRL1) -#define DMC_CHAN_STS (S_DMC_REG_BASE + (0x32 << 2)) -#define P_DMC_CHAN_STS MMC_REG_ADDR(DMC_CHAN_STS) -#define DMC_CMD_FILTER_CTRL1 (S_DMC_REG_BASE + (0x40 << 2)) -#define P_DMC_CMD_FILTER_CTRL1 MMC_REG_ADDR(DMC_CMD_FILTER_CTRL1) -#define DMC_CMD_FILTER_CTRL2 (S_DMC_REG_BASE + (0x41 << 2)) -#define P_DMC_CMD_FILTER_CTRL2 MMC_REG_ADDR(DMC_CMD_FILTER_CTRL2) -#define DMC_CMD_FILTER_CTRL3 (S_DMC_REG_BASE + (0x42 << 2)) -#define P_DMC_CMD_FILTER_CTRL3 MMC_REG_ADDR(DMC_CMD_FILTER_CTRL3) -#define DMC_CMD_FILTER_CTRL4 (S_DMC_REG_BASE + (0x43 << 2)) -#define P_DMC_CMD_FILTER_CTRL4 MMC_REG_ADDR(DMC_CMD_FILTER_CTRL4) -#define DMC_CMD_BUFFER_CTRL (S_DMC_REG_BASE + (0x44 << 2)) -#define P_DMC_CMD_BUFFER_CTRL MMC_REG_ADDR(DMC_CMD_BUFFER_CTRL) -#define DMC_AM0_CHAN_CTRL (S_DMC_REG_BASE + (0x60 << 2)) -#define P_DMC_AM0_CHAN_CTRL MMC_REG_ADDR(DMC_AM0_CHAN_CTRL) -#define DMC_AM0_HOLD_CTRL (S_DMC_REG_BASE + (0x61 << 2)) -#define P_DMC_AM0_HOLD_CTRL MMC_REG_ADDR(DMC_AM0_HOLD_CTRL) -#define DMC_AM0_QOS_INC (S_DMC_REG_BASE + (0x62 << 2)) -#define P_DMC_AM0_QOS_INC MMC_REG_ADDR(DMC_AM0_QOS_INC) -#define DMC_AM0_QOS_INCBK (S_DMC_REG_BASE + (0x63 << 2)) -#define P_DMC_AM0_QOS_INCBK MMC_REG_ADDR(DMC_AM0_QOS_INCBK) -#define DMC_AM0_QOS_DEC (S_DMC_REG_BASE + (0x64 << 2)) -#define P_DMC_AM0_QOS_DEC MMC_REG_ADDR(DMC_AM0_QOS_DEC) -#define DMC_AM0_QOS_DECBK (S_DMC_REG_BASE + (0x65 << 2)) -#define P_DMC_AM0_QOS_DECBK MMC_REG_ADDR(DMC_AM0_QOS_DECBK) -#define DMC_AM0_QOS_DIS (S_DMC_REG_BASE + (0x66 << 2)) -#define P_DMC_AM0_QOS_DIS MMC_REG_ADDR(DMC_AM0_QOS_DIS) -#define DMC_AM0_QOS_DISBK (S_DMC_REG_BASE + (0x67 << 2)) -#define P_DMC_AM0_QOS_DISBK MMC_REG_ADDR(DMC_AM0_QOS_DISBK) -#define DMC_AM0_QOS_CTRL0 (S_DMC_REG_BASE + (0x68 << 2)) -#define P_DMC_AM0_QOS_CTRL0 MMC_REG_ADDR(DMC_AM0_QOS_CTRL0) -#define DMC_AM0_QOS_CTRL1 (S_DMC_REG_BASE + (0x69 << 2)) -#define P_DMC_AM0_QOS_CTRL1 MMC_REG_ADDR(DMC_AM0_QOS_CTRL1) -#define DMC_AM1_CHAN_CTRL (S_DMC_REG_BASE + (0x6a << 2)) -#define P_DMC_AM1_CHAN_CTRL MMC_REG_ADDR(DMC_AM1_CHAN_CTRL) -#define DMC_AM1_HOLD_CTRL (S_DMC_REG_BASE + (0x6b << 2)) -#define P_DMC_AM1_HOLD_CTRL MMC_REG_ADDR(DMC_AM1_HOLD_CTRL) -#define DMC_AM1_QOS_INC (S_DMC_REG_BASE + (0x6c << 2)) -#define P_DMC_AM1_QOS_INC MMC_REG_ADDR(DMC_AM1_QOS_INC) -#define DMC_AM1_QOS_INCBK (S_DMC_REG_BASE + (0x6d << 2)) -#define P_DMC_AM1_QOS_INCBK MMC_REG_ADDR(DMC_AM1_QOS_INCBK) -#define DMC_AM1_QOS_DEC (S_DMC_REG_BASE + (0x6e << 2)) -#define P_DMC_AM1_QOS_DEC MMC_REG_ADDR(DMC_AM1_QOS_DEC) -#define DMC_AM1_QOS_DECBK (S_DMC_REG_BASE + (0x6f << 2)) -#define P_DMC_AM1_QOS_DECBK MMC_REG_ADDR(DMC_AM1_QOS_DECBK) -#define DMC_AM1_QOS_DIS (S_DMC_REG_BASE + (0x70 << 2)) -#define P_DMC_AM1_QOS_DIS MMC_REG_ADDR(DMC_AM1_QOS_DIS) -#define DMC_AM1_QOS_DISBK (S_DMC_REG_BASE + (0x71 << 2)) -#define P_DMC_AM1_QOS_DISBK MMC_REG_ADDR(DMC_AM1_QOS_DISBK) -#define DMC_AM1_QOS_CTRL0 (S_DMC_REG_BASE + (0x72 << 2)) -#define P_DMC_AM1_QOS_CTRL0 MMC_REG_ADDR(DMC_AM1_QOS_CTRL0) -#define DMC_AM1_QOS_CTRL1 (S_DMC_REG_BASE + (0x73 << 2)) -#define P_DMC_AM1_QOS_CTRL1 MMC_REG_ADDR(DMC_AM1_QOS_CTRL1) -#define DMC_AM2_CHAN_CTRL (S_DMC_REG_BASE + (0x74 << 2)) -#define P_DMC_AM2_CHAN_CTRL MMC_REG_ADDR(DMC_AM2_CHAN_CTRL) -#define DMC_AM2_HOLD_CTRL (S_DMC_REG_BASE + (0x75 << 2)) -#define P_DMC_AM2_HOLD_CTRL MMC_REG_ADDR(DMC_AM2_HOLD_CTRL) -#define DMC_AM2_QOS_INC (S_DMC_REG_BASE + (0x76 << 2)) -#define P_DMC_AM2_QOS_INC MMC_REG_ADDR(DMC_AM2_QOS_INC) -#define DMC_AM2_QOS_INCBK (S_DMC_REG_BASE + (0x77 << 2)) -#define P_DMC_AM2_QOS_INCBK MMC_REG_ADDR(DMC_AM2_QOS_INCBK) -#define DMC_AM2_QOS_DEC (S_DMC_REG_BASE + (0x78 << 2)) -#define P_DMC_AM2_QOS_DEC MMC_REG_ADDR(DMC_AM2_QOS_DEC) -#define DMC_AM2_QOS_DECBK (S_DMC_REG_BASE + (0x79 << 2)) -#define P_DMC_AM2_QOS_DECBK MMC_REG_ADDR(DMC_AM2_QOS_DECBK) -#define DMC_AM2_QOS_DIS (S_DMC_REG_BASE + (0x7a << 2)) -#define P_DMC_AM2_QOS_DIS MMC_REG_ADDR(DMC_AM2_QOS_DIS) -#define DMC_AM2_QOS_DISBK (S_DMC_REG_BASE + (0x7b << 2)) -#define P_DMC_AM2_QOS_DISBK MMC_REG_ADDR(DMC_AM2_QOS_DISBK) -#define DMC_AM2_QOS_CTRL0 (S_DMC_REG_BASE + (0x7c << 2)) -#define P_DMC_AM2_QOS_CTRL0 MMC_REG_ADDR(DMC_AM2_QOS_CTRL0) -#define DMC_AM2_QOS_CTRL1 (S_DMC_REG_BASE + (0x7d << 2)) -#define P_DMC_AM2_QOS_CTRL1 MMC_REG_ADDR(DMC_AM2_QOS_CTRL1) -#define DMC_AM3_CHAN_CTRL (S_DMC_REG_BASE + (0x7e << 2)) -#define P_DMC_AM3_CHAN_CTRL MMC_REG_ADDR(DMC_AM3_CHAN_CTRL) -#define DMC_AM3_HOLD_CTRL (S_DMC_REG_BASE + (0x7f << 2)) -#define P_DMC_AM3_HOLD_CTRL MMC_REG_ADDR(DMC_AM3_HOLD_CTRL) -#define DMC_AM3_QOS_INC (S_DMC_REG_BASE + (0x80 << 2)) -#define P_DMC_AM3_QOS_INC MMC_REG_ADDR(DMC_AM3_QOS_INC) -#define DMC_AM3_QOS_INCBK (S_DMC_REG_BASE + (0x81 << 2)) -#define P_DMC_AM3_QOS_INCBK MMC_REG_ADDR(DMC_AM3_QOS_INCBK) -#define DMC_AM3_QOS_DEC (S_DMC_REG_BASE + (0x82 << 2)) -#define P_DMC_AM3_QOS_DEC MMC_REG_ADDR(DMC_AM3_QOS_DEC) -#define DMC_AM3_QOS_DECBK (S_DMC_REG_BASE + (0x83 << 2)) -#define P_DMC_AM3_QOS_DECBK MMC_REG_ADDR(DMC_AM3_QOS_DECBK) -#define DMC_AM3_QOS_DIS (S_DMC_REG_BASE + (0x84 << 2)) -#define P_DMC_AM3_QOS_DIS MMC_REG_ADDR(DMC_AM3_QOS_DIS) -#define DMC_AM3_QOS_DISBK (S_DMC_REG_BASE + (0x85 << 2)) -#define P_DMC_AM3_QOS_DISBK MMC_REG_ADDR(DMC_AM3_QOS_DISBK) -#define DMC_AM3_QOS_CTRL0 (S_DMC_REG_BASE + (0x86 << 2)) -#define P_DMC_AM3_QOS_CTRL0 MMC_REG_ADDR(DMC_AM3_QOS_CTRL0) -#define DMC_AM3_QOS_CTRL1 (S_DMC_REG_BASE + (0x87 << 2)) -#define P_DMC_AM3_QOS_CTRL1 MMC_REG_ADDR(DMC_AM3_QOS_CTRL1) -#define DMC_AM4_CHAN_CTRL (S_DMC_REG_BASE + (0x88 << 2)) -#define P_DMC_AM4_CHAN_CTRL MMC_REG_ADDR(DMC_AM4_CHAN_CTRL) -#define DMC_AM4_HOLD_CTRL (S_DMC_REG_BASE + (0x89 << 2)) -#define P_DMC_AM4_HOLD_CTRL MMC_REG_ADDR(DMC_AM4_HOLD_CTRL) -#define DMC_AM4_QOS_INC (S_DMC_REG_BASE + (0x8a << 2)) -#define P_DMC_AM4_QOS_INC MMC_REG_ADDR(DMC_AM4_QOS_INC) -#define DMC_AM4_QOS_INCBK (S_DMC_REG_BASE + (0x8b << 2)) -#define P_DMC_AM4_QOS_INCBK MMC_REG_ADDR(DMC_AM4_QOS_INCBK) -#define DMC_AM4_QOS_DEC (S_DMC_REG_BASE + (0x8c << 2)) -#define P_DMC_AM4_QOS_DEC MMC_REG_ADDR(DMC_AM4_QOS_DEC) -#define DMC_AM4_QOS_DECBK (S_DMC_REG_BASE + (0x8d << 2)) -#define P_DMC_AM4_QOS_DECBK MMC_REG_ADDR(DMC_AM4_QOS_DECBK) -#define DMC_AM4_QOS_DIS (S_DMC_REG_BASE + (0x8e << 2)) -#define P_DMC_AM4_QOS_DIS MMC_REG_ADDR(DMC_AM4_QOS_DIS) -#define DMC_AM4_QOS_DISBK (S_DMC_REG_BASE + (0x8f << 2)) -#define P_DMC_AM4_QOS_DISBK MMC_REG_ADDR(DMC_AM4_QOS_DISBK) -#define DMC_AM4_QOS_CTRL0 (S_DMC_REG_BASE + (0x90 << 2)) -#define P_DMC_AM4_QOS_CTRL0 MMC_REG_ADDR(DMC_AM4_QOS_CTRL0) -#define DMC_AM4_QOS_CTRL1 (S_DMC_REG_BASE + (0x91 << 2)) -#define P_DMC_AM4_QOS_CTRL1 MMC_REG_ADDR(DMC_AM4_QOS_CTRL1) -#define DMC_AM5_CHAN_CTRL (S_DMC_REG_BASE + (0x92 << 2)) -#define P_DMC_AM5_CHAN_CTRL MMC_REG_ADDR(DMC_AM5_CHAN_CTRL) -#define DMC_AM5_HOLD_CTRL (S_DMC_REG_BASE + (0x93 << 2)) -#define P_DMC_AM5_HOLD_CTRL MMC_REG_ADDR(DMC_AM5_HOLD_CTRL) -#define DMC_AM5_QOS_INC (S_DMC_REG_BASE + (0x94 << 2)) -#define P_DMC_AM5_QOS_INC MMC_REG_ADDR(DMC_AM5_QOS_INC) -#define DMC_AM5_QOS_INCBK (S_DMC_REG_BASE + (0x95 << 2)) -#define P_DMC_AM5_QOS_INCBK MMC_REG_ADDR(DMC_AM5_QOS_INCBK) -#define DMC_AM5_QOS_DEC (S_DMC_REG_BASE + (0x96 << 2)) -#define P_DMC_AM5_QOS_DEC MMC_REG_ADDR(DMC_AM5_QOS_DEC) -#define DMC_AM5_QOS_DECBK (S_DMC_REG_BASE + (0x97 << 2)) -#define P_DMC_AM5_QOS_DECBK MMC_REG_ADDR(DMC_AM5_QOS_DECBK) -#define DMC_AM5_QOS_DIS (S_DMC_REG_BASE + (0x98 << 2)) -#define P_DMC_AM5_QOS_DIS MMC_REG_ADDR(DMC_AM5_QOS_DIS) -#define DMC_AM5_QOS_DISBK (S_DMC_REG_BASE + (0x99 << 2)) -#define P_DMC_AM5_QOS_DISBK MMC_REG_ADDR(DMC_AM5_QOS_DISBK) -#define DMC_AM5_QOS_CTRL0 (S_DMC_REG_BASE + (0x9a << 2)) -#define P_DMC_AM5_QOS_CTRL0 MMC_REG_ADDR(DMC_AM5_QOS_CTRL0) -#define DMC_AM5_QOS_CTRL1 (S_DMC_REG_BASE + (0x9b << 2)) -#define P_DMC_AM5_QOS_CTRL1 MMC_REG_ADDR(DMC_AM5_QOS_CTRL1) -#define DMC_AM6_CHAN_CTRL (S_DMC_REG_BASE + (0x9c << 2)) -#define P_DMC_AM6_CHAN_CTRL MMC_REG_ADDR(DMC_AM6_CHAN_CTRL) -#define DMC_AM6_HOLD_CTRL (S_DMC_REG_BASE + (0x9d << 2)) -#define P_DMC_AM6_HOLD_CTRL MMC_REG_ADDR(DMC_AM6_HOLD_CTRL) -#define DMC_AM6_QOS_INC (S_DMC_REG_BASE + (0x9e << 2)) -#define P_DMC_AM6_QOS_INC MMC_REG_ADDR(DMC_AM6_QOS_INC) -#define DMC_AM6_QOS_INCBK (S_DMC_REG_BASE + (0x9f << 2)) -#define P_DMC_AM6_QOS_INCBK MMC_REG_ADDR(DMC_AM6_QOS_INCBK) -#define DMC_AM6_QOS_DEC (S_DMC_REG_BASE + (0xa0 << 2)) -#define P_DMC_AM6_QOS_DEC MMC_REG_ADDR(DMC_AM6_QOS_DEC) -#define DMC_AM6_QOS_DECBK (S_DMC_REG_BASE + (0xa1 << 2)) -#define P_DMC_AM6_QOS_DECBK MMC_REG_ADDR(DMC_AM6_QOS_DECBK) -#define DMC_AM6_QOS_DIS (S_DMC_REG_BASE + (0xa2 << 2)) -#define P_DMC_AM6_QOS_DIS MMC_REG_ADDR(DMC_AM6_QOS_DIS) -#define DMC_AM6_QOS_DISBK (S_DMC_REG_BASE + (0xa3 << 2)) -#define P_DMC_AM6_QOS_DISBK MMC_REG_ADDR(DMC_AM6_QOS_DISBK) -#define DMC_AM6_QOS_CTRL0 (S_DMC_REG_BASE + (0xa4 << 2)) -#define P_DMC_AM6_QOS_CTRL0 MMC_REG_ADDR(DMC_AM6_QOS_CTRL0) -#define DMC_AM6_QOS_CTRL1 (S_DMC_REG_BASE + (0xa5 << 2)) -#define P_DMC_AM6_QOS_CTRL1 MMC_REG_ADDR(DMC_AM6_QOS_CTRL1) -#define DMC_AM7_CHAN_CTRL (S_DMC_REG_BASE + (0xa6 << 2)) -#define P_DMC_AM7_CHAN_CTRL MMC_REG_ADDR(DMC_AM7_CHAN_CTRL) -#define DMC_AM7_HOLD_CTRL (S_DMC_REG_BASE + (0xa7 << 2)) -#define P_DMC_AM7_HOLD_CTRL MMC_REG_ADDR(DMC_AM7_HOLD_CTRL) -#define DMC_AM7_QOS_INC (S_DMC_REG_BASE + (0xa8 << 2)) -#define P_DMC_AM7_QOS_INC MMC_REG_ADDR(DMC_AM7_QOS_INC) -#define DMC_AM7_QOS_INCBK (S_DMC_REG_BASE + (0xa9 << 2)) -#define P_DMC_AM7_QOS_INCBK MMC_REG_ADDR(DMC_AM7_QOS_INCBK) -#define DMC_AM7_QOS_DEC (S_DMC_REG_BASE + (0xaa << 2)) -#define P_DMC_AM7_QOS_DEC MMC_REG_ADDR(DMC_AM7_QOS_DEC) -#define DMC_AM7_QOS_DECBK (S_DMC_REG_BASE + (0xab << 2)) -#define P_DMC_AM7_QOS_DECBK MMC_REG_ADDR(DMC_AM7_QOS_DECBK) -#define DMC_AM7_QOS_DIS (S_DMC_REG_BASE + (0xac << 2)) -#define P_DMC_AM7_QOS_DIS MMC_REG_ADDR(DMC_AM7_QOS_DIS) -#define DMC_AM7_QOS_DISBK (S_DMC_REG_BASE + (0xad << 2)) -#define P_DMC_AM7_QOS_DISBK MMC_REG_ADDR(DMC_AM7_QOS_DISBK) -#define DMC_AM7_QOS_CTRL0 (S_DMC_REG_BASE + (0xae << 2)) -#define P_DMC_AM7_QOS_CTRL0 MMC_REG_ADDR(DMC_AM7_QOS_CTRL0) -#define DMC_AM7_QOS_CTRL1 (S_DMC_REG_BASE + (0xaf << 2)) -#define P_DMC_AM7_QOS_CTRL1 MMC_REG_ADDR(DMC_AM7_QOS_CTRL1) -#define DMC_AXI0_CHAN_CTRL (S_DMC_REG_BASE + (0xb0 << 2)) -#define P_DMC_AXI0_CHAN_CTRL MMC_REG_ADDR(DMC_AXI0_CHAN_CTRL) -#define DMC_AXI0_HOLD_CTRL (S_DMC_REG_BASE + (0xb1 << 2)) -#define P_DMC_AXI0_HOLD_CTRL MMC_REG_ADDR(DMC_AXI0_HOLD_CTRL) -#define DMC_AXI0_QOS_INC (S_DMC_REG_BASE + (0xb2 << 2)) -#define P_DMC_AXI0_QOS_INC MMC_REG_ADDR(DMC_AXI0_QOS_INC) -#define DMC_AXI0_QOS_INCBK (S_DMC_REG_BASE + (0xb3 << 2)) -#define P_DMC_AXI0_QOS_INCBK MMC_REG_ADDR(DMC_AXI0_QOS_INCBK) -#define DMC_AXI0_QOS_DEC (S_DMC_REG_BASE + (0xb4 << 2)) -#define P_DMC_AXI0_QOS_DEC MMC_REG_ADDR(DMC_AXI0_QOS_DEC) -#define DMC_AXI0_QOS_DECBK (S_DMC_REG_BASE + (0xb5 << 2)) -#define P_DMC_AXI0_QOS_DECBK MMC_REG_ADDR(DMC_AXI0_QOS_DECBK) -#define DMC_AXI0_QOS_DIS (S_DMC_REG_BASE + (0xb6 << 2)) -#define P_DMC_AXI0_QOS_DIS MMC_REG_ADDR(DMC_AXI0_QOS_DIS) -#define DMC_AXI0_QOS_DISBK (S_DMC_REG_BASE + (0xb7 << 2)) -#define P_DMC_AXI0_QOS_DISBK MMC_REG_ADDR(DMC_AXI0_QOS_DISBK) -#define DMC_AXI0_QOS_CTRL0 (S_DMC_REG_BASE + (0xb8 << 2)) -#define P_DMC_AXI0_QOS_CTRL0 MMC_REG_ADDR(DMC_AXI0_QOS_CTRL0) -#define DMC_AXI0_QOS_CTRL1 (S_DMC_REG_BASE + (0xb9 << 2)) -#define P_DMC_AXI0_QOS_CTRL1 MMC_REG_ADDR(DMC_AXI0_QOS_CTRL1) -#define DMC_AXI1_CHAN_CTRL (S_DMC_REG_BASE + (0xba << 2)) -#define P_DMC_AXI1_CHAN_CTRL MMC_REG_ADDR(DMC_AXI1_CHAN_CTRL) -#define DMC_AXI1_HOLD_CTRL (S_DMC_REG_BASE + (0xbb << 2)) -#define P_DMC_AXI1_HOLD_CTRL MMC_REG_ADDR(DMC_AXI1_HOLD_CTRL) -#define DMC_AXI1_QOS_INC (S_DMC_REG_BASE + (0xbc << 2)) -#define P_DMC_AXI1_QOS_INC MMC_REG_ADDR(DMC_AXI1_QOS_INC) -#define DMC_AXI1_QOS_INCBK (S_DMC_REG_BASE + (0xbd << 2)) -#define P_DMC_AXI1_QOS_INCBK MMC_REG_ADDR(DMC_AXI1_QOS_INCBK) -#define DMC_AXI1_QOS_DEC (S_DMC_REG_BASE + (0xbe << 2)) -#define P_DMC_AXI1_QOS_DEC MMC_REG_ADDR(DMC_AXI1_QOS_DEC) -#define DMC_AXI1_QOS_DECBK (S_DMC_REG_BASE + (0xbf << 2)) -#define P_DMC_AXI1_QOS_DECBK MMC_REG_ADDR(DMC_AXI1_QOS_DECBK) -#define DMC_AXI1_QOS_DIS (S_DMC_REG_BASE + (0xc0 << 2)) -#define P_DMC_AXI1_QOS_DIS MMC_REG_ADDR(DMC_AXI1_QOS_DIS) -#define DMC_AXI1_QOS_DISBK (S_DMC_REG_BASE + (0xc1 << 2)) -#define P_DMC_AXI1_QOS_DISBK MMC_REG_ADDR(DMC_AXI1_QOS_DISBK) -#define DMC_AXI1_QOS_CTRL0 (S_DMC_REG_BASE + (0xc2 << 2)) -#define P_DMC_AXI1_QOS_CTRL0 MMC_REG_ADDR(DMC_AXI1_QOS_CTRL0) -#define DMC_AXI1_QOS_CTRL1 (S_DMC_REG_BASE + (0xc3 << 2)) -#define P_DMC_AXI1_QOS_CTRL1 MMC_REG_ADDR(DMC_AXI1_QOS_CTRL1) -#define DMC_AXI2_CHAN_CTRL (S_DMC_REG_BASE + (0xc4 << 2)) -#define P_DMC_AXI2_CHAN_CTRL MMC_REG_ADDR(DMC_AXI2_CHAN_CTRL) -#define DMC_AXI2_HOLD_CTRL (S_DMC_REG_BASE + (0xc5 << 2)) -#define P_DMC_AXI2_HOLD_CTRL MMC_REG_ADDR(DMC_AXI2_HOLD_CTRL) -#define DMC_AXI2_QOS_INC (S_DMC_REG_BASE + (0xc6 << 2)) -#define P_DMC_AXI2_QOS_INC MMC_REG_ADDR(DMC_AXI2_QOS_INC) -#define DMC_AXI2_QOS_INCBK (S_DMC_REG_BASE + (0xc7 << 2)) -#define P_DMC_AXI2_QOS_INCBK MMC_REG_ADDR(DMC_AXI2_QOS_INCBK) -#define DMC_AXI2_QOS_DEC (S_DMC_REG_BASE + (0xc8 << 2)) -#define P_DMC_AXI2_QOS_DEC MMC_REG_ADDR(DMC_AXI2_QOS_DEC) -#define DMC_AXI2_QOS_DECBK (S_DMC_REG_BASE + (0xc9 << 2)) -#define P_DMC_AXI2_QOS_DECBK MMC_REG_ADDR(DMC_AXI2_QOS_DECBK) -#define DMC_AXI2_QOS_DIS (S_DMC_REG_BASE + (0xca << 2)) -#define P_DMC_AXI2_QOS_DIS MMC_REG_ADDR(DMC_AXI2_QOS_DIS) -#define DMC_AXI2_QOS_DISBK (S_DMC_REG_BASE + (0xcb << 2)) -#define P_DMC_AXI2_QOS_DISBK MMC_REG_ADDR(DMC_AXI2_QOS_DISBK) -#define DMC_AXI2_QOS_CTRL0 (S_DMC_REG_BASE + (0xcc << 2)) -#define P_DMC_AXI2_QOS_CTRL0 MMC_REG_ADDR(DMC_AXI2_QOS_CTRL0) -#define DMC_AXI2_QOS_CTRL1 (S_DMC_REG_BASE + (0xcd << 2)) -#define P_DMC_AXI2_QOS_CTRL1 MMC_REG_ADDR(DMC_AXI2_QOS_CTRL1) -#define DMC_AXI3_CHAN_CTRL (S_DMC_REG_BASE + (0xce << 2)) -#define P_DMC_AXI3_CHAN_CTRL MMC_REG_ADDR(DMC_AXI3_CHAN_CTRL) -#define DMC_AXI3_HOLD_CTRL (S_DMC_REG_BASE + (0xcf << 2)) -#define P_DMC_AXI3_HOLD_CTRL MMC_REG_ADDR(DMC_AXI3_HOLD_CTRL) -#define DMC_AXI3_QOS_INC (S_DMC_REG_BASE + (0xd0 << 2)) -#define P_DMC_AXI3_QOS_INC MMC_REG_ADDR(DMC_AXI3_QOS_INC) -#define DMC_AXI3_QOS_INCBK (S_DMC_REG_BASE + (0xd1 << 2)) -#define P_DMC_AXI3_QOS_INCBK MMC_REG_ADDR(DMC_AXI3_QOS_INCBK) -#define DMC_AXI3_QOS_DEC (S_DMC_REG_BASE + (0xd2 << 2)) -#define P_DMC_AXI3_QOS_DEC MMC_REG_ADDR(DMC_AXI3_QOS_DEC) -#define DMC_AXI3_QOS_DECBK (S_DMC_REG_BASE + (0xd3 << 2)) -#define P_DMC_AXI3_QOS_DECBK MMC_REG_ADDR(DMC_AXI3_QOS_DECBK) -#define DMC_AXI3_QOS_DIS (S_DMC_REG_BASE + (0xd4 << 2)) -#define P_DMC_AXI3_QOS_DIS MMC_REG_ADDR(DMC_AXI3_QOS_DIS) -#define DMC_AXI3_QOS_DISBK (S_DMC_REG_BASE + (0xd5 << 2)) -#define P_DMC_AXI3_QOS_DISBK MMC_REG_ADDR(DMC_AXI3_QOS_DISBK) -#define DMC_AXI3_QOS_CTRL0 (S_DMC_REG_BASE + (0xd6 << 2)) -#define P_DMC_AXI3_QOS_CTRL0 MMC_REG_ADDR(DMC_AXI3_QOS_CTRL0) -#define DMC_AXI3_QOS_CTRL1 (S_DMC_REG_BASE + (0xd7 << 2)) -#define P_DMC_AXI3_QOS_CTRL1 MMC_REG_ADDR(DMC_AXI3_QOS_CTRL1) -#define DMC_AXI4_CHAN_CTRL (S_DMC_REG_BASE + (0xd8 << 2)) -#define P_DMC_AXI4_CHAN_CTRL MMC_REG_ADDR(DMC_AXI4_CHAN_CTRL) -#define DMC_AXI4_HOLD_CTRL (S_DMC_REG_BASE + (0xd9 << 2)) -#define P_DMC_AXI4_HOLD_CTRL MMC_REG_ADDR(DMC_AXI4_HOLD_CTRL) -#define DMC_AXI4_QOS_INC (S_DMC_REG_BASE + (0xda << 2)) -#define P_DMC_AXI4_QOS_INC MMC_REG_ADDR(DMC_AXI4_QOS_INC) -#define DMC_AXI4_QOS_INCBK (S_DMC_REG_BASE + (0xdb << 2)) -#define P_DMC_AXI4_QOS_INCBK MMC_REG_ADDR(DMC_AXI4_QOS_INCBK) -#define DMC_AXI4_QOS_DEC (S_DMC_REG_BASE + (0xdc << 2)) -#define P_DMC_AXI4_QOS_DEC MMC_REG_ADDR(DMC_AXI4_QOS_DEC) -#define DMC_AXI4_QOS_DECBK (S_DMC_REG_BASE + (0xdd << 2)) -#define P_DMC_AXI4_QOS_DECBK MMC_REG_ADDR(DMC_AXI4_QOS_DECBK) -#define DMC_AXI4_QOS_DIS (S_DMC_REG_BASE + (0xde << 2)) -#define P_DMC_AXI4_QOS_DIS MMC_REG_ADDR(DMC_AXI4_QOS_DIS) -#define DMC_AXI4_QOS_DISBK (S_DMC_REG_BASE + (0xdf << 2)) -#define P_DMC_AXI4_QOS_DISBK MMC_REG_ADDR(DMC_AXI4_QOS_DISBK) -#define DMC_AXI4_QOS_CTRL0 (S_DMC_REG_BASE + (0xe0 << 2)) -#define P_DMC_AXI4_QOS_CTRL0 MMC_REG_ADDR(DMC_AXI4_QOS_CTRL0) -#define DMC_AXI4_QOS_CTRL1 (S_DMC_REG_BASE + (0xe1 << 2)) -#define P_DMC_AXI4_QOS_CTRL1 MMC_REG_ADDR(DMC_AXI4_QOS_CTRL1) -#define DMC_AXI5_CHAN_CTRL (S_DMC_REG_BASE + (0xe2 << 2)) -#define P_DMC_AXI5_CHAN_CTRL MMC_REG_ADDR(DMC_AXI5_CHAN_CTRL) -#define DMC_AXI5_HOLD_CTRL (S_DMC_REG_BASE + (0xe3 << 2)) -#define P_DMC_AXI5_HOLD_CTRL MMC_REG_ADDR(DMC_AXI5_HOLD_CTRL) -#define DMC_AXI5_QOS_INC (S_DMC_REG_BASE + (0xe4 << 2)) -#define P_DMC_AXI5_QOS_INC MMC_REG_ADDR(DMC_AXI5_QOS_INC) -#define DMC_AXI5_QOS_INCBK (S_DMC_REG_BASE + (0xe5 << 2)) -#define P_DMC_AXI5_QOS_INCBK MMC_REG_ADDR(DMC_AXI5_QOS_INCBK) -#define DMC_AXI5_QOS_DEC (S_DMC_REG_BASE + (0xe6 << 2)) -#define P_DMC_AXI5_QOS_DEC MMC_REG_ADDR(DMC_AXI5_QOS_DEC) -#define DMC_AXI5_QOS_DECBK (S_DMC_REG_BASE + (0xe7 << 2)) -#define P_DMC_AXI5_QOS_DECBK MMC_REG_ADDR(DMC_AXI5_QOS_DECBK) -#define DMC_AXI5_QOS_DIS (S_DMC_REG_BASE + (0xe8 << 2)) -#define P_DMC_AXI5_QOS_DIS MMC_REG_ADDR(DMC_AXI5_QOS_DIS) -#define DMC_AXI5_QOS_DISBK (S_DMC_REG_BASE + (0xe9 << 2)) -#define P_DMC_AXI5_QOS_DISBK MMC_REG_ADDR(DMC_AXI5_QOS_DISBK) -#define DMC_AXI5_QOS_CTRL0 (S_DMC_REG_BASE + (0xea << 2)) -#define P_DMC_AXI5_QOS_CTRL0 MMC_REG_ADDR(DMC_AXI5_QOS_CTRL0) -#define DMC_AXI5_QOS_CTRL1 (S_DMC_REG_BASE + (0xeb << 2)) -#define P_DMC_AXI5_QOS_CTRL1 MMC_REG_ADDR(DMC_AXI5_QOS_CTRL1) -#define DMC_AXI6_CHAN_CTRL (S_DMC_REG_BASE + (0xec << 2)) -#define P_DMC_AXI6_CHAN_CTRL MMC_REG_ADDR(DMC_AXI6_CHAN_CTRL) -#define DMC_AXI6_HOLD_CTRL (S_DMC_REG_BASE + (0xed << 2)) -#define P_DMC_AXI6_HOLD_CTRL MMC_REG_ADDR(DMC_AXI6_HOLD_CTRL) -#define DMC_AXI6_QOS_INC (S_DMC_REG_BASE + (0xee << 2)) -#define P_DMC_AXI6_QOS_INC MMC_REG_ADDR(DMC_AXI6_QOS_INC) -#define DMC_AXI6_QOS_INCBK (S_DMC_REG_BASE + (0xef << 2)) -#define P_DMC_AXI6_QOS_INCBK MMC_REG_ADDR(DMC_AXI6_QOS_INCBK) -#define DMC_AXI6_QOS_DEC (S_DMC_REG_BASE + (0xf0 << 2)) -#define P_DMC_AXI6_QOS_DEC MMC_REG_ADDR(DMC_AXI6_QOS_DEC) -#define DMC_AXI6_QOS_DECBK (S_DMC_REG_BASE + (0xf1 << 2)) -#define P_DMC_AXI6_QOS_DECBK MMC_REG_ADDR(DMC_AXI6_QOS_DECBK) -#define DMC_AXI6_QOS_DIS (S_DMC_REG_BASE + (0xf2 << 2)) -#define P_DMC_AXI6_QOS_DIS MMC_REG_ADDR(DMC_AXI6_QOS_DIS) -#define DMC_AXI6_QOS_DISBK (S_DMC_REG_BASE + (0xf3 << 2)) -#define P_DMC_AXI6_QOS_DISBK MMC_REG_ADDR(DMC_AXI6_QOS_DISBK) -#define DMC_AXI6_QOS_CTRL0 (S_DMC_REG_BASE + (0xf4 << 2)) -#define P_DMC_AXI6_QOS_CTRL0 MMC_REG_ADDR(DMC_AXI6_QOS_CTRL0) -#define DMC_AXI6_QOS_CTRL1 (S_DMC_REG_BASE + (0xf5 << 2)) -#define P_DMC_AXI6_QOS_CTRL1 MMC_REG_ADDR(DMC_AXI6_QOS_CTRL1) -#define DMC_AXI7_CHAN_CTRL (S_DMC_REG_BASE + (0xf6 << 2)) -#define P_DMC_AXI7_CHAN_CTRL MMC_REG_ADDR(DMC_AXI7_CHAN_CTRL) -#define DMC_AXI7_HOLD_CTRL (S_DMC_REG_BASE + (0xf7 << 2)) -#define P_DMC_AXI7_HOLD_CTRL MMC_REG_ADDR(DMC_AXI7_HOLD_CTRL) -#define DMC_AXI7_QOS_INC (S_DMC_REG_BASE + (0xf8 << 2)) -#define P_DMC_AXI7_QOS_INC MMC_REG_ADDR(DMC_AXI7_QOS_INC) -#define DMC_AXI7_QOS_INCBK (S_DMC_REG_BASE + (0xf9 << 2)) -#define P_DMC_AXI7_QOS_INCBK MMC_REG_ADDR(DMC_AXI7_QOS_INCBK) -#define DMC_AXI7_QOS_DEC (S_DMC_REG_BASE + (0xfa << 2)) -#define P_DMC_AXI7_QOS_DEC MMC_REG_ADDR(DMC_AXI7_QOS_DEC) -#define DMC_AXI7_QOS_DECBK (S_DMC_REG_BASE + (0xfb << 2)) -#define P_DMC_AXI7_QOS_DECBK MMC_REG_ADDR(DMC_AXI7_QOS_DECBK) -#define DMC_AXI7_QOS_DIS (S_DMC_REG_BASE + (0xfc << 2)) -#define P_DMC_AXI7_QOS_DIS MMC_REG_ADDR(DMC_AXI7_QOS_DIS) -#define DMC_AXI7_QOS_DISBK (S_DMC_REG_BASE + (0xfd << 2)) -#define P_DMC_AXI7_QOS_DISBK MMC_REG_ADDR(DMC_AXI7_QOS_DISBK) -#define DMC_AXI7_QOS_CTRL0 (S_DMC_REG_BASE + (0xfe << 2)) -#define P_DMC_AXI7_QOS_CTRL0 MMC_REG_ADDR(DMC_AXI7_QOS_CTRL0) -#define DMC_AXI7_QOS_CTRL1 (S_DMC_REG_BASE + (0xff << 2)) -#define P_DMC_AXI7_QOS_CTRL1 MMC_REG_ADDR(DMC_AXI7_QOS_CTRL1) /**/ -#define STB_VERSION 0x1600 +#define STB_VERSION (STB_CBUS_BASE + 0x00) #define P_STB_VERSION CBUS_REG_ADDR(STB_VERSION) -#define STB_VERSION_2 0x1650 +#define STB_VERSION_2 (STB_CBUS_BASE + 0x50) #define P_STB_VERSION_2 CBUS_REG_ADDR(STB_VERSION_2) -#define STB_VERSION_3 0x16a0 +#define STB_VERSION_3 (STB_CBUS_BASE + 0xa0) #define P_STB_VERSION_3 CBUS_REG_ADDR(STB_VERSION_3) -#define STB_TEST_REG 0x1601 +#define STB_TEST_REG (STB_CBUS_BASE + 0x01) #define P_STB_TEST_REG CBUS_REG_ADDR(STB_TEST_REG) -#define STB_TEST_REG_2 0x1651 +#define STB_TEST_REG_2 (STB_CBUS_BASE + 0x51) #define P_STB_TEST_REG_2 CBUS_REG_ADDR(STB_TEST_REG_2) -#define STB_TEST_REG_3 0x16a1 +#define STB_TEST_REG_3 (STB_CBUS_BASE + 0xa1) #define P_STB_TEST_REG_3 CBUS_REG_ADDR(STB_TEST_REG_3) -#define FEC_INPUT_CONTROL 0x1602 + +#define FEC_INPUT_CONTROL (STB_CBUS_BASE + 0x2) #define P_FEC_INPUT_CONTROL CBUS_REG_ADDR(FEC_INPUT_CONTROL) -#define FEC_INPUT_CONTROL_2 0x1652 +#define FEC_INPUT_CONTROL_2 (STB_CBUS_BASE + 0x52) #define P_FEC_INPUT_CONTROL_2 CBUS_REG_ADDR(FEC_INPUT_CONTROL_2) -#define FEC_INPUT_CONTROL_3 0x16a2 +#define FEC_INPUT_CONTROL_3 (STB_CBUS_BASE + 0xa2) #define P_FEC_INPUT_CONTROL_3 CBUS_REG_ADDR(FEC_INPUT_CONTROL_3) -#define FEC_INPUT_DATA 0x1603 +/*no used*/ +#define FEC_INPUT_DATA (STB_CBUS_BASE + 0x03) #define P_FEC_INPUT_DATA CBUS_REG_ADDR(FEC_INPUT_DATA) -#define FEC_INPUT_DATA_2 0x1653 +#define FEC_INPUT_DATA_2 (STB_CBUS_BASE + 0x53) #define P_FEC_INPUT_DATA_2 CBUS_REG_ADDR(FEC_INPUT_DATA_2) -#define FEC_INPUT_DATA_3 0x16a3 +#define FEC_INPUT_DATA_3 (STB_CBUS_BASE + 0xa3) #define P_FEC_INPUT_DATA_3 CBUS_REG_ADDR(FEC_INPUT_DATA_3) -#define DEMUX_CONTROL 0x1604 +/*no used end*/ +#define DEMUX_CONTROL (STB_CBUS_BASE + 0x04) #define P_DEMUX_CONTROL CBUS_REG_ADDR(DEMUX_CONTROL) -#define DEMUX_CONTROL_2 0x1654 +#define DEMUX_CONTROL_2 (STB_CBUS_BASE + 0x54) #define P_DEMUX_CONTROL_2 CBUS_REG_ADDR(DEMUX_CONTROL_2) -#define DEMUX_CONTROL_3 0x16a4 +#define DEMUX_CONTROL_3 (STB_CBUS_BASE + 0xa4) #define P_DEMUX_CONTROL_3 CBUS_REG_ADDR(DEMUX_CONTROL_3) -#define FEC_SYNC_BYTE 0x1605 +/*no used*/ +#define FEC_SYNC_BYTE (STB_CBUS_BASE + 0x05) #define P_FEC_SYNC_BYTE CBUS_REG_ADDR(FEC_SYNC_BYTE) -#define FEC_SYNC_BYTE_2 0x1655 +#define FEC_SYNC_BYTE_2 (STB_CBUS_BASE + 0x55) #define P_FEC_SYNC_BYTE_2 CBUS_REG_ADDR(FEC_SYNC_BYTE_2) -#define FEC_SYNC_BYTE_3 0x16a5 +#define FEC_SYNC_BYTE_3 (STB_CBUS_BASE + 0xa5) #define P_FEC_SYNC_BYTE_3 CBUS_REG_ADDR(FEC_SYNC_BYTE_3) -#define FM_WR_DATA 0x1606 +/*no used end*/ + +#define FM_WR_DATA (STB_CBUS_BASE + 0x06) #define P_FM_WR_DATA CBUS_REG_ADDR(FM_WR_DATA) -#define FM_WR_DATA_2 0x1656 +#define FM_WR_DATA_2 (STB_CBUS_BASE + 0x56) #define P_FM_WR_DATA_2 CBUS_REG_ADDR(FM_WR_DATA_2) -#define FM_WR_DATA_3 0x16a6 +#define FM_WR_DATA_3 (STB_CBUS_BASE + 0xa6) #define P_FM_WR_DATA_3 CBUS_REG_ADDR(FM_WR_DATA_3) -#define FM_WR_ADDR 0x1607 +#define FM_WR_ADDR (STB_CBUS_BASE + 0x07) #define P_FM_WR_ADDR CBUS_REG_ADDR(FM_WR_ADDR) -#define FM_WR_ADDR_2 0x1657 +#define FM_WR_ADDR_2 (STB_CBUS_BASE + 0x57) #define P_FM_WR_ADDR_2 CBUS_REG_ADDR(FM_WR_ADDR_2) -#define FM_WR_ADDR_3 0x16a7 +#define FM_WR_ADDR_3 (STB_CBUS_BASE + 0xa7) #define P_FM_WR_ADDR_3 CBUS_REG_ADDR(FM_WR_ADDR_3) -#define MAX_FM_COMP_ADDR 0x1608 +#define MAX_FM_COMP_ADDR (STB_CBUS_BASE + 0x08) #define P_MAX_FM_COMP_ADDR CBUS_REG_ADDR(MAX_FM_COMP_ADDR) -#define MAX_FM_COMP_ADDR_2 0x1658 +#define MAX_FM_COMP_ADDR_2 (STB_CBUS_BASE + 0x58) #define P_MAX_FM_COMP_ADDR_2 CBUS_REG_ADDR(MAX_FM_COMP_ADDR_2) -#define MAX_FM_COMP_ADDR_3 0x16a8 +#define MAX_FM_COMP_ADDR_3 (STB_CBUS_BASE + 0xa8) #define P_MAX_FM_COMP_ADDR_3 CBUS_REG_ADDR(MAX_FM_COMP_ADDR_3) -#define TS_HEAD_0 0x1609 + +#define TS_HEAD_0 (STB_CBUS_BASE + 0x09) #define P_TS_HEAD_0 CBUS_REG_ADDR(TS_HEAD_0) -#define TS_HEAD_0_2 0x1659 +#define TS_HEAD_0_2 (STB_CBUS_BASE + 0x59) #define P_TS_HEAD_0_2 CBUS_REG_ADDR(TS_HEAD_0_2) -#define TS_HEAD_0_3 0x16a9 +#define TS_HEAD_0_3 (STB_CBUS_BASE + 0xa9) #define P_TS_HEAD_0_3 CBUS_REG_ADDR(TS_HEAD_0_3) -#define TS_HEAD_1 0x160a +#define TS_HEAD_1 (STB_CBUS_BASE + 0x0a) #define P_TS_HEAD_1 CBUS_REG_ADDR(TS_HEAD_1) -#define TS_HEAD_1_2 0x165a +#define TS_HEAD_1_2 (STB_CBUS_BASE + 0x5a) #define P_TS_HEAD_1_2 CBUS_REG_ADDR(TS_HEAD_1_2) -#define TS_HEAD_1_3 0x16aa +#define TS_HEAD_1_3 (STB_CBUS_BASE + 0xaa) #define P_TS_HEAD_1_3 CBUS_REG_ADDR(TS_HEAD_1_3) -#define OM_CMD_STATUS 0x160b + +#define OM_CMD_STATUS (STB_CBUS_BASE + 0x0b) #define P_OM_CMD_STATUS CBUS_REG_ADDR(OM_CMD_STATUS) -#define OM_CMD_STATUS_2 0x165b +#define OM_CMD_STATUS_2 (STB_CBUS_BASE + 0x5b) #define P_OM_CMD_STATUS_2 CBUS_REG_ADDR(OM_CMD_STATUS_2) -#define OM_CMD_STATUS_3 0x16ab +#define OM_CMD_STATUS_3 (STB_CBUS_BASE + 0xab) #define P_OM_CMD_STATUS_3 CBUS_REG_ADDR(OM_CMD_STATUS_3) -#define OM_CMD_DATA 0x160c + +#define OM_CMD_DATA (STB_CBUS_BASE + 0x0c) #define P_OM_CMD_DATA CBUS_REG_ADDR(OM_CMD_DATA) -#define OM_CMD_DATA_2 0x165c +#define OM_CMD_DATA_2 (STB_CBUS_BASE + 0x5c) #define P_OM_CMD_DATA_2 CBUS_REG_ADDR(OM_CMD_DATA_2) -#define OM_CMD_DATA_3 0x16ac +#define OM_CMD_DATA_3 (STB_CBUS_BASE + 0xac) #define P_OM_CMD_DATA_3 CBUS_REG_ADDR(OM_CMD_DATA_3) -#define OM_CMD_DATA2 0x160d +#define OM_CMD_DATA2 (STB_CBUS_BASE + 0x0d) #define P_OM_CMD_DATA2 CBUS_REG_ADDR(OM_CMD_DATA2) -#define OM_CMD_DATA2_2 0x165d +#define OM_CMD_DATA2_2 (STB_CBUS_BASE + 0x5d) #define P_OM_CMD_DATA2_2 CBUS_REG_ADDR(OM_CMD_DATA2_2) -#define OM_CMD_DATA2_3 0x16ad +#define OM_CMD_DATA2_3 (STB_CBUS_BASE + 0xad) #define P_OM_CMD_DATA2_3 CBUS_REG_ADDR(OM_CMD_DATA2_3) -#define SEC_BUFF_01_START 0x160e + +#define SEC_BUFF_01_START (STB_CBUS_BASE + 0x0e) #define P_SEC_BUFF_01_START CBUS_REG_ADDR(SEC_BUFF_01_START) -#define SEC_BUFF_01_START_2 0x165e +#define SEC_BUFF_01_START_2 (STB_CBUS_BASE + 0x5e) #define P_SEC_BUFF_01_START_2 CBUS_REG_ADDR(SEC_BUFF_01_START_2) -#define SEC_BUFF_01_START_3 0x16ae +#define SEC_BUFF_01_START_3 (STB_CBUS_BASE + 0xae) #define P_SEC_BUFF_01_START_3 CBUS_REG_ADDR(SEC_BUFF_01_START_3) -#define SEC_BUFF_23_START 0x160f +#define SEC_BUFF_23_START (STB_CBUS_BASE + 0x0f) #define P_SEC_BUFF_23_START CBUS_REG_ADDR(SEC_BUFF_23_START) -#define SEC_BUFF_23_START_2 0x165f +#define SEC_BUFF_23_START_2 (STB_CBUS_BASE + 0x5f) #define P_SEC_BUFF_23_START_2 CBUS_REG_ADDR(SEC_BUFF_23_START_2) -#define SEC_BUFF_23_START_3 0x16af +#define SEC_BUFF_23_START_3 (STB_CBUS_BASE + 0xaf) #define P_SEC_BUFF_23_START_3 CBUS_REG_ADDR(SEC_BUFF_23_START_3) -#define SEC_BUFF_SIZE 0x1610 +#define SEC_BUFF_SIZE (STB_CBUS_BASE + 0x10) #define P_SEC_BUFF_SIZE CBUS_REG_ADDR(SEC_BUFF_SIZE) -#define SEC_BUFF_SIZE_2 0x1660 +#define SEC_BUFF_SIZE_2 (STB_CBUS_BASE + 0x60) #define P_SEC_BUFF_SIZE_2 CBUS_REG_ADDR(SEC_BUFF_SIZE_2) -#define SEC_BUFF_SIZE_3 0x16b0 +#define SEC_BUFF_SIZE_3 (STB_CBUS_BASE + 0xb0) #define P_SEC_BUFF_SIZE_3 CBUS_REG_ADDR(SEC_BUFF_SIZE_3) -#define SEC_BUFF_BUSY 0x1611 +#define SEC_BUFF_BUSY (STB_CBUS_BASE + 0x11) #define P_SEC_BUFF_BUSY CBUS_REG_ADDR(SEC_BUFF_BUSY) -#define SEC_BUFF_BUSY_2 0x1661 +#define SEC_BUFF_BUSY_2 (STB_CBUS_BASE + 0x61) #define P_SEC_BUFF_BUSY_2 CBUS_REG_ADDR(SEC_BUFF_BUSY_2) -#define SEC_BUFF_BUSY_3 0x16b1 +#define SEC_BUFF_BUSY_3 (STB_CBUS_BASE + 0xb1) #define P_SEC_BUFF_BUSY_3 CBUS_REG_ADDR(SEC_BUFF_BUSY_3) -#define SEC_BUFF_READY 0x1612 +#define SEC_BUFF_READY (STB_CBUS_BASE + 0x12) #define P_SEC_BUFF_READY CBUS_REG_ADDR(SEC_BUFF_READY) -#define SEC_BUFF_READY_2 0x1662 +#define SEC_BUFF_READY_2 (STB_CBUS_BASE + 0x62) #define P_SEC_BUFF_READY_2 CBUS_REG_ADDR(SEC_BUFF_READY_2) -#define SEC_BUFF_READY_3 0x16b2 +#define SEC_BUFF_READY_3 (STB_CBUS_BASE + 0xb2) #define P_SEC_BUFF_READY_3 CBUS_REG_ADDR(SEC_BUFF_READY_3) -#define SEC_BUFF_NUMBER 0x1613 +#define SEC_BUFF_NUMBER (STB_CBUS_BASE + 0x13) #define P_SEC_BUFF_NUMBER CBUS_REG_ADDR(SEC_BUFF_NUMBER) -#define SEC_BUFF_NUMBER_2 0x1663 +#define SEC_BUFF_NUMBER_2 (STB_CBUS_BASE + 0x63) #define P_SEC_BUFF_NUMBER_2 CBUS_REG_ADDR(SEC_BUFF_NUMBER_2) -#define SEC_BUFF_NUMBER_3 0x16b3 +#define SEC_BUFF_NUMBER_3 (STB_CBUS_BASE + 0xb3) #define P_SEC_BUFF_NUMBER_3 CBUS_REG_ADDR(SEC_BUFF_NUMBER_3) -#define ASSIGN_PID_NUMBER 0x1614 + + +/**no used*/ +#define ASSIGN_PID_NUMBER (STB_CBUS_BASE + 0x14) #define P_ASSIGN_PID_NUMBER CBUS_REG_ADDR(ASSIGN_PID_NUMBER) -#define ASSIGN_PID_NUMBER_2 0x1664 +#define ASSIGN_PID_NUMBER_2 (STB_CBUS_BASE + 0x64) #define P_ASSIGN_PID_NUMBER_2 CBUS_REG_ADDR(ASSIGN_PID_NUMBER_2) -#define ASSIGN_PID_NUMBER_3 0x16b4 +#define ASSIGN_PID_NUMBER_3 (STB_CBUS_BASE + 0xb4) #define P_ASSIGN_PID_NUMBER_3 CBUS_REG_ADDR(ASSIGN_PID_NUMBER_3) -#define VIDEO_STREAM_ID 0x1615 +#define VIDEO_STREAM_ID (STB_CBUS_BASE + 0x15) #define P_VIDEO_STREAM_ID CBUS_REG_ADDR(VIDEO_STREAM_ID) -#define VIDEO_STREAM_ID_2 0x1665 +#define VIDEO_STREAM_ID_2 (STB_CBUS_BASE + 0x65) #define P_VIDEO_STREAM_ID_2 CBUS_REG_ADDR(VIDEO_STREAM_ID_2) -#define VIDEO_STREAM_ID_3 0x16b5 +#define VIDEO_STREAM_ID_3 (STB_CBUS_BASE + 0xb5) #define P_VIDEO_STREAM_ID_3 CBUS_REG_ADDR(VIDEO_STREAM_ID_3) -#define AUDIO_STREAM_ID 0x1616 +#define AUDIO_STREAM_ID (STB_CBUS_BASE + 0x16) #define P_AUDIO_STREAM_ID CBUS_REG_ADDR(AUDIO_STREAM_ID) -#define AUDIO_STREAM_ID_2 0x1666 +#define AUDIO_STREAM_ID_2 (STB_CBUS_BASE + 0x66) #define P_AUDIO_STREAM_ID_2 CBUS_REG_ADDR(AUDIO_STREAM_ID_2) -#define AUDIO_STREAM_ID_3 0x16b6 +#define AUDIO_STREAM_ID_3 (STB_CBUS_BASE + 0xb6) #define P_AUDIO_STREAM_ID_3 CBUS_REG_ADDR(AUDIO_STREAM_ID_3) -#define SUB_STREAM_ID 0x1617 +#define SUB_STREAM_ID (STB_CBUS_BASE + 0x17) #define P_SUB_STREAM_ID CBUS_REG_ADDR(SUB_STREAM_ID) -#define SUB_STREAM_ID_2 0x1667 +#define SUB_STREAM_ID_2 (STB_CBUS_BASE + 0x67) #define P_SUB_STREAM_ID_2 CBUS_REG_ADDR(SUB_STREAM_ID_2) -#define SUB_STREAM_ID_3 0x16b7 +#define SUB_STREAM_ID_3 (STB_CBUS_BASE + 0xb7) #define P_SUB_STREAM_ID_3 CBUS_REG_ADDR(SUB_STREAM_ID_3) -#define OTHER_STREAM_ID 0x1618 +#define OTHER_STREAM_ID (STB_CBUS_BASE + 0x18) #define P_OTHER_STREAM_ID CBUS_REG_ADDR(OTHER_STREAM_ID) -#define OTHER_STREAM_ID_2 0x1668 +#define OTHER_STREAM_ID_2 (STB_CBUS_BASE + 0x68) #define P_OTHER_STREAM_ID_2 CBUS_REG_ADDR(OTHER_STREAM_ID_2) -#define OTHER_STREAM_ID_3 0x16b8 +#define OTHER_STREAM_ID_3 (STB_CBUS_BASE + 0xb8) #define P_OTHER_STREAM_ID_3 CBUS_REG_ADDR(OTHER_STREAM_ID_3) -#define PCR90K_CTL 0x1619 +#define PCR90K_CTL (STB_CBUS_BASE + 0x19) #define P_PCR90K_CTL CBUS_REG_ADDR(PCR90K_CTL) -#define PCR90K_CTL_2 0x1669 +#define PCR90K_CTL_2 (STB_CBUS_BASE + 0x69) #define P_PCR90K_CTL_2 CBUS_REG_ADDR(PCR90K_CTL_2) -#define PCR90K_CTL_3 0x16b9 +#define PCR90K_CTL_3 (STB_CBUS_BASE + 0xb9) #define P_PCR90K_CTL_3 CBUS_REG_ADDR(PCR90K_CTL_3) -#define PCR_DEMUX 0x161a +/*no used end*/ +#define PCR_DEMUX (STB_CBUS_BASE + 0x1a) #define P_PCR_DEMUX CBUS_REG_ADDR(PCR_DEMUX) -#define PCR_DEMUX_2 0x166a +#define PCR_DEMUX_2 (STB_CBUS_BASE + 0x6a) #define P_PCR_DEMUX_2 CBUS_REG_ADDR(PCR_DEMUX_2) -#define PCR_DEMUX_3 0x16ba +#define PCR_DEMUX_3 (STB_CBUS_BASE + 0xba) #define P_PCR_DEMUX_3 CBUS_REG_ADDR(PCR_DEMUX_3) -#define VIDEO_PTS_DEMUX 0x161b + +#define VIDEO_PTS_DEMUX (STB_CBUS_BASE + 0x1b) #define P_VIDEO_PTS_DEMUX CBUS_REG_ADDR(VIDEO_PTS_DEMUX) -#define VIDEO_PTS_DEMUX_2 0x166b +#define VIDEO_PTS_DEMUX_2 (STB_CBUS_BASE + 0x6b) #define P_VIDEO_PTS_DEMUX_2 CBUS_REG_ADDR(VIDEO_PTS_DEMUX_2) -#define VIDEO_PTS_DEMUX_3 0x16bb +#define VIDEO_PTS_DEMUX_3 (STB_CBUS_BASE + 0xbb) #define P_VIDEO_PTS_DEMUX_3 CBUS_REG_ADDR(VIDEO_PTS_DEMUX_3) -#define VIDEO_DTS_DEMUX 0x161c +/*no used*/ +#define VIDEO_DTS_DEMUX (STB_CBUS_BASE + 0x1c) #define P_VIDEO_DTS_DEMUX CBUS_REG_ADDR(VIDEO_DTS_DEMUX) -#define VIDEO_DTS_DEMUX_2 0x166c +#define VIDEO_DTS_DEMUX_2 (STB_CBUS_BASE + 0x6c) #define P_VIDEO_DTS_DEMUX_2 CBUS_REG_ADDR(VIDEO_DTS_DEMUX_2) -#define VIDEO_DTS_DEMUX_3 0x16bc +#define VIDEO_DTS_DEMUX_3 (STB_CBUS_BASE + 0xbc) #define P_VIDEO_DTS_DEMUX_3 CBUS_REG_ADDR(VIDEO_DTS_DEMUX_3) -#define AUDIO_PTS_DEMUX 0x161d +/*no used end*/ +#define AUDIO_PTS_DEMUX (STB_CBUS_BASE + 0x1d) #define P_AUDIO_PTS_DEMUX CBUS_REG_ADDR(AUDIO_PTS_DEMUX) -#define AUDIO_PTS_DEMUX_2 0x166d +#define AUDIO_PTS_DEMUX_2 (STB_CBUS_BASE + 0x6d) #define P_AUDIO_PTS_DEMUX_2 CBUS_REG_ADDR(AUDIO_PTS_DEMUX_2) -#define AUDIO_PTS_DEMUX_3 0x16bd +#define AUDIO_PTS_DEMUX_3 (STB_CBUS_BASE + 0xbd) #define P_AUDIO_PTS_DEMUX_3 CBUS_REG_ADDR(AUDIO_PTS_DEMUX_3) -#define SUB_PTS_DEMUX 0x161e +/*no used */ +#define SUB_PTS_DEMUX (STB_CBUS_BASE + 0x1e) #define P_SUB_PTS_DEMUX CBUS_REG_ADDR(SUB_PTS_DEMUX) -#define SUB_PTS_DEMUX_2 0x166e +#define SUB_PTS_DEMUX_2 (STB_CBUS_BASE + 0x6e) #define P_SUB_PTS_DEMUX_2 CBUS_REG_ADDR(SUB_PTS_DEMUX_2) -#define SUB_PTS_DEMUX_3 0x16be +#define SUB_PTS_DEMUX_3 (STB_CBUS_BASE + 0xbe) #define P_SUB_PTS_DEMUX_3 CBUS_REG_ADDR(SUB_PTS_DEMUX_3) -#define STB_PTS_DTS_STATUS 0x161f +/*no used end*/ +#define STB_PTS_DTS_STATUS (STB_CBUS_BASE + 0x1f) #define P_STB_PTS_DTS_STATUS CBUS_REG_ADDR(STB_PTS_DTS_STATUS) -#define STB_PTS_DTS_STATUS_2 0x166f +#define STB_PTS_DTS_STATUS_2 (STB_CBUS_BASE + 0x6f) #define P_STB_PTS_DTS_STATUS_2 CBUS_REG_ADDR(STB_PTS_DTS_STATUS_2) -#define STB_PTS_DTS_STATUS_3 0x16bf +#define STB_PTS_DTS_STATUS_3 (STB_CBUS_BASE + 0xbf) #define P_STB_PTS_DTS_STATUS_3 CBUS_REG_ADDR(STB_PTS_DTS_STATUS_3) -#define STB_DEBUG_INDEX 0x1620 + +/*no use*/ +#define STB_DEBUG_INDEX (STB_CBUS_BASE + 0x20) #define P_STB_DEBUG_INDEX CBUS_REG_ADDR(STB_DEBUG_INDEX) -#define STB_DEBUG_INDEX_2 0x1670 +#define STB_DEBUG_INDEX_2 (STB_CBUS_BASE + 0x70) #define P_STB_DEBUG_INDEX_2 CBUS_REG_ADDR(STB_DEBUG_INDEX_2) -#define STB_DEBUG_INDEX_3 0x16c0 +#define STB_DEBUG_INDEX_3 (STB_CBUS_BASE + 0xc0) #define P_STB_DEBUG_INDEX_3 CBUS_REG_ADDR(STB_DEBUG_INDEX_3) -#define STB_DEBUG_DATAUT_O 0x1621 +#define STB_DEBUG_DATAUT_O (STB_CBUS_BASE + 0x21) #define P_STB_DEBUG_DATAUT_O CBUS_REG_ADDR(STB_DEBUG_DATAUT_O) -#define STB_DEBUG_DATAUT_O_2 0x1671 +#define STB_DEBUG_DATAUT_O_2 (STB_CBUS_BASE + 0x71) #define P_STB_DEBUG_DATAUT_O_2 CBUS_REG_ADDR(STB_DEBUG_DATAUT_O_2) -#define STB_DEBUG_DATAUT_O_3 0x16c1 +#define STB_DEBUG_DATAUT_O_3 (STB_CBUS_BASE + 0xc1) #define P_STB_DEBUG_DATAUT_O_3 CBUS_REG_ADDR(STB_DEBUG_DATAUT_O_3) -#define STBM_CTL_O 0x1622 +/*no use end*/ + +#define STBM_CTL_O (STB_CBUS_BASE + 0x22) #define P_STBM_CTL_O CBUS_REG_ADDR(STBM_CTL_O) -#define STBM_CTL_O_2 0x1672 +#define STBM_CTL_O_2 (STB_CBUS_BASE + 0x72) #define P_STBM_CTL_O_2 CBUS_REG_ADDR(STBM_CTL_O_2) -#define STBM_CTL_O_3 0x16c2 +#define STBM_CTL_O_3 (STB_CBUS_BASE + 0xc2) #define P_STBM_CTL_O_3 CBUS_REG_ADDR(STBM_CTL_O_3) -#define STB_INT_STATUS 0x1623 +#define STB_INT_STATUS (STB_CBUS_BASE + 0x23) #define P_STB_INT_STATUS CBUS_REG_ADDR(STB_INT_STATUS) -#define STB_INT_STATUS_2 0x1673 +#define STB_INT_STATUS_2 (STB_CBUS_BASE + 0x73) #define P_STB_INT_STATUS_2 CBUS_REG_ADDR(STB_INT_STATUS_2) -#define STB_INT_STATUS_3 0x16c3 +#define STB_INT_STATUS_3 (STB_CBUS_BASE + 0xc3) #define P_STB_INT_STATUS_3 CBUS_REG_ADDR(STB_INT_STATUS_3) -#define DEMUX_ENDIAN 0x1624 +#define DEMUX_ENDIAN (STB_CBUS_BASE + 0x24) #define P_DEMUX_ENDIAN CBUS_REG_ADDR(DEMUX_ENDIAN) -#define DEMUX_ENDIAN_2 0x1674 +#define DEMUX_ENDIAN_2 (STB_CBUS_BASE + 0x74) #define P_DEMUX_ENDIAN_2 CBUS_REG_ADDR(DEMUX_ENDIAN_2) -#define DEMUX_ENDIAN_3 0x16c4 +#define DEMUX_ENDIAN_3 (STB_CBUS_BASE + 0xc4) #define P_DEMUX_ENDIAN_3 CBUS_REG_ADDR(DEMUX_ENDIAN_3) -#define TS_HIU_CTL 0x1625 +#define TS_HIU_CTL (STB_CBUS_BASE + 0x25) #define P_TS_HIU_CTL CBUS_REG_ADDR(TS_HIU_CTL) -#define TS_HIU_CTL_2 0x1675 +#define TS_HIU_CTL_2 (STB_CBUS_BASE + 0x75) #define P_TS_HIU_CTL_2 CBUS_REG_ADDR(TS_HIU_CTL_2) -#define TS_HIU_CTL_3 0x16c5 +#define TS_HIU_CTL_3 (STB_CBUS_BASE + 0xc5) #define P_TS_HIU_CTL_3 CBUS_REG_ADDR(TS_HIU_CTL_3) -#define SEC_BUFF_BASE 0x1626 + +#define SEC_BUFF_BASE (STB_CBUS_BASE + 0x26) #define P_SEC_BUFF_BASE CBUS_REG_ADDR(SEC_BUFF_BASE) -#define SEC_BUFF_BASE_2 0x1676 +#define SEC_BUFF_BASE_2 (STB_CBUS_BASE + 0x76) #define P_SEC_BUFF_BASE_2 CBUS_REG_ADDR(SEC_BUFF_BASE_2) -#define SEC_BUFF_BASE_3 0x16c6 +#define SEC_BUFF_BASE_3 (STB_CBUS_BASE + 0xc6) #define P_SEC_BUFF_BASE_3 CBUS_REG_ADDR(SEC_BUFF_BASE_3) -#define DEMUX_MEM_REQ_EN 0x1627 +#define DEMUX_MEM_REQ_EN (STB_CBUS_BASE + 0x27) #define P_DEMUX_MEM_REQ_EN CBUS_REG_ADDR(DEMUX_MEM_REQ_EN) -#define DEMUX_MEM_REQ_EN_2 0x1677 +#define DEMUX_MEM_REQ_EN_2 (STB_CBUS_BASE + 0x77) #define P_DEMUX_MEM_REQ_EN_2 CBUS_REG_ADDR(DEMUX_MEM_REQ_EN_2) -#define DEMUX_MEM_REQ_EN_3 0x16c7 +#define DEMUX_MEM_REQ_EN_3 (STB_CBUS_BASE + 0xc7) #define P_DEMUX_MEM_REQ_EN_3 CBUS_REG_ADDR(DEMUX_MEM_REQ_EN_3) -#define VIDEO_PDTS_WR_PTR 0x1628 + + +/*no use*/ +#define VIDEO_PDTS_WR_PTR (STB_CBUS_BASE + 0x28) #define P_VIDEO_PDTS_WR_PTR CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR) -#define VIDEO_PDTS_WR_PTR_2 0x1678 +#define VIDEO_PDTS_WR_PTR_2 (STB_CBUS_BASE + 0x78) #define P_VIDEO_PDTS_WR_PTR_2 CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR_2) -#define VIDEO_PDTS_WR_PTR_3 0x16c8 +#define VIDEO_PDTS_WR_PTR_3 (STB_CBUS_BASE + 0xc8) #define P_VIDEO_PDTS_WR_PTR_3 CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR_3) -#define AUDIO_PDTS_WR_PTR 0x1629 +#define AUDIO_PDTS_WR_PTR (STB_CBUS_BASE + 0x29) #define P_AUDIO_PDTS_WR_PTR CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR) -#define AUDIO_PDTS_WR_PTR_2 0x1679 +#define AUDIO_PDTS_WR_PTR_2 (STB_CBUS_BASE + 0x79) #define P_AUDIO_PDTS_WR_PTR_2 CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR_2) -#define AUDIO_PDTS_WR_PTR_3 0x16c9 +#define AUDIO_PDTS_WR_PTR_3 (STB_CBUS_BASE + 0xc9) #define P_AUDIO_PDTS_WR_PTR_3 CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR_3) -#define SUB_WR_PTR 0x162a +#define SUB_WR_PTR (STB_CBUS_BASE + 0x2a) #define P_SUB_WR_PTR CBUS_REG_ADDR(SUB_WR_PTR) -#define SUB_WR_PTR_2 0x167a +#define SUB_WR_PTR_2 (STB_CBUS_BASE + 0x7a) #define P_SUB_WR_PTR_2 CBUS_REG_ADDR(SUB_WR_PTR_2) -#define SUB_WR_PTR_3 0x16ca +#define SUB_WR_PTR_3 (STB_CBUS_BASE + 0xca) #define P_SUB_WR_PTR_3 CBUS_REG_ADDR(SUB_WR_PTR_3) -#define SB_START 0x162b +/*no use*/ + +#define SB_START (STB_CBUS_BASE + 0x2b) #define P_SB_START CBUS_REG_ADDR(SB_START) -#define SB_START_2 0x167b +#define SB_START_2 (STB_CBUS_BASE + 0x7b) #define P_SB_START_2 CBUS_REG_ADDR(SB_START_2) -#define SB_START_3 0x16cb +#define SB_START_3 (STB_CBUS_BASE + 0xcb) #define P_SB_START_3 CBUS_REG_ADDR(SB_START_3) -#define SB_LAST_ADDR 0x162c +#define SB_LAST_ADDR (STB_CBUS_BASE + 0x2c) #define P_SB_LAST_ADDR CBUS_REG_ADDR(SB_LAST_ADDR) -#define SB_LAST_ADDR_2 0x167c +#define SB_LAST_ADDR_2 (STB_CBUS_BASE + 0x7c) #define P_SB_LAST_ADDR_2 CBUS_REG_ADDR(SB_LAST_ADDR_2) -#define SB_LAST_ADDR_3 0x16cc +#define SB_LAST_ADDR_3 (STB_CBUS_BASE + 0xcc) #define P_SB_LAST_ADDR_3 CBUS_REG_ADDR(SB_LAST_ADDR_3) -#define SB_PES_WR_PTR 0x162d +#define SB_PES_WR_PTR (STB_CBUS_BASE + 0x2d) #define P_SB_PES_WR_PTR CBUS_REG_ADDR(SB_PES_WR_PTR) -#define SB_PES_WR_PTR_2 0x167d +#define SB_PES_WR_PTR_2 (STB_CBUS_BASE + 0x7d) #define P_SB_PES_WR_PTR_2 CBUS_REG_ADDR(SB_PES_WR_PTR_2) -#define SB_PES_WR_PTR_3 0x16cd +#define SB_PES_WR_PTR_3 (STB_CBUS_BASE + 0xcd) #define P_SB_PES_WR_PTR_3 CBUS_REG_ADDR(SB_PES_WR_PTR_3) -#define OTHER_WR_PTR 0x162e +#define OTHER_WR_PTR (STB_CBUS_BASE + 0x2e) #define P_OTHER_WR_PTR CBUS_REG_ADDR(OTHER_WR_PTR) -#define OTHER_WR_PTR_2 0x167e +#define OTHER_WR_PTR_2 (STB_CBUS_BASE + 0x7e) #define P_OTHER_WR_PTR_2 CBUS_REG_ADDR(OTHER_WR_PTR_2) -#define OTHER_WR_PTR_3 0x16ce +#define OTHER_WR_PTR_3 (STB_CBUS_BASE + 0xce) #define P_OTHER_WR_PTR_3 CBUS_REG_ADDR(OTHER_WR_PTR_3) -#define OB_START 0x162f + +#define OB_START (STB_CBUS_BASE + 0x2f) #define P_OB_START CBUS_REG_ADDR(OB_START) -#define OB_START_2 0x167f +#define OB_START_2 (STB_CBUS_BASE + 0x7f) #define P_OB_START_2 CBUS_REG_ADDR(OB_START_2) -#define OB_START_3 0x16cf +#define OB_START_3 (STB_CBUS_BASE + 0xcf) #define P_OB_START_3 CBUS_REG_ADDR(OB_START_3) -#define OB_LAST_ADDR 0x1630 +#define OB_LAST_ADDR (STB_CBUS_BASE + 0x30) #define P_OB_LAST_ADDR CBUS_REG_ADDR(OB_LAST_ADDR) -#define OB_LAST_ADDR_2 0x1680 +#define OB_LAST_ADDR_2 (STB_CBUS_BASE + 0x80) #define P_OB_LAST_ADDR_2 CBUS_REG_ADDR(OB_LAST_ADDR_2) -#define OB_LAST_ADDR_3 0x16d0 +#define OB_LAST_ADDR_3 (STB_CBUS_BASE + 0xd0) #define P_OB_LAST_ADDR_3 CBUS_REG_ADDR(OB_LAST_ADDR_3) -#define OB_PES_WR_PTR 0x1631 +#define OB_PES_WR_PTR (STB_CBUS_BASE + 0x31) #define P_OB_PES_WR_PTR CBUS_REG_ADDR(OB_PES_WR_PTR) -#define OB_PES_WR_PTR_2 0x1681 +#define OB_PES_WR_PTR_2 (STB_CBUS_BASE + 0x81) #define P_OB_PES_WR_PTR_2 CBUS_REG_ADDR(OB_PES_WR_PTR_2) -#define OB_PES_WR_PTR_3 0x16d1 +#define OB_PES_WR_PTR_3 (STB_CBUS_BASE + 0xd1) #define P_OB_PES_WR_PTR_3 CBUS_REG_ADDR(OB_PES_WR_PTR_3) -#define STB_INT_MASK 0x1632 +#define STB_INT_MASK (STB_CBUS_BASE + 0x32) #define P_STB_INT_MASK CBUS_REG_ADDR(STB_INT_MASK) -#define STB_INT_MASK_2 0x1682 +#define STB_INT_MASK_2 (STB_CBUS_BASE + 0x82) #define P_STB_INT_MASK_2 CBUS_REG_ADDR(STB_INT_MASK_2) -#define STB_INT_MASK_3 0x16d2 +#define STB_INT_MASK_3 (STB_CBUS_BASE + 0xd2) #define P_STB_INT_MASK_3 CBUS_REG_ADDR(STB_INT_MASK_3) -#define VIDEO_SPLICING_CTL 0x1633 +/*no used */ +#define VIDEO_SPLICING_CTL (STB_CBUS_BASE + 0x33) #define P_VIDEO_SPLICING_CTL CBUS_REG_ADDR(VIDEO_SPLICING_CTL) -#define VIDEO_SPLICING_CTL_2 0x1683 +#define VIDEO_SPLICING_CTL_2 (STB_CBUS_BASE + 0x83) #define P_VIDEO_SPLICING_CTL_2 CBUS_REG_ADDR(VIDEO_SPLICING_CTL_2) -#define VIDEO_SPLICING_CTL_3 0x16d3 +#define VIDEO_SPLICING_CTL_3 (STB_CBUS_BASE + 0xd3) #define P_VIDEO_SPLICING_CTL_3 CBUS_REG_ADDR(VIDEO_SPLICING_CTL_3) -#define AUDIO_SPLICING_CTL 0x1634 +#define AUDIO_SPLICING_CTL (STB_CBUS_BASE + 0x34) #define P_AUDIO_SPLICING_CTL CBUS_REG_ADDR(AUDIO_SPLICING_CTL) -#define AUDIO_SPLICING_CTL_2 0x1684 +#define AUDIO_SPLICING_CTL_2 (STB_CBUS_BASE + 0x84) #define P_AUDIO_SPLICING_CTL_2 CBUS_REG_ADDR(AUDIO_SPLICING_CTL_2) -#define AUDIO_SPLICING_CTL_3 0x16d4 +#define AUDIO_SPLICING_CTL_3 (STB_CBUS_BASE + 0xd4) #define P_AUDIO_SPLICING_CTL_3 CBUS_REG_ADDR(AUDIO_SPLICING_CTL_3) -#define TS_PACKAGE_BYTE_COUNT 0x1635 +#define TS_PACKAGE_BYTE_COUNT (STB_CBUS_BASE + 0x35) #define P_TS_PACKAGE_BYTE_COUNT \ CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT) -#define TS_PACKAGE_BYTE_COUNT_2 0x1685 +#define TS_PACKAGE_BYTE_COUNT_2 (STB_CBUS_BASE + 0x85) #define P_TS_PACKAGE_BYTE_COUNT_2 \ CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT_2) -#define TS_PACKAGE_BYTE_COUNT_3 0x16d5 +#define TS_PACKAGE_BYTE_COUNT_3 (STB_CBUS_BASE + 0xd5) #define P_TS_PACKAGE_BYTE_COUNT_3 \ CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT_3) -#define PES_STRONG_SYNC 0x1636 +/*no used end*/ + +#define PES_STRONG_SYNC (STB_CBUS_BASE + 0x36) #define P_PES_STRONG_SYNC CBUS_REG_ADDR(PES_STRONG_SYNC) -#define PES_STRONG_SYNC_2 0x1686 +#define PES_STRONG_SYNC_2 (STB_CBUS_BASE + 0x86) #define P_PES_STRONG_SYNC_2 CBUS_REG_ADDR(PES_STRONG_SYNC_2) -#define PES_STRONG_SYNC_3 0x16d6 +#define PES_STRONG_SYNC_3 (STB_CBUS_BASE + 0xd6) #define P_PES_STRONG_SYNC_3 CBUS_REG_ADDR(PES_STRONG_SYNC_3) -#define OM_DATA_RD_ADDR 0x1637 + +#define OM_DATA_RD_ADDR (STB_CBUS_BASE + 0x37) #define P_OM_DATA_RD_ADDR CBUS_REG_ADDR(OM_DATA_RD_ADDR) -#define OM_DATA_RD_ADDR_2 0x1687 +#define OM_DATA_RD_ADDR_2 (STB_CBUS_BASE + 0x87) #define P_OM_DATA_RD_ADDR_2 CBUS_REG_ADDR(OM_DATA_RD_ADDR_2) -#define OM_DATA_RD_ADDR_3 0x16d7 +#define OM_DATA_RD_ADDR_3 (STB_CBUS_BASE + 0xd7) #define P_OM_DATA_RD_ADDR_3 CBUS_REG_ADDR(OM_DATA_RD_ADDR_3) -#define OM_DATA_RD 0x1638 +#define OM_DATA_RD (STB_CBUS_BASE + 0x38) #define P_OM_DATA_RD CBUS_REG_ADDR(OM_DATA_RD) -#define OM_DATA_RD_2 0x1688 +#define OM_DATA_RD_2 (STB_CBUS_BASE + 0x88) #define P_OM_DATA_RD_2 CBUS_REG_ADDR(OM_DATA_RD_2) -#define OM_DATA_RD_3 0x16d8 +#define OM_DATA_RD_3 (STB_CBUS_BASE + 0xd8) #define P_OM_DATA_RD_3 CBUS_REG_ADDR(OM_DATA_RD_3) -#define SECTION_AUTO_STOP_3 0x1639 + +/*no used*/ + +#define SECTION_AUTO_STOP_3 (STB_CBUS_BASE + 0x39) #define P_SECTION_AUTO_STOP_3 CBUS_REG_ADDR(SECTION_AUTO_STOP_3) -#define SECTION_AUTO_STOP_3_2 0x1689 +#define SECTION_AUTO_STOP_3_2 (STB_CBUS_BASE + 0x89) #define P_SECTION_AUTO_STOP_3_2 \ CBUS_REG_ADDR(SECTION_AUTO_STOP_3_2) -#define SECTION_AUTO_STOP_3_3 0x16d9 +#define SECTION_AUTO_STOP_3_3 (STB_CBUS_BASE + 0xd9) #define P_SECTION_AUTO_STOP_3_3 \ CBUS_REG_ADDR(SECTION_AUTO_STOP_3_3) -#define SECTION_AUTO_STOP_2 0x163a +#define SECTION_AUTO_STOP_2 (STB_CBUS_BASE + 0x3a) #define P_SECTION_AUTO_STOP_2 \ CBUS_REG_ADDR(SECTION_AUTO_STOP_2) -#define SECTION_AUTO_STOP_2_2 0x168a +#define SECTION_AUTO_STOP_2_2 (STB_CBUS_BASE + 0x8a) #define P_SECTION_AUTO_STOP_2_2 \ CBUS_REG_ADDR(SECTION_AUTO_STOP_2_2) -#define SECTION_AUTO_STOP_2_3 0x16da +#define SECTION_AUTO_STOP_2_3 (STB_CBUS_BASE + 0xda) #define P_SECTION_AUTO_STOP_2_3 \ CBUS_REG_ADDR(SECTION_AUTO_STOP_2_3) -#define SECTION_AUTO_STOP_1 0x163b +#define SECTION_AUTO_STOP_1 (STB_CBUS_BASE + 0x3b) #define P_SECTION_AUTO_STOP_1 CBUS_REG_ADDR(SECTION_AUTO_STOP_1) -#define SECTION_AUTO_STOP_1_2 0x168b +#define SECTION_AUTO_STOP_1_2 (STB_CBUS_BASE + 0x8b) #define P_SECTION_AUTO_STOP_1_2 \ CBUS_REG_ADDR(SECTION_AUTO_STOP_1_2) -#define SECTION_AUTO_STOP_1_3 0x16db +#define SECTION_AUTO_STOP_1_3 (STB_CBUS_BASE + 0xdb) #define P_SECTION_AUTO_STOP_1_3 \ CBUS_REG_ADDR(SECTION_AUTO_STOP_1_3) -#define SECTION_AUTO_STOP_0 0x163c +#define SECTION_AUTO_STOP_0 (STB_CBUS_BASE + 0x3c) #define P_SECTION_AUTO_STOP_0 \ CBUS_REG_ADDR(SECTION_AUTO_STOP_0) -#define SECTION_AUTO_STOP_0_2 0x168c +#define SECTION_AUTO_STOP_0_2 (STB_CBUS_BASE + 0x8c) #define P_SECTION_AUTO_STOP_0_2 \ CBUS_REG_ADDR(SECTION_AUTO_STOP_0_2) -#define SECTION_AUTO_STOP_0_3 0x16dc +#define SECTION_AUTO_STOP_0_3 (STB_CBUS_BASE + 0xdc) #define P_SECTION_AUTO_STOP_0_3 \ CBUS_REG_ADDR(SECTION_AUTO_STOP_0_3) -#define DEMUX_CHANNEL_RESET 0x163d + +#define DEMUX_CHANNEL_RESET (STB_CBUS_BASE + 0x3d) #define P_DEMUX_CHANNEL_RESET \ CBUS_REG_ADDR(DEMUX_CHANNEL_RESET) -#define DEMUX_CHANNEL_RESET_2 0x168d +#define DEMUX_CHANNEL_RESET_2 (STB_CBUS_BASE + 0x8d) #define P_DEMUX_CHANNEL_RESET_2 \ CBUS_REG_ADDR(DEMUX_CHANNEL_RESET_2) -#define DEMUX_CHANNEL_RESET_3 0x16dd +#define DEMUX_CHANNEL_RESET_3 (STB_CBUS_BASE + 0xdd) #define P_DEMUX_CHANNEL_RESET_3 \ CBUS_REG_ADDR(DEMUX_CHANNEL_RESET_3) -#define DEMUX_SCRAMBLING_STATE 0x163e -#define DEMUX_SCRAMBLING_STATE_2 0x168e +/*no use end*/ +#define DEMUX_SCRAMBLING_STATE (STB_CBUS_BASE + 0x3e) +#define DEMUX_SCRAMBLING_STATE_2 (STB_CBUS_BASE + 0x8e) #define P_DEMUX_SCRAMBLING_STATE_2 \ CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE_2) -#define DEMUX_SCRAMBLING_STATE_3 0x16de +#define DEMUX_SCRAMBLING_STATE_3 (STB_CBUS_BASE + 0xde) #define P_DEMUX_SCRAMBLING_STATE_3 \ CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE_3) -#define DEMUX_CHANNEL_ACTIVITY 0x163f +#define DEMUX_CHANNEL_ACTIVITY (STB_CBUS_BASE + 0x3f) #define P_DEMUX_CHANNEL_ACTIVITY \ CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY) -#define DEMUX_CHANNEL_ACTIVITY_2 0x168f +#define DEMUX_CHANNEL_ACTIVITY_2 (STB_CBUS_BASE + 0x8f) #define P_DEMUX_CHANNEL_ACTIVITY_2 \ CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY_2) -#define DEMUX_CHANNEL_ACTIVITY_3 0x16df +#define DEMUX_CHANNEL_ACTIVITY_3 (STB_CBUS_BASE + 0xdf) #define P_DEMUX_CHANNEL_ACTIVITY_3 \ CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY_3) -#define DEMUX_STAMP_CTL 0x1640 + +/*no use*/ + +#define DEMUX_STAMP_CTL (STB_CBUS_BASE + 0x40) #define P_DEMUX_STAMP_CTL CBUS_REG_ADDR(DEMUX_STAMP_CTL) -#define DEMUX_STAMP_CTL_2 0x1690 +#define DEMUX_STAMP_CTL_2 (STB_CBUS_BASE + 0x90) #define P_DEMUX_STAMP_CTL_2 \ CBUS_REG_ADDR(DEMUX_STAMP_CTL_2) -#define DEMUX_STAMP_CTL_3 0x16e0 +#define DEMUX_STAMP_CTL_3 (STB_CBUS_BASE + 0xe0) #define P_DEMUX_STAMP_CTL_3 \ CBUS_REG_ADDR(DEMUX_STAMP_CTL_3) -#define DEMUX_VIDEO_STAMP_SYNC_0 0x1641 +#define DEMUX_VIDEO_STAMP_SYNC_0 (STB_CBUS_BASE + 0x41) #define P_DEMUX_VIDEO_STAMP_SYNC_0 \ CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0) -#define DEMUX_VIDEO_STAMP_SYNC_0_2 0x1691 +#define DEMUX_VIDEO_STAMP_SYNC_0_2 (STB_CBUS_BASE + 0x91) #define P_DEMUX_VIDEO_STAMP_SYNC_0_2 \ CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0_2) -#define DEMUX_VIDEO_STAMP_SYNC_0_3 0x16e1 +#define DEMUX_VIDEO_STAMP_SYNC_0_3 (STB_CBUS_BASE + 0xe1) #define P_DEMUX_VIDEO_STAMP_SYNC_0_3 \ CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0_3) -#define DEMUX_VIDEO_STAMP_SYNC_1 0x1642 +#define DEMUX_VIDEO_STAMP_SYNC_1 (STB_CBUS_BASE + 0x42) #define P_DEMUX_VIDEO_STAMP_SYNC_1 \ CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1) -#define DEMUX_VIDEO_STAMP_SYNC_1_2 0x1692 +#define DEMUX_VIDEO_STAMP_SYNC_1_2 (STB_CBUS_BASE + 0x92) #define P_DEMUX_VIDEO_STAMP_SYNC_1_2 \ CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1_2) -#define DEMUX_VIDEO_STAMP_SYNC_1_3 0x16e2 +#define DEMUX_VIDEO_STAMP_SYNC_1_3 (STB_CBUS_BASE + 0xe2) #define P_DEMUX_VIDEO_STAMP_SYNC_1_3 \ CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1_3) -#define DEMUX_AUDIO_STAMP_SYNC_0 0x1643 +#define DEMUX_AUDIO_STAMP_SYNC_0 (STB_CBUS_BASE + 0x43) #define P_DEMUX_AUDIO_STAMP_SYNC_0 \ CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0) -#define DEMUX_AUDIO_STAMP_SYNC_0_2 0x1693 +#define DEMUX_AUDIO_STAMP_SYNC_0_2 (STB_CBUS_BASE + 0x93) #define P_DEMUX_AUDIO_STAMP_SYNC_0_2 \ CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0_2) -#define DEMUX_AUDIO_STAMP_SYNC_0_3 0x16e3 +#define DEMUX_AUDIO_STAMP_SYNC_0_3 (STB_CBUS_BASE + 0xe3) #define P_DEMUX_AUDIO_STAMP_SYNC_0_3 \ CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0_3) -#define DEMUX_AUDIO_STAMP_SYNC_1 0x1644 +#define DEMUX_AUDIO_STAMP_SYNC_1 (STB_CBUS_BASE + 0x44) #define P_DEMUX_AUDIO_STAMP_SYNC_1 \ CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1) -#define DEMUX_AUDIO_STAMP_SYNC_1_2 0x1694 +#define DEMUX_AUDIO_STAMP_SYNC_1_2 (STB_CBUS_BASE + 0x94) #define P_DEMUX_AUDIO_STAMP_SYNC_1_2 \ CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1_2) -#define DEMUX_AUDIO_STAMP_SYNC_1_3 0x16e4 +#define DEMUX_AUDIO_STAMP_SYNC_1_3 (STB_CBUS_BASE + 0xe4) #define P_DEMUX_AUDIO_STAMP_SYNC_1_3 \ CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1_3) -#define DEMUX_SECTION_RESET 0x1645 +#define DEMUX_SECTION_RESET (STB_CBUS_BASE + 0x45) #define P_DEMUX_SECTION_RESET CBUS_REG_ADDR(DEMUX_SECTION_RESET) -#define DEMUX_SECTION_RESET_2 0x1695 +#define DEMUX_SECTION_RESET_2 (STB_CBUS_BASE + 0x95) #define P_DEMUX_SECTION_RESET_2 \ CBUS_REG_ADDR(DEMUX_SECTION_RESET_2) -#define DEMUX_SECTION_RESET_3 0x16e5 +#define DEMUX_SECTION_RESET_3 (STB_CBUS_BASE + 0xe5) #define P_DEMUX_SECTION_RESET_3 \ CBUS_REG_ADDR(DEMUX_SECTION_RESET_3) -#define EFUSE_CNTL0 0x0 -#define P_EFUSE_CNTL0 SECBUS_REG_ADDR(EFUSE_CNTL0) -#define EFUSE_CNTL1 0x1 -#define P_EFUSE_CNTL1 SECBUS_REG_ADDR(EFUSE_CNTL1) -#define EFUSE_CNTL2 0x2 -#define P_EFUSE_CNTL2 SECBUS_REG_ADDR(EFUSE_CNTL2) -#define EFUSE_CNTL3 0x3 -#define P_EFUSE_CNTL3 SECBUS_REG_ADDR(EFUSE_CNTL3) -#define EFUSE_CNTL4 0x4 -#define P_EFUSE_CNTL4 SECBUS_REG_ADDR(EFUSE_CNTL4) -#define AO_SECURE_REG0 0x00 -#define P_AO_SECURE_REG0 SECBUS2_REG_ADDR(AO_SECURE_REG0) -#define AO_SECURE_REG1 0x01 -#define P_AO_SECURE_REG1 SECBUS2_REG_ADDR(AO_SECURE_REG1) -#define AO_SECURE_REG2 0x02 -#define P_AO_SECURE_REG2 SECBUS2_REG_ADDR(AO_SECURE_REG2) -#define SEC_BLKMV_AES_REG0 0x00 -#define P_SEC_BLKMV_AES_REG0 SECBUS3_REG_ADDR(SEC_BLKMV_AES_REG0) -#define SEC_BLKMV_AES_W0 0x01 -#define P_SEC_BLKMV_AES_W0 SECBUS3_REG_ADDR(SEC_BLKMV_AES_W0) -#define SEC_BLKMV_AES_W1 0x02 -#define P_SEC_BLKMV_AES_W1 SECBUS3_REG_ADDR(SEC_BLKMV_AES_W1) -#define SEC_BLKMV_AES_W2 0x03 -#define P_SEC_BLKMV_AES_W2 SECBUS3_REG_ADDR(SEC_BLKMV_AES_W2) -#define SEC_BLKMV_AES_W3 0x04 -#define P_SEC_BLKMV_AES_W3 SECBUS3_REG_ADDR(SEC_BLKMV_AES_W3) -#define SEC_BLKMV_AES_R0 0x05 -#define P_SEC_BLKMV_AES_R0 SECBUS3_REG_ADDR(SEC_BLKMV_AES_R0) -#define SEC_BLKMV_AES_R1 0x06 -#define P_SEC_BLKMV_AES_R1 SECBUS3_REG_ADDR(SEC_BLKMV_AES_R1) -#define SEC_BLKMV_AES_R2 0x07 -#define P_SEC_BLKMV_AES_R2 SECBUS3_REG_ADDR(SEC_BLKMV_AES_R2) -#define SEC_BLKMV_AES_R3 0x08 -#define P_SEC_BLKMV_AES_R3 SECBUS3_REG_ADDR(SEC_BLKMV_AES_R3) -#define SEC_BLKMV_TDES_LAST_IV_LO 0x09 -#define P_SEC_BLKMV_TDES_LAST_IV_LO \ - SECBUS3_REG_ADDR(SEC_BLKMV_TDES_LAST_IV_LO) -#define SEC_BLKMV_TDES_LAST_IV_HI 0x0a -#define P_SEC_BLKMV_TDES_LAST_IV_HI \ - SECBUS3_REG_ADDR(SEC_BLKMV_TDES_LAST_IV_HI) -#define SEC_BLKMV_AES_IV_0 0x0b -#define P_SEC_BLKMV_AES_IV_0 SECBUS3_REG_ADDR(SEC_BLKMV_AES_IV_0) -#define SEC_BLKMV_AES_IV_1 0x0c -#define P_SEC_BLKMV_AES_IV_1 SECBUS3_REG_ADDR(SEC_BLKMV_AES_IV_1) -#define SEC_BLKMV_AES_IV_2 0x0d -#define P_SEC_BLKMV_AES_IV_2 SECBUS3_REG_ADDR(SEC_BLKMV_AES_IV_2) -#define SEC_BLKMV_AES_IV_3 0x0e -#define P_SEC_BLKMV_AES_IV_3 SECBUS3_REG_ADDR(SEC_BLKMV_AES_IV_3) -/*add from M8M2*/ -#define SEC_BLKMV_AES_KEY_0 0x10 -#define P_SEC_BLKMV_AES_KEY_0 SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_0) -#define SEC_BLKMV_AES_KEY_1 0x11 -#define P_SEC_BLKMV_AES_KEY_1 SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_1) -#define SEC_BLKMV_AES_KEY_2 0x12 -#define P_SEC_BLKMV_AES_KEY_2 SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_2) -#define SEC_BLKMV_AES_KEY_3 0x13 -#define P_SEC_BLKMV_AES_KEY_3 SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_3) -#define SEC_BLKMV_AES_KEY_4 0x14 -#define P_SEC_BLKMV_AES_KEY_4 SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_4) -#define SEC_BLKMV_AES_KEY_5 0x15 -#define P_SEC_BLKMV_AES_KEY_5 SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_5) -#define SEC_BLKMV_AES_KEY_6 0x16 -#define P_SEC_BLKMV_AES_KEY_6 SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_6) -#define SEC_BLKMV_AES_KEY_7 0x17 -#define P_SEC_BLKMV_AES_KEY_7 SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_7) -#define SEC_BLKMV_THREAD_TABLE_START0 0x18 -#define P_SEC_BLKMV_THREAD_TABLE_START0 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_START0) -#define SEC_BLKMV_THREAD_TABLE_CURR0 0x19 -#define P_SEC_BLKMV_THREAD_TABLE_CURR0 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_CURR0) -#define SEC_BLKMV_THREAD_TABLE_END0 0x1a -#define P_SEC_BLKMV_THREAD_TABLE_END0 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_END0) -#define SEC_BLKMV_THREAD_TABLE_START1 0x1b -#define P_SEC_BLKMV_THREAD_TABLE_START1 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_START1) -#define SEC_BLKMV_THREAD_TABLE_CURR1 0x1c -#define P_SEC_BLKMV_THREAD_TABLE_CURR1 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_CURR1) -#define SEC_BLKMV_THREAD_TABLE_END1 0x1d -#define P_SEC_BLKMV_THREAD_TABLE_END1 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_END1) -#define SEC_BLKMV_THREAD_TABLE_START2 0x1e -#define P_SEC_BLKMV_THREAD_TABLE_START2 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_START2) -#define SEC_BLKMV_THREAD_TABLE_CURR2 0x1f -#define P_SEC_BLKMV_THREAD_TABLE_CURR2 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_CURR2) -#define SEC_BLKMV_THREAD_TABLE_END2 0x20 -#define P_SEC_BLKMV_THREAD_TABLE_END2 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_END2) -#define SEC_BLKMV_THREAD_TABLE_START3 0x21 -#define P_SEC_BLKMV_THREAD_TABLE_START3 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_START3) -#define SEC_BLKMV_THREAD_TABLE_CURR3 0x22 -#define P_SEC_BLKMV_THREAD_TABLE_CURR3 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_CURR3) -#define SEC_BLKMV_THREAD_TABLE_END3 0x23 -#define P_SEC_BLKMV_THREAD_TABLE_END3 \ - SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_END3) -#define SEC_BLKMV_GEN_REG0 0x24 -#define P_SEC_BLKMV_GEN_REG0 SECBUS3_REG_ADDR(SEC_BLKMV_GEN_REG0) +/*no use end*/ + +/*from c_stb_define.h*/ +#define COMM_DESC_2_CTL (STB_CBUS_BASE + 0xff) /*0x16ff*/ + +#define STB_OM_CTL \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x22) /* 0x1622*/ +#define STB_OM_CTL_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x22) /* 0x1672*/ +#define STB_OM_CTL_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x22) /* 0x16c2*/ + +#define DEMUX_INPUT_TIMEOUT_C \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x46) /* 0x1646*/ +#define DEMUX_INPUT_TIMEOUT_C_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x46) /* 0x1696*/ +#define DEMUX_INPUT_TIMEOUT_C_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x46) /* 0x16e6*/ +/* bit[31] - no_match_reset_timeout_disable*/ +/* bit[30:0] input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-count*/ +#define DEMUX_INPUT_TIMEOUT \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x47) /* 0x1647*/ +#define DEMUX_INPUT_TIMEOUT_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x47) /* 0x1697*/ +#define DEMUX_INPUT_TIMEOUT_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x47) /* 0x16e7*/ + +/* bit[31:0] - channel_packet_count_disable*/ +#define DEMUX_PACKET_COUNT_C \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x48) /* 0x1648*/ +#define DEMUX_PACKET_COUNT_C_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x48) /* 0x1698*/ +#define DEMUX_PACKET_COUNT_C_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x48) /* 0x16e8*/ +/* bit[31] - no_match_packet_count_disable*/ +/* bit[30:0] input_packet_count*/ +#define DEMUX_PACKET_COUNT \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x49) /* 0x1649*/ +#define DEMUX_PACKET_COUNT_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x49) /* 0x1699*/ +#define DEMUX_PACKET_COUNT_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x49) /* 0x16e9*/ + +/* bit[31:0] channel_record_enable*/ +#define DEMUX_CHAN_RECORD_EN \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4a) /* 0x164a*/ +#define DEMUX_CHAN_RECORD_EN_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4a) /* 0x169a*/ +#define DEMUX_CHAN_RECORD_EN_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4a) /* 0x16ea*/ + +/* bit[31:0] channel_process_enable*/ +#define DEMUX_CHAN_PROCESS_EN \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4b) /* 0x164b*/ +#define DEMUX_CHAN_PROCESS_EN_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4b) /* 0x169b*/ +#define DEMUX_CHAN_PROCESS_EN_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4b) /* 0x16eb*/ + +/* bit[31:24] small_sec_size ((n+1) * 256 Bytes)*/ +/* bit[23:16] small_sec_rd_ptr */ +/* bit[15:8] small_sec_wr_ptr */ +/* bit[7:2] reserved*/ +/* bit[1] small_sec_wr_ptr_wr_enable*/ +/* bit[0] small_section_enable*/ +#define DEMUX_SMALL_SEC_CTL \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4c) /* 0x164c*/ +#define DEMUX_SMALL_SEC_CTL_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4c) /* 0x169c*/ +#define DEMUX_SMALL_SEC_CTL_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4c) /* 0x16ec*/ +/* bit[31:0] small_sec_start_addr*/ +#define DEMUX_SMALL_SEC_ADDR \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4d) /* 0x164d*/ +#define DEMUX_SMALL_SEC_ADDR_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4d) /* 0x169d*/ +#define DEMUX_SMALL_SEC_ADDR_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4d) /* 0x16ed*/ + #endif diff --git a/drivers/amlogic/media_modules/stream_input/parser/tsdemux.c b/drivers/amlogic/media_modules/stream_input/parser/tsdemux.c index 21833b267d87..261eb557e680 100644 --- a/drivers/amlogic/media_modules/stream_input/parser/tsdemux.c +++ b/drivers/amlogic/media_modules/stream_input/parser/tsdemux.c @@ -69,11 +69,7 @@ static DEFINE_SPINLOCK(demux_ops_lock); static int enable_demux_driver(void) { -#ifdef ENABLE_DEMUX_DRIVER return demux_ops ? 1 : 0; -#else - return 0; -#endif } void tsdemux_set_ops(struct tsdemux_ops *ops)