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arm64: dts: rockchip: rk3568: set 24M ref clk for naneng combphy

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Change-Id: Ie17a4bf16bd47e1e9fd6529873492ebcd11b5fae
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
William Wu
2020-11-10 21:19:04 +08:00
committed by Tao Huang
parent 847bb599e2
commit 762245fafd
1 changed files with 7 additions and 1 deletions
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8
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -2226,6 +2226,8 @@
#phy-cells = <1>;
clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>;
clock-names = "refclk", "apbclk";
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
assigned-clock-rates = <24000000>;
resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&pipegrf>;
@@ -2239,7 +2241,9 @@
#phy-cells = <1>;
clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>;
clock-names = "refclk", "apbclk";
resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
assigned-clock-rates = <24000000>;
resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
@@ -2252,6 +2256,8 @@
#phy-cells = <1>;
clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>;
clock-names = "refclk", "apbclk";
assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
assigned-clock-rates = <24000000>;
resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&pipegrf>;