From 762245fafda3f9a371fc5ab915539975ea04e434 Mon Sep 17 00:00:00 2001 From: William Wu Date: Tue, 10 Nov 2020 21:19:04 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3568: set 24M ref clk for naneng combphy Change-Id: Ie17a4bf16bd47e1e9fd6529873492ebcd11b5fae Signed-off-by: William Wu --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 6318b7e14ccf..282ba2e83222 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -2226,6 +2226,8 @@ #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>; clock-names = "refclk", "apbclk"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <24000000>; resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; reset-names = "combphy-apb", "combphy"; rockchip,pipe-grf = <&pipegrf>; @@ -2239,7 +2241,9 @@ #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>; clock-names = "refclk", "apbclk"; - resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <24000000>; + resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; reset-names = "combphy-apb", "combphy"; rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf1>; @@ -2252,6 +2256,8 @@ #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>; clock-names = "refclk", "apbclk"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <24000000>; resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; reset-names = "combphy-apb", "combphy"; rockchip,pipe-grf = <&pipegrf>;