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vdin: add new interface for passing dma-buf to vdin [1/1]
PD#TV-3863 Problem: gpu cann't get vdin buf directly Solution: vdin write data to the addr passed by upper layer Verify: verified by t962x2_x301 Change-Id: I495b78c419e10a6dacb9b9f29c0f8e87339ac195 Signed-off-by: zhiwei.yuan <zhiwei.yuan@amlogic.com>
This commit is contained in:
@@ -99,8 +99,10 @@
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vdin1_cma_reserved:linux,vdin1_cma {
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vdin1_cma_reserved:linux,vdin1_cma {
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compatible = "shared-dma-pool";
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compatible = "shared-dma-pool";
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reusable;
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reusable;
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/* 1920x1080x2x4 =16 M */
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/*keystone need 4 buffers,each has 1920*1080*3
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size = <0x1400000>;
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*for keystone, change to 0x1800000(24M)
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*/
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size = <0x1400000>;/*20M*/
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alignment = <0x400000>;
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alignment = <0x400000>;
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};
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};
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@@ -114,8 +114,10 @@
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vdin1_cma_reserved:linux,vdin1_cma {
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vdin1_cma_reserved:linux,vdin1_cma {
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compatible = "shared-dma-pool";
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compatible = "shared-dma-pool";
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reusable;
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reusable;
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/* 1920x1080x2x4 =16 M */
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/*keystone need 4 buffers,each has 1920*1080*3
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size = <0x1400000>;
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*for keystone, change to 0x1800000(24M)
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*/
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size = <0x1400000>;/*20M*/
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alignment = <0x400000>;
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alignment = <0x400000>;
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};
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};
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@@ -122,8 +122,10 @@
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vdin1_cma_reserved:linux,vdin1_cma {
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vdin1_cma_reserved:linux,vdin1_cma {
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compatible = "shared-dma-pool";
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compatible = "shared-dma-pool";
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reusable;
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reusable;
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/* 1920x1080x2x4 =16 M */
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/*keystone need 4 buffers,each has 1920*1080*3
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size = <0x1400000>;
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*for keystone, change to 0x1800000(24M)
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*/
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size = <0x1400000>;/*20M*/
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alignment = <0x400000>;
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alignment = <0x400000>;
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};
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};
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@@ -125,8 +125,10 @@
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vdin1_cma_reserved:linux,vdin1_cma {
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vdin1_cma_reserved:linux,vdin1_cma {
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compatible = "shared-dma-pool";
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compatible = "shared-dma-pool";
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reusable;
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reusable;
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/* 1920x1080x2x4 =16 M */
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/*keystone need 4 buffers,each has 1920*1080*3
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size = <0x1400000>;
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*for keystone, change to 0x1800000(24M)
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*/
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size = <0x1400000>;/*20M*/
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alignment = <0x400000>;
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alignment = <0x400000>;
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alloc-ranges = <0x30000000 0x10000000>;
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alloc-ranges = <0x30000000 0x10000000>;
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};
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};
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@@ -124,8 +124,10 @@
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vdin1_cma_reserved:linux,vdin1_cma {
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vdin1_cma_reserved:linux,vdin1_cma {
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compatible = "shared-dma-pool";
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compatible = "shared-dma-pool";
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reusable;
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reusable;
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/* 1920x1080x2x4 =16 M */
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/*keystone need 4 buffers,each has 1920*1080*3
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size = <0x1400000>;
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*for keystone, change to 0x1800000(24M)
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*/
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size = <0x1400000>;/*20M*/
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alignment = <0x400000>;
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alignment = <0x400000>;
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};
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};
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@@ -121,8 +121,10 @@
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vdin1_cma_reserved:linux,vdin1_cma {
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vdin1_cma_reserved:linux,vdin1_cma {
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compatible = "shared-dma-pool";
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compatible = "shared-dma-pool";
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reusable;
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reusable;
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/* 1920x1080x2x4 =16 M */
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/*keystone need 4 buffers,each has 1920*1080*3
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size = <0x0 0x1400000>;
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*for keystone, change to 0x1800000(24M)
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*/
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size = <0x0 0x1400000>;/*20M*/
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alignment = <0x0 0x400000>;
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alignment = <0x0 0x400000>;
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};
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};
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@@ -123,8 +123,10 @@
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vdin1_cma_reserved:linux,vdin1_cma {
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vdin1_cma_reserved:linux,vdin1_cma {
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compatible = "shared-dma-pool";
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compatible = "shared-dma-pool";
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reusable;
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reusable;
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/* 1920x1080x2x4 =16 M */
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/*keystone need 4 buffers,each has 1920*1080*3
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size = <0x0 0x1400000>;
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*for keystone, change to 0x1800000(24M)
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*/
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size = <0x0 0x1400000>;/*20M*/
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alignment = <0x0 0x400000>;
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alignment = <0x0 0x400000>;
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alloc-ranges = <0x0 0x30000000 0x0 0x10000000>;
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alloc-ranges = <0x0 0x30000000 0x0 0x10000000>;
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};
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};
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@@ -121,8 +121,10 @@
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vdin1_cma_reserved:linux,vdin1_cma {
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vdin1_cma_reserved:linux,vdin1_cma {
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compatible = "shared-dma-pool";
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compatible = "shared-dma-pool";
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reusable;
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reusable;
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/* 1920x1080x2x4 =16 M */
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/*keystone need 4 buffers,each has 1920*1080*3
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size = <0x0 0x1400000>;
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*for keystone, change to 0x1800000(24M)
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*/
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size = <0x0 0x1400000>;/*20M*/
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alignment = <0x0 0x400000>;
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alignment = <0x0 0x400000>;
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};
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};
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@@ -332,6 +332,23 @@ void vdin_canvas_auto_config(struct vdin_dev_s *devp)
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pr_err("\nvdin%d canvas_max_num %d less than vfmem_max_cnt %d\n",
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pr_err("\nvdin%d canvas_max_num %d less than vfmem_max_cnt %d\n",
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devp->index, devp->canvas_max_num, devp->vfmem_max_cnt);
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devp->index, devp->canvas_max_num, devp->vfmem_max_cnt);
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}
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}
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if (devp->set_canvas_manual == 1) {
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for (i = 0; i < 4; i++) {
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canvas_id =
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vdin_canvas_ids[devp->index][i * canvas_step];
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canvas_addr = vdin_set_canvas_addr[i].paddr;
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canvas_config(canvas_id, canvas_addr,
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devp->canvas_w, devp->canvas_h,
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CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
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pr_info("canvas index=%d- %3d: 0x%lx-0x%lx %ux%u\n",
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i, canvas_id, canvas_addr,
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canvas_addr + devp->canvas_max_size,
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devp->canvas_w, devp->canvas_h);
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}
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return;
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}
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if ((devp->cma_config_en != 1) || !(devp->cma_config_flag & 0x100)) {
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if ((devp->cma_config_en != 1) || !(devp->cma_config_flag & 0x100)) {
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/*use_reserved_mem or alloc_from_contiguous*/
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/*use_reserved_mem or alloc_from_contiguous*/
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devp->mem_start = roundup(devp->mem_start, devp->canvas_align);
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devp->mem_start = roundup(devp->mem_start, devp->canvas_align);
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@@ -503,9 +520,25 @@ unsigned int vdin_cma_alloc(struct vdin_dev_s *devp)
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devp->vfmem_size = PAGE_ALIGN(mem_size) + dolby_size_byte;
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devp->vfmem_size = PAGE_ALIGN(mem_size) + dolby_size_byte;
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devp->vfmem_size = (devp->vfmem_size/PAGE_SIZE + 1)*PAGE_SIZE;
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devp->vfmem_size = (devp->vfmem_size/PAGE_SIZE + 1)*PAGE_SIZE;
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if (devp->set_canvas_manual == 1) {
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for (i = 0; i < VDIN_CANVAS_MAX_CNT; i++) {
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if (vdin_set_canvas_addr[i].dmabuff == NULL)
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break;
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vdin_set_canvas_addr[i].paddr =
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roundup(vdin_set_canvas_addr[i].paddr,
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devp->canvas_align);
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}
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devp->canvas_max_num = max_buffer_num = i;
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devp->vfmem_max_cnt = max_buffer_num;
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}
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mem_size = PAGE_ALIGN(mem_size) * max_buffer_num +
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mem_size = PAGE_ALIGN(mem_size) * max_buffer_num +
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dolby_size_byte * max_buffer_num;
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dolby_size_byte * max_buffer_num;
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mem_size = (mem_size/PAGE_SIZE + 1)*PAGE_SIZE;
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mem_size = (mem_size/PAGE_SIZE + 1)*PAGE_SIZE;
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if (mem_size > devp->cma_mem_size) {
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if (mem_size > devp->cma_mem_size) {
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mem_size = devp->cma_mem_size;
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mem_size = devp->cma_mem_size;
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pr_err("\nvdin%d cma_mem_size is not enough!!!\n", devp->index);
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pr_err("\nvdin%d cma_mem_size is not enough!!!\n", devp->index);
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@@ -750,7 +750,7 @@ static void vdin_set_meas_mux(unsigned int offset, enum tvin_port_e port_,
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b.BT_PATH_GPIO_B:gxtvbb & gxbb
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b.BT_PATH_GPIO_B:gxtvbb & gxbb
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c.txl and txlx don't support bt656
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c.txl and txlx don't support bt656
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*/
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*/
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void vdin_set_top(unsigned int offset,
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void vdin_set_top(struct vdin_dev_s *devp, unsigned int offset,
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enum tvin_port_e port,
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enum tvin_port_e port,
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enum tvin_color_fmt_e input_cfmt, unsigned int h,
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enum tvin_color_fmt_e input_cfmt, unsigned int h,
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enum bt_path_e bt_path)
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enum bt_path_e bt_path)
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@@ -873,6 +873,7 @@ void vdin_set_top(unsigned int offset,
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vdin_mux = VDIN_MUX_NULL;
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vdin_mux = VDIN_MUX_NULL;
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break;
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break;
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}
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}
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switch (input_cfmt) {
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switch (input_cfmt) {
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case TVIN_YVYU422:
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case TVIN_YVYU422:
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vdin_data_bus_1 = VDIN_MAP_RCR;
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vdin_data_bus_1 = VDIN_MAP_RCR;
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@@ -888,6 +889,14 @@ void vdin_set_top(unsigned int offset,
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vdin_data_bus_1 = VDIN_MAP_RCR;
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vdin_data_bus_1 = VDIN_MAP_RCR;
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vdin_data_bus_2 = VDIN_MAP_Y_G;
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vdin_data_bus_2 = VDIN_MAP_Y_G;
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break;
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break;
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case TVIN_RGB444:
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/*RGB mapping*/
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if (devp->set_canvas_manual == 1) {
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vdin_data_bus_0 = VDIN_MAP_RCR;
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vdin_data_bus_1 = VDIN_MAP_BPB;
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vdin_data_bus_2 = VDIN_MAP_Y_G;
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}
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break;
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default:
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default:
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break;
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break;
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}
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}
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@@ -1996,7 +2005,14 @@ static inline void vdin_set_wr_ctrl(struct vdin_dev_s *devp,
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VDIN_WRCTRLREG_PAUSE_BIT, 1);
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VDIN_WRCTRLREG_PAUSE_BIT, 1);
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/* swap the 2 64bits word in 128 words */
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/* swap the 2 64bits word in 128 words */
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/*if (is_meson_gxbb_cpu())*/
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/*if (is_meson_gxbb_cpu())*/
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wr_bits(offset, VDIN_WR_CTRL, 1, 19, 1);
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if (devp->set_canvas_manual == 1) {
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/*not swap 2 64bits words in 128 words */
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wr_bits(offset, VDIN_WR_CTRL, 0, 19, 1);
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/*little endian*/
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wr_bits(offset, VDIN_WR_H_START_END, 1, 30, 1);
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} else
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wr_bits(offset, VDIN_WR_CTRL, 1, 19, 1);
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}
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}
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void vdin_set_wr_ctrl_vsync(struct vdin_dev_s *devp,
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void vdin_set_wr_ctrl_vsync(struct vdin_dev_s *devp,
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unsigned int offset, enum vdin_format_convert_e format_convert,
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unsigned int offset, enum vdin_format_convert_e format_convert,
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@@ -2577,7 +2593,7 @@ void vdin_set_all_regs(struct vdin_dev_s *devp)
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devp->color_depth_mode, devp->source_bitdepth);
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devp->color_depth_mode, devp->source_bitdepth);
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/* top sub-module */
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/* top sub-module */
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vdin_set_top(devp->addr_offset, devp->parm.port,
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vdin_set_top(devp, devp->addr_offset, devp->parm.port,
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devp->prop.color_format, devp->h_active,
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devp->prop.color_format, devp->h_active,
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devp->bt_path);
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devp->bt_path);
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@@ -2585,7 +2601,6 @@ void vdin_set_all_regs(struct vdin_dev_s *devp)
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vdin_set_meas_mux(devp->addr_offset, devp->parm.port,
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vdin_set_meas_mux(devp->addr_offset, devp->parm.port,
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devp->bt_path);
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devp->bt_path);
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}
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}
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static void vdin_delay_line(unsigned short num, unsigned int offset)
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static void vdin_delay_line(unsigned short num, unsigned int offset)
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@@ -2969,6 +2984,18 @@ unsigned int vdin_get_field_type(unsigned int offset)
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{
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{
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return rd_bits(offset, VDIN_COM_STATUS0, 0, 1);
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return rd_bits(offset, VDIN_COM_STATUS0, 0, 1);
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}
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}
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bool vdin_check_vdi6_afifo_overflow(unsigned int offset)
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{
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return rd_bits(offset, VDIN_COM_STATUS2, 15, 1);
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}
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void vdin_clear_vdi6_afifo_overflow_flg(unsigned int offset)
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{
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wr_bits(offset, VDIN_ASFIFO_CTRL3, 0x1, 1, 1);
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wr_bits(offset, VDIN_ASFIFO_CTRL3, 0x0, 1, 1);
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}
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static unsigned int vdin_reset_flag;
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static unsigned int vdin_reset_flag;
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inline int vdin_vsync_reset_mif(int index)
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inline int vdin_vsync_reset_mif(int index)
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{
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{
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@@ -145,6 +145,8 @@ extern void vdin_hw_enable(unsigned int offset);
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extern void vdin_hw_disable(unsigned int offset);
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extern void vdin_hw_disable(unsigned int offset);
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extern unsigned int vdin_get_field_type(unsigned int offset);
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extern unsigned int vdin_get_field_type(unsigned int offset);
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extern int vdin_vsync_reset_mif(int index);
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extern int vdin_vsync_reset_mif(int index);
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extern bool vdin_check_vdi6_afifo_overflow(unsigned int offset);
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extern void vdin_clear_vdi6_afifo_overflow_flg(unsigned int offset);
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extern void vdin_set_cutwin(struct vdin_dev_s *devp);
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extern void vdin_set_cutwin(struct vdin_dev_s *devp);
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extern void vdin_set_decimation(struct vdin_dev_s *devp);
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extern void vdin_set_decimation(struct vdin_dev_s *devp);
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extern void vdin_fix_nonstd_vsync(struct vdin_dev_s *devp);
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extern void vdin_fix_nonstd_vsync(struct vdin_dev_s *devp);
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@@ -187,7 +189,7 @@ extern void vdin_dolby_addr_alloc(struct vdin_dev_s *devp, unsigned int size);
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extern void vdin_dolby_addr_release(struct vdin_dev_s *devp, unsigned int size);
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extern void vdin_dolby_addr_release(struct vdin_dev_s *devp, unsigned int size);
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extern int vdin_event_cb(int type, void *data, void *op_arg);
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extern int vdin_event_cb(int type, void *data, void *op_arg);
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extern void vdin_hdmiin_patch(struct vdin_dev_s *devp);
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extern void vdin_hdmiin_patch(struct vdin_dev_s *devp);
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extern void vdin_set_top(unsigned int offset,
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extern void vdin_set_top(struct vdin_dev_s *devp, unsigned int offset,
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enum tvin_port_e port,
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enum tvin_port_e port,
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enum tvin_color_fmt_e input_cfmt, unsigned int h,
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enum tvin_color_fmt_e input_cfmt, unsigned int h,
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enum bt_path_e bt_path);
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enum bt_path_e bt_path);
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@@ -2101,15 +2101,9 @@ start_chk:
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pr_info("urgent_en (%d):%d\n", devp->index,
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pr_info("urgent_en (%d):%d\n", devp->index,
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devp->urgent_en);
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devp->urgent_en);
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}
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}
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} else if (!strcmp(parm[0], "irq_flag")) {
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} else if (!strcmp(parm[0], "irq_cnt"))
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if (!parm[1])
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pr_info("vdin(%d) irq_cnt: %d\n", devp->index, devp->irq_cnt);
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pr_err("miss parameters .\n");
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else if (!strcmp(parm[0], "skip_vf_num")) {
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else if (kstrtoul(parm[1], 10, &val) == 0) {
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devp->vdin_irq_flag = val;
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pr_info("vdin(%d) irq_flag: %d\n", devp->index,
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devp->vdin_irq_flag);
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}
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} else if (!strcmp(parm[0], "skip_vf_num")) {
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||||||
if (!parm[1])
|
if (!parm[1])
|
||||||
pr_err("miss parameters .\n");
|
pr_err("miss parameters .\n");
|
||||||
else if ((kstrtoul(parm[1], 10, &val) == 0) && (devp->vfp)) {
|
else if ((kstrtoul(parm[1], 10, &val) == 0) && (devp->vfp)) {
|
||||||
@@ -2198,9 +2192,14 @@ start_chk:
|
|||||||
} else {
|
} else {
|
||||||
pr_info("vdin_afbce_mode: %d\n", devp->afbce_mode);
|
pr_info("vdin_afbce_mode: %d\n", devp->afbce_mode);
|
||||||
}
|
}
|
||||||
} else {
|
} else if (!strcmp(parm[0], "vdi6_afifo_overflow"))
|
||||||
|
pr_info("%d\n",
|
||||||
|
vdin_check_vdi6_afifo_overflow(devp->addr_offset));
|
||||||
|
else if (!strcmp(parm[0], "vdi6_afifo_clear"))
|
||||||
|
vdin_clear_vdi6_afifo_overflow_flg(devp->addr_offset);
|
||||||
|
else
|
||||||
pr_info("unknown command\n");
|
pr_info("unknown command\n");
|
||||||
}
|
|
||||||
kfree(buf_orig);
|
kfree(buf_orig);
|
||||||
return len;
|
return len;
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -41,9 +41,13 @@
|
|||||||
#include <linux/of_reserved_mem.h>
|
#include <linux/of_reserved_mem.h>
|
||||||
#include <linux/of_irq.h>
|
#include <linux/of_irq.h>
|
||||||
#include <linux/cma.h>
|
#include <linux/cma.h>
|
||||||
|
#include <linux/dma-buf.h>
|
||||||
|
#include <linux/scatterlist.h>
|
||||||
|
#include <linux/mm_types.h>
|
||||||
#include <linux/amlogic/media/codec_mm/codec_mm.h>
|
#include <linux/amlogic/media/codec_mm/codec_mm.h>
|
||||||
#include <linux/dma-contiguous.h>
|
#include <linux/dma-contiguous.h>
|
||||||
#include <linux/amlogic/iomap.h>
|
#include <linux/amlogic/iomap.h>
|
||||||
|
#include <linux/fdtable.h>
|
||||||
/* Amlogic Headers */
|
/* Amlogic Headers */
|
||||||
#include <linux/amlogic/media/vpu/vpu.h>
|
#include <linux/amlogic/media/vpu/vpu.h>
|
||||||
#include <linux/amlogic/media/vfm/vframe.h>
|
#include <linux/amlogic/media/vfm/vframe.h>
|
||||||
@@ -80,6 +84,8 @@ static unsigned long mem_start, mem_end;
|
|||||||
static unsigned int use_reserved_mem;
|
static unsigned int use_reserved_mem;
|
||||||
static unsigned int pr_times;
|
static unsigned int pr_times;
|
||||||
|
|
||||||
|
struct vdin_set_canvas_addr_s vdin_set_canvas_addr[VDIN_CANVAS_MAX_CNT];
|
||||||
|
static DECLARE_WAIT_QUEUE_HEAD(vframe_waitq);
|
||||||
/*
|
/*
|
||||||
* canvas_config_mode
|
* canvas_config_mode
|
||||||
* 0: canvas_config in driver probe
|
* 0: canvas_config in driver probe
|
||||||
@@ -874,6 +880,7 @@ int start_tvin_service(int no, struct vdin_parm_s *para)
|
|||||||
fe = tvin_get_frontend(para->port, 1);
|
fe = tvin_get_frontend(para->port, 1);
|
||||||
} else
|
} else
|
||||||
fe = tvin_get_frontend(para->port, 0);
|
fe = tvin_get_frontend(para->port, 0);
|
||||||
|
|
||||||
if (fe) {
|
if (fe) {
|
||||||
fe->private_data = para;
|
fe->private_data = para;
|
||||||
fe->port = para->port;
|
fe->port = para->port;
|
||||||
@@ -901,6 +908,7 @@ int start_tvin_service(int no, struct vdin_parm_s *para)
|
|||||||
(viu_hw_irq != 0)) {
|
(viu_hw_irq != 0)) {
|
||||||
ret = request_irq(devp->irq, vdin_v4l2_isr, IRQF_SHARED,
|
ret = request_irq(devp->irq, vdin_v4l2_isr, IRQF_SHARED,
|
||||||
devp->irq_name, (void *)devp);
|
devp->irq_name, (void *)devp);
|
||||||
|
|
||||||
if (ret != 0) {
|
if (ret != 0) {
|
||||||
pr_info("vdin_v4l2_isr request irq error.\n");
|
pr_info("vdin_v4l2_isr request irq error.\n");
|
||||||
return -1;
|
return -1;
|
||||||
@@ -1615,7 +1623,7 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
|
|||||||
devp->format_convert,
|
devp->format_convert,
|
||||||
devp->color_depth_mode, devp->source_bitdepth,
|
devp->color_depth_mode, devp->source_bitdepth,
|
||||||
devp->flags&VDIN_FLAG_RDMA_ENABLE);
|
devp->flags&VDIN_FLAG_RDMA_ENABLE);
|
||||||
vdin_set_top(devp->addr_offset, devp->parm.port,
|
vdin_set_top(devp, devp->addr_offset, devp->parm.port,
|
||||||
devp->prop.color_format, devp->h_active,
|
devp->prop.color_format, devp->h_active,
|
||||||
devp->bt_path);
|
devp->bt_path);
|
||||||
|
|
||||||
@@ -1970,6 +1978,15 @@ module_param(skip_ratio, ushort, 0664);
|
|||||||
MODULE_PARM_DESC(skip_ratio,
|
MODULE_PARM_DESC(skip_ratio,
|
||||||
"\n vdin skip frame ratio 1/ratio will reserved.\n");
|
"\n vdin skip frame ratio 1/ratio will reserved.\n");
|
||||||
|
|
||||||
|
static struct vf_entry *check_vdin_readlist(struct vdin_dev_s *devp)
|
||||||
|
{
|
||||||
|
struct vf_entry *vfe;
|
||||||
|
|
||||||
|
vfe = receiver_vf_peek(devp->vfp);
|
||||||
|
|
||||||
|
return vfe;
|
||||||
|
}
|
||||||
|
|
||||||
irqreturn_t vdin_v4l2_isr(int irq, void *dev_id)
|
irqreturn_t vdin_v4l2_isr(int irq, void *dev_id)
|
||||||
{
|
{
|
||||||
ulong flags;
|
ulong flags;
|
||||||
@@ -1981,7 +1998,7 @@ irqreturn_t vdin_v4l2_isr(int irq, void *dev_id)
|
|||||||
struct tvin_decoder_ops_s *decops;
|
struct tvin_decoder_ops_s *decops;
|
||||||
struct tvin_state_machine_ops_s *sm_ops;
|
struct tvin_state_machine_ops_s *sm_ops;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
int offset;
|
unsigned int offset;
|
||||||
|
|
||||||
if (!devp)
|
if (!devp)
|
||||||
return IRQ_HANDLED;
|
return IRQ_HANDLED;
|
||||||
@@ -1996,6 +2013,7 @@ irqreturn_t vdin_v4l2_isr(int irq, void *dev_id)
|
|||||||
spin_lock_irqsave(&devp->isr_lock, flags);
|
spin_lock_irqsave(&devp->isr_lock, flags);
|
||||||
devp->vdin_reset_flag = vdin_vsync_reset_mif(devp->index);
|
devp->vdin_reset_flag = vdin_vsync_reset_mif(devp->index);
|
||||||
offset = devp->addr_offset;
|
offset = devp->addr_offset;
|
||||||
|
|
||||||
if (devp)
|
if (devp)
|
||||||
/* avoid null pointer oops */
|
/* avoid null pointer oops */
|
||||||
stamp = vdin_get_meas_vstamp(offset);
|
stamp = vdin_get_meas_vstamp(offset);
|
||||||
@@ -2019,12 +2037,21 @@ irqreturn_t vdin_v4l2_isr(int irq, void *dev_id)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if ((devp->set_canvas_manual == 1) && check_vdin_readlist(devp)) {
|
||||||
|
devp->keystone_vframe_ready = 1;
|
||||||
|
wake_up_interruptible(&vframe_waitq);
|
||||||
|
}
|
||||||
|
|
||||||
if (devp->last_wr_vfe) {
|
if (devp->last_wr_vfe) {
|
||||||
provider_vf_put(devp->last_wr_vfe, devp->vfp);
|
provider_vf_put(devp->last_wr_vfe, devp->vfp);
|
||||||
devp->last_wr_vfe = NULL;
|
devp->last_wr_vfe = NULL;
|
||||||
vf_notify_receiver(devp->name,
|
|
||||||
|
if (devp->set_canvas_manual != 1) {
|
||||||
|
vf_notify_receiver(devp->name,
|
||||||
VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
|
VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*check vs is valid base on the time during continuous vs*/
|
/*check vs is valid base on the time during continuous vs*/
|
||||||
vdin_check_cycle(devp);
|
vdin_check_cycle(devp);
|
||||||
|
|
||||||
@@ -2101,6 +2128,7 @@ irqreturn_t vdin_v4l2_isr(int irq, void *dev_id)
|
|||||||
goto irq_handled;
|
goto irq_handled;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (curr_wr_vfe) {
|
if (curr_wr_vfe) {
|
||||||
curr_wr_vfe->flag |= VF_FLAG_NORMAL_FRAME;
|
curr_wr_vfe->flag |= VF_FLAG_NORMAL_FRAME;
|
||||||
/* provider_vf_put(curr_wr_vfe, devp->vfp); */
|
/* provider_vf_put(curr_wr_vfe, devp->vfp); */
|
||||||
@@ -2124,8 +2152,10 @@ irqreturn_t vdin_v4l2_isr(int irq, void *dev_id)
|
|||||||
}
|
}
|
||||||
|
|
||||||
devp->curr_wr_vfe = next_wr_vfe;
|
devp->curr_wr_vfe = next_wr_vfe;
|
||||||
vf_notify_receiver(devp->name, VFRAME_EVENT_PROVIDER_VFRAME_READY,
|
|
||||||
NULL);
|
if (devp->set_canvas_manual != 1)
|
||||||
|
vf_notify_receiver(devp->name,
|
||||||
|
VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
|
||||||
|
|
||||||
irq_handled:
|
irq_handled:
|
||||||
spin_unlock_irqrestore(&devp->isr_lock, flags);
|
spin_unlock_irqrestore(&devp->isr_lock, flags);
|
||||||
@@ -2188,6 +2218,9 @@ static int vdin_open(struct inode *inode, struct file *file)
|
|||||||
devp = container_of(inode->i_cdev, struct vdin_dev_s, cdev);
|
devp = container_of(inode->i_cdev, struct vdin_dev_s, cdev);
|
||||||
file->private_data = devp;
|
file->private_data = devp;
|
||||||
|
|
||||||
|
if (devp->set_canvas_manual == 1)
|
||||||
|
return 0;
|
||||||
|
|
||||||
if (devp->index >= VDIN_MAX_DEVS)
|
if (devp->index >= VDIN_MAX_DEVS)
|
||||||
return -ENXIO;
|
return -ENXIO;
|
||||||
|
|
||||||
@@ -2293,12 +2326,17 @@ static int vdin_release(struct inode *inode, struct file *file)
|
|||||||
static long vdin_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
static long vdin_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||||
{
|
{
|
||||||
long ret = 0;
|
long ret = 0;
|
||||||
|
int i;
|
||||||
int callmaster_status = 0;
|
int callmaster_status = 0;
|
||||||
struct vdin_dev_s *devp = NULL;
|
struct vdin_dev_s *devp = NULL;
|
||||||
void __user *argp = (void __user *)arg;
|
void __user *argp = (void __user *)arg;
|
||||||
struct vdin_parm_s param;
|
struct vdin_parm_s param;
|
||||||
ulong flags;
|
ulong flags;
|
||||||
struct vdin_hist_s vdin1_hist_temp;
|
struct vdin_hist_s vdin1_hist_temp;
|
||||||
|
struct page *page;
|
||||||
|
struct vdin_set_canvas_s vdinsetcanvas[VDIN_CANVAS_MAX_CNT];
|
||||||
|
unsigned int idx = 0;
|
||||||
|
unsigned int recov_idx = 0;
|
||||||
|
|
||||||
/* Get the per-device structure that contains this cdev */
|
/* Get the per-device structure that contains this cdev */
|
||||||
devp = file->private_data;
|
devp = file->private_data;
|
||||||
@@ -2415,6 +2453,7 @@ static long vdin_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
|||||||
}
|
}
|
||||||
case TVIN_IOC_STOP_DEC: {
|
case TVIN_IOC_STOP_DEC: {
|
||||||
struct tvin_parm_s *parm = &devp->parm;
|
struct tvin_parm_s *parm = &devp->parm;
|
||||||
|
|
||||||
mutex_lock(&devp->fe_lock);
|
mutex_lock(&devp->fe_lock);
|
||||||
if (!(devp->flags & VDIN_FLAG_DEC_STARTED)) {
|
if (!(devp->flags & VDIN_FLAG_DEC_STARTED)) {
|
||||||
pr_err("TVIN_IOC_STOP_DEC(%d) decode havn't started\n",
|
pr_err("TVIN_IOC_STOP_DEC(%d) decode havn't started\n",
|
||||||
@@ -2471,6 +2510,7 @@ static long vdin_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
|||||||
case TVIN_IOC_CLOSE: {
|
case TVIN_IOC_CLOSE: {
|
||||||
struct tvin_parm_s *parm = &devp->parm;
|
struct tvin_parm_s *parm = &devp->parm;
|
||||||
enum tvin_port_e port = parm->port;
|
enum tvin_port_e port = parm->port;
|
||||||
|
|
||||||
mutex_lock(&devp->fe_lock);
|
mutex_lock(&devp->fe_lock);
|
||||||
if (!(devp->flags & VDIN_FLAG_DEC_OPENED)) {
|
if (!(devp->flags & VDIN_FLAG_DEC_OPENED)) {
|
||||||
pr_err("TVIN_IOC_CLOSE(%d) you have not opened port\n",
|
pr_err("TVIN_IOC_CLOSE(%d) you have not opened port\n",
|
||||||
@@ -2772,25 +2812,34 @@ static long vdin_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
|||||||
param.port = TVIN_PORT_VIU1_WB0_VPP;
|
param.port = TVIN_PORT_VIU1_WB0_VPP;
|
||||||
else
|
else
|
||||||
param.port = TVIN_PORT_VIU1;
|
param.port = TVIN_PORT_VIU1;
|
||||||
param.reserved |= PARAM_STATE_HISTGRAM;
|
|
||||||
param.h_active = vdin_v4l2_param.width;
|
param.h_active = vdin_v4l2_param.width;
|
||||||
param.v_active = vdin_v4l2_param.height;
|
param.v_active = vdin_v4l2_param.height;
|
||||||
/* use 1280X720 for histgram*/
|
|
||||||
if ((vdin_v4l2_param.width > 1280) &&
|
if (devp->set_canvas_manual != 1) {
|
||||||
(vdin_v4l2_param.height > 720)) {
|
param.reserved |= PARAM_STATE_HISTGRAM;
|
||||||
devp->debug.scaler4w = 1280;
|
/* use 1280X720 for histgram*/
|
||||||
devp->debug.scaler4h = 720;
|
if ((vdin_v4l2_param.width > 1280) &&
|
||||||
devp->debug.dest_cfmt = TVIN_YUV422;
|
(vdin_v4l2_param.height > 720)) {
|
||||||
devp->flags |= VDIN_FLAG_MANUAL_CONVERSION;
|
devp->debug.scaler4w = 1280;
|
||||||
|
devp->debug.scaler4h = 720;
|
||||||
|
devp->debug.dest_cfmt = TVIN_YUV422;
|
||||||
|
devp->flags |= VDIN_FLAG_MANUAL_CONVERSION;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
param.frame_rate = vdin_v4l2_param.fps;
|
param.frame_rate = vdin_v4l2_param.fps;
|
||||||
param.cfmt = TVIN_YUV422;
|
param.cfmt = TVIN_YUV422;
|
||||||
param.dfmt = TVIN_YUV422;
|
|
||||||
|
if (devp->set_canvas_manual == 1)
|
||||||
|
param.dfmt = TVIN_RGB444;
|
||||||
|
else
|
||||||
|
param.dfmt = TVIN_YUV422;
|
||||||
|
|
||||||
param.scan_mode = TVIN_SCAN_MODE_PROGRESSIVE;
|
param.scan_mode = TVIN_SCAN_MODE_PROGRESSIVE;
|
||||||
param.fmt = TVIN_SIG_FMT_MAX;
|
param.fmt = TVIN_SIG_FMT_MAX;
|
||||||
//devp->flags |= VDIN_FLAG_V4L2_DEBUG;
|
//devp->flags |= VDIN_FLAG_V4L2_DEBUG;
|
||||||
devp->hist_bar_enable = 1;
|
devp->hist_bar_enable = 1;
|
||||||
devp->index = 1;
|
|
||||||
start_tvin_service(devp->index, ¶m);
|
start_tvin_service(devp->index, ¶m);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
@@ -2803,7 +2852,101 @@ static long vdin_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
|||||||
devp->flags &= (~VDIN_FLAG_ISR_REQ);
|
devp->flags &= (~VDIN_FLAG_ISR_REQ);
|
||||||
devp->flags &= (~VDIN_FLAG_FS_OPENED);
|
devp->flags &= (~VDIN_FLAG_FS_OPENED);
|
||||||
stop_tvin_service(devp->index);
|
stop_tvin_service(devp->index);
|
||||||
|
|
||||||
|
/*release manual set dma-bufs*/
|
||||||
|
if (devp->set_canvas_manual == 1) {
|
||||||
|
for (i = 0; i < 4; i++) {
|
||||||
|
if (vdin_set_canvas_addr[i].dmabuff == 0)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
dma_buf_unmap_attachment(
|
||||||
|
vdin_set_canvas_addr[i].dmabufattach,
|
||||||
|
vdin_set_canvas_addr[i].sgtable,
|
||||||
|
DMA_BIDIRECTIONAL);
|
||||||
|
dma_buf_detach(
|
||||||
|
vdin_set_canvas_addr[i].dmabuff,
|
||||||
|
vdin_set_canvas_addr[i].dmabufattach);
|
||||||
|
dma_buf_put(vdin_set_canvas_addr[i].dmabuff);
|
||||||
|
devp->keystone_entry[i] = NULL;
|
||||||
|
}
|
||||||
|
memset(vdin_set_canvas_addr, 0,
|
||||||
|
sizeof(struct vdin_set_canvas_addr_s) *
|
||||||
|
VDIN_CANVAS_MAX_CNT);
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case TVIN_IOC_S_CANVAS_ADDR:
|
||||||
|
if (devp->index == 0) {
|
||||||
|
pr_info("TVIN_IOC_S_CANVAS_ADDR can't be used at vdin0\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (copy_from_user(vdinsetcanvas, argp,
|
||||||
|
sizeof(struct vdin_set_canvas_s) * 4)) {
|
||||||
|
pr_info("TVIN_IOC_S_CANVAS_ADDR copy fail\n");
|
||||||
|
return -EFAULT;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < 4; i++) {
|
||||||
|
/*when fd means, the canvas list reaches end*/
|
||||||
|
if (vdinsetcanvas[i].fd < 0)
|
||||||
|
break;
|
||||||
|
|
||||||
|
if (vdinsetcanvas[i].index >= VDIN_CANVAS_MAX_CNT) {
|
||||||
|
pr_err("vdin buf idx range (0 ~ %d), current idx is too big.\n ",
|
||||||
|
VDIN_CANVAS_MAX_CNT - 1);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
idx = vdinsetcanvas[i].index;
|
||||||
|
|
||||||
|
vdin_set_canvas_addr[idx].dmabuff =
|
||||||
|
dma_buf_get(vdinsetcanvas[i].fd);
|
||||||
|
|
||||||
|
vdin_set_canvas_addr[idx].dmabufattach =
|
||||||
|
dma_buf_attach(
|
||||||
|
vdin_set_canvas_addr[idx].dmabuff,
|
||||||
|
devp->dev);
|
||||||
|
vdin_set_canvas_addr[idx].sgtable =
|
||||||
|
dma_buf_map_attachment(
|
||||||
|
vdin_set_canvas_addr[idx].dmabufattach,
|
||||||
|
DMA_BIDIRECTIONAL);
|
||||||
|
|
||||||
|
page = sg_page(vdin_set_canvas_addr[idx].sgtable->sgl);
|
||||||
|
vdin_set_canvas_addr[idx].paddr =
|
||||||
|
PFN_PHYS(page_to_pfn(page));
|
||||||
|
vdin_set_canvas_addr[idx].size =
|
||||||
|
vdin_set_canvas_addr[idx].dmabuff->size;
|
||||||
|
|
||||||
|
pr_info("TVIN_IOC_S_CANVAS_ADDR[%d] addr=0x%lx, len=0x%x.\n",
|
||||||
|
i,
|
||||||
|
vdin_set_canvas_addr[idx].paddr,
|
||||||
|
vdin_set_canvas_addr[idx].size);
|
||||||
|
|
||||||
|
__close_fd(current->files, vdinsetcanvas[i].fd);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case TVIN_IOC_S_CANVAS_RECOVERY:
|
||||||
|
if (devp->index == 0) {
|
||||||
|
pr_info("TVIN_IOC_S_CANVAS_RECOVERY can't be used at vdin0\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (copy_from_user(&recov_idx, argp, sizeof(unsigned int))) {
|
||||||
|
pr_info("TVIN_IOC_S_CANVAS_RECOVERY copy fail\n");
|
||||||
|
return -EFAULT;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (devp->keystone_entry[recov_idx]) {
|
||||||
|
receiver_vf_put(&devp->keystone_entry[recov_idx]->vf,
|
||||||
|
devp->vfp);
|
||||||
|
devp->keystone_entry[recov_idx] = NULL;
|
||||||
|
} else
|
||||||
|
pr_err("[vdin.%d] idx %d RECOVERY error\n",
|
||||||
|
devp->index, recov_idx);
|
||||||
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
ret = -ENOIOCTLCMD;
|
ret = -ENOIOCTLCMD;
|
||||||
/* pr_info("%s %d is not supported command\n", __func__, cmd); */
|
/* pr_info("%s %d is not supported command\n", __func__, cmd); */
|
||||||
@@ -2865,22 +3008,57 @@ static unsigned int vdin_poll(struct file *file, poll_table *wait)
|
|||||||
struct vdin_dev_s *devp = file->private_data;
|
struct vdin_dev_s *devp = file->private_data;
|
||||||
unsigned int mask = 0;
|
unsigned int mask = 0;
|
||||||
|
|
||||||
poll_wait(file, &devp->queue, wait);
|
if (devp->set_canvas_manual == 1) {
|
||||||
mask = (POLLIN | POLLRDNORM);
|
poll_wait(file, &vframe_waitq, wait);
|
||||||
|
|
||||||
|
if (devp->keystone_vframe_ready == 1)
|
||||||
|
mask = (POLLIN | POLLRDNORM);
|
||||||
|
} else {
|
||||||
|
poll_wait(file, &devp->queue, wait);
|
||||||
|
mask = (POLLIN | POLLRDNORM);
|
||||||
|
}
|
||||||
|
|
||||||
return mask;
|
return mask;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static ssize_t vdin_read(struct file *file, char __user *buf,
|
||||||
|
size_t count, loff_t *ppos)
|
||||||
|
{
|
||||||
|
int index;
|
||||||
|
long ret;
|
||||||
|
struct vf_entry *vfe;
|
||||||
|
struct vdin_dev_s *devp = file->private_data;
|
||||||
|
|
||||||
|
vfe = receiver_vf_peek(devp->vfp);
|
||||||
|
if (!vfe)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
vfe = receiver_vf_get(devp->vfp);
|
||||||
|
/*index = report_canvas_index;*/
|
||||||
|
index = vfe->vf.index;
|
||||||
|
devp->keystone_entry[index] = vfe;
|
||||||
|
ret = copy_to_user(buf, (void *)(&index), sizeof(int));
|
||||||
|
if (ret) {
|
||||||
|
pr_info("vdin_read copy_to_user error\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
devp->keystone_vframe_ready = 0;
|
||||||
|
|
||||||
|
return sizeof(int);
|
||||||
|
}
|
||||||
|
|
||||||
static const struct file_operations vdin_fops = {
|
static const struct file_operations vdin_fops = {
|
||||||
.owner = THIS_MODULE,
|
.owner = THIS_MODULE,
|
||||||
.open = vdin_open,
|
.open = vdin_open,
|
||||||
.release = vdin_release,
|
.read = vdin_read,
|
||||||
.unlocked_ioctl = vdin_ioctl,
|
.release = vdin_release,
|
||||||
|
.unlocked_ioctl = vdin_ioctl,
|
||||||
#ifdef CONFIG_COMPAT
|
#ifdef CONFIG_COMPAT
|
||||||
.compat_ioctl = vdin_compat_ioctl,
|
.compat_ioctl = vdin_compat_ioctl,
|
||||||
#endif
|
#endif
|
||||||
.mmap = vdin_mmap,
|
.mmap = vdin_mmap,
|
||||||
.poll = vdin_poll,
|
.poll = vdin_poll,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
@@ -3068,6 +3246,16 @@ static int vdin_drv_probe(struct platform_device *pdev)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ret = of_property_read_u32(pdev->dev.of_node,
|
||||||
|
"set_canvas_manual", &vdevp->set_canvas_manual);
|
||||||
|
|
||||||
|
if (ret) {
|
||||||
|
vdevp->set_canvas_manual = 0;
|
||||||
|
pr_info("set_canvas_manual = 0\n");
|
||||||
|
} else {
|
||||||
|
pr_info("set_canvas_manual = %d\n", vdevp->set_canvas_manual);
|
||||||
|
}
|
||||||
|
|
||||||
/*vdin urgent en*/
|
/*vdin urgent en*/
|
||||||
ret = of_property_read_u32(pdev->dev.of_node,
|
ret = of_property_read_u32(pdev->dev.of_node,
|
||||||
"urgent_en", &urgent_en);
|
"urgent_en", &urgent_en);
|
||||||
@@ -3087,16 +3275,12 @@ static int vdin_drv_probe(struct platform_device *pdev)
|
|||||||
/* @todo vdin_addr_offset */
|
/* @todo vdin_addr_offset */
|
||||||
if (is_meson_gxbb_cpu() && vdevp->index)
|
if (is_meson_gxbb_cpu() && vdevp->index)
|
||||||
vdin_addr_offset[vdevp->index] = 0x70;
|
vdin_addr_offset[vdevp->index] = 0x70;
|
||||||
else if ((is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
|
else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A) && vdevp->index)
|
||||||
is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
|
|
||||||
is_meson_tm2_cpu()) && vdevp->index)
|
|
||||||
vdin_addr_offset[vdevp->index] = 0x100;
|
vdin_addr_offset[vdevp->index] = 0x100;
|
||||||
vdevp->addr_offset = vdin_addr_offset[vdevp->index];
|
vdevp->addr_offset = vdin_addr_offset[vdevp->index];
|
||||||
vdevp->flags = 0;
|
vdevp->flags = 0;
|
||||||
/*canvas align number*/
|
/*canvas align number*/
|
||||||
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
|
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
|
||||||
is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
|
|
||||||
is_meson_tm2_cpu())
|
|
||||||
vdevp->canvas_align = 64;
|
vdevp->canvas_align = 64;
|
||||||
else
|
else
|
||||||
vdevp->canvas_align = 32;
|
vdevp->canvas_align = 32;
|
||||||
|
|||||||
@@ -157,6 +157,21 @@ static inline const char *vdin_fmt_convert_str(
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
struct vdin_set_canvas_s {
|
||||||
|
int fd;
|
||||||
|
int index;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vdin_set_canvas_addr_s {
|
||||||
|
long paddr;
|
||||||
|
int size;
|
||||||
|
|
||||||
|
struct dma_buf *dmabuff;
|
||||||
|
struct dma_buf_attachment *dmabufattach;
|
||||||
|
struct sg_table *sgtable;
|
||||||
|
};
|
||||||
|
extern struct vdin_set_canvas_addr_s vdin_set_canvas_addr[VDIN_CANVAS_MAX_CNT];
|
||||||
|
|
||||||
/*******for debug **********/
|
/*******for debug **********/
|
||||||
struct vdin_debug_s {
|
struct vdin_debug_s {
|
||||||
struct tvin_cutwin_s cutwin;
|
struct tvin_cutwin_s cutwin;
|
||||||
@@ -351,6 +366,11 @@ struct vdin_dev_s {
|
|||||||
unsigned int afbce_mode_pre;
|
unsigned int afbce_mode_pre;
|
||||||
unsigned int afbce_mode;
|
unsigned int afbce_mode;
|
||||||
unsigned int afbce_valid;
|
unsigned int afbce_valid;
|
||||||
|
|
||||||
|
/*fot 'T correction' on projector*/
|
||||||
|
unsigned int set_canvas_manual;
|
||||||
|
unsigned int keystone_vframe_ready;
|
||||||
|
struct vf_entry *keystone_entry[VDIN_CANVAS_MAX_CNT];
|
||||||
unsigned int canvas_config_mode;
|
unsigned int canvas_config_mode;
|
||||||
bool prehsc_en;
|
bool prehsc_en;
|
||||||
bool vshrk_en;
|
bool vshrk_en;
|
||||||
@@ -368,7 +388,6 @@ struct vdin_dev_s {
|
|||||||
unsigned int vdin_reset_flag;
|
unsigned int vdin_reset_flag;
|
||||||
unsigned int vdin_dev_ssize;
|
unsigned int vdin_dev_ssize;
|
||||||
wait_queue_head_t queue;
|
wait_queue_head_t queue;
|
||||||
|
|
||||||
struct dentry *dbg_root; /*dbg_fs*/
|
struct dentry *dbg_root; /*dbg_fs*/
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@@ -217,9 +217,7 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
|
|||||||
wr_viu(VPU_VIU2VDIN_HDN_CTRL, 0x40f00);
|
wr_viu(VPU_VIU2VDIN_HDN_CTRL, 0x40f00);
|
||||||
} else
|
} else
|
||||||
wr_bits_viu(VPU_VIU2VDIN_HDN_CTRL, devp->parm.h_active, 0, 14);
|
wr_bits_viu(VPU_VIU2VDIN_HDN_CTRL, devp->parm.h_active, 0, 14);
|
||||||
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
|
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
|
||||||
is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
|
|
||||||
is_meson_tm2_cpu()) {
|
|
||||||
if (((port >= TVIN_PORT_VIU1_WB0_VD1) &&
|
if (((port >= TVIN_PORT_VIU1_WB0_VD1) &&
|
||||||
(port <= TVIN_PORT_VIU1_WB0_POST_BLEND)) ||
|
(port <= TVIN_PORT_VIU1_WB0_POST_BLEND)) ||
|
||||||
((port >= TVIN_PORT_VIU2_WB0_VD1) &&
|
((port >= TVIN_PORT_VIU2_WB0_VD1) &&
|
||||||
@@ -263,9 +261,11 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
|
|||||||
(port == TVIN_PORT_VIU2_WB0_POST_BLEND))
|
(port == TVIN_PORT_VIU2_WB0_POST_BLEND))
|
||||||
wr_bits_viu(VPP_WRBAK_CTRL, 5, 0, 3);
|
wr_bits_viu(VPP_WRBAK_CTRL, 5, 0, 3);
|
||||||
else if ((port == TVIN_PORT_VIU1_WB0_VPP) ||
|
else if ((port == TVIN_PORT_VIU1_WB0_VPP) ||
|
||||||
(port == TVIN_PORT_VIU2_WB0_VPP))
|
(port == TVIN_PORT_VIU2_WB0_VPP)) {
|
||||||
wr_bits_viu(VPP_WRBAK_CTRL, 6, 0, 3);
|
wr_bits_viu(VPP_WRBAK_CTRL, 6, 0, 3);
|
||||||
else
|
/*increase h banking in case vdin afifo overflow*/
|
||||||
|
wr_bits_viu(VPP_WRBAK_CTRL, 0xff, 16, 8);
|
||||||
|
} else
|
||||||
wr_bits_viu(VPP_WRBAK_CTRL, 0, 4, 3);
|
wr_bits_viu(VPP_WRBAK_CTRL, 0, 4, 3);
|
||||||
|
|
||||||
if ((port == TVIN_PORT_VIU1_WB1_VD1) ||
|
if ((port == TVIN_PORT_VIU1_WB1_VD1) ||
|
||||||
|
|||||||
@@ -449,7 +449,9 @@ struct tvafe_pin_mux_s {
|
|||||||
struct tvin_latency_s)
|
struct tvin_latency_s)
|
||||||
#define TVIN_IOC_G_FRONTEND_INFO _IOR(_TM_T, 0x4e,\
|
#define TVIN_IOC_G_FRONTEND_INFO _IOR(_TM_T, 0x4e,\
|
||||||
struct tvin_frontend_info_s)
|
struct tvin_frontend_info_s)
|
||||||
|
#define TVIN_IOC_S_CANVAS_ADDR _IOW(_TM_T, 0x4f,\
|
||||||
|
struct vdin_set_canvas_s)
|
||||||
|
#define TVIN_IOC_S_CANVAS_RECOVERY _IO(_TM_T, 0x0a)
|
||||||
/* TVAFE */
|
/* TVAFE */
|
||||||
#define TVIN_IOC_S_AFE_VGA_PARM _IOW(_TM_T, 0x16, struct tvafe_vga_parm_s)
|
#define TVIN_IOC_S_AFE_VGA_PARM _IOW(_TM_T, 0x16, struct tvafe_vga_parm_s)
|
||||||
#define TVIN_IOC_G_AFE_VGA_PARM _IOR(_TM_T, 0x17, struct tvafe_vga_parm_s)
|
#define TVIN_IOC_G_AFE_VGA_PARM _IOR(_TM_T, 0x17, struct tvafe_vga_parm_s)
|
||||||
|
|||||||
Reference in New Issue
Block a user