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codec: support 3028a & 3026

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This commit is contained in:
yj
2013-08-01 16:52:07 +08:00
parent 73f33a7578
commit 76fedd9b84
11 changed files with 2803 additions and 1 deletions
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1
arch/arm/configs/rk3026_tb_defconfig
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@@ -325,6 +325,7 @@ CONFIG_SND_RK29_SOC=y
CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
CONFIG_SND_I2S_DMA_EVENT_STATIC=y
CONFIG_SND_RK_SOC_HDMI_I2S=y
CONFIG_SND_RK_SOC_RK3028=y
CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
CONFIG_UHID=y
CONFIG_HID_A4TECH=y

1
arch/arm/configs/rk3028a_tb_defconfig
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@@ -325,6 +325,7 @@ CONFIG_SND_RK29_SOC=y
CONFIG_SND_I2SO_USE_DOUBLE_CHANNELS=y
CONFIG_SND_I2S_DMA_EVENT_STATIC=y
CONFIG_SND_RK_SOC_HDMI_I2S=y
CONFIG_SND_RK_SOC_RK3028=y
CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
CONFIG_UHID=y
CONFIG_HID_A4TECH=y

30
arch/arm/mach-rk3026/board-rk3026-tb.c
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@@ -51,6 +51,10 @@
#include "../../../drivers/spi/rk29_spim.h"
#endif
#ifdef CONFIG_SND_SOC_RK3028
#include "../../../sound/soc/codecs/rk3028_codec.h"
#endif
#if defined(CONFIG_RK_HDMI)
#include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
#endif
@@ -932,6 +936,29 @@ void __sramfunc board_pmu_resume(void)
#endif
}
#ifdef CONFIG_SND_SOC_RK3028
struct rk3028_codec_pdata rk3028_codec_pdata_info={
.spk_ctl_gpio = INVALID_GPIO,
.hp_ctl_gpio = RK2928_PIN1_PA0,
};
static struct resource resources_acodec[] = {
{
.start = RK2928_ACODEC_PHYS,
.end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device rk3028_codec = {
.name = "rk3028-codec",
.id = -1,
.resource = resources_acodec,
.dev = {
.platform_data = &rk3028_codec_pdata_info,
}
};
#endif
/***********************************************************
* i2c
************************************************************/
@@ -1032,6 +1059,9 @@ static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_WIFI_CONTROL_FUNC
&rk29sdk_wifi_device,
#endif
#ifdef CONFIG_SND_SOC_RK3028
&rk3028_codec,
#endif
};
static void rk30_pm_power_off(void)

31
arch/arm/mach-rk3026/board-rk3028a-tb.c
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@@ -51,6 +51,10 @@
#include "../../../drivers/spi/rk29_spim.h"
#endif
#ifdef CONFIG_SND_SOC_RK3028
#include "../../../sound/soc/codecs/rk3028_codec.h"
#endif
#if defined(CONFIG_RK_HDMI)
#include "../../../drivers/video/rockchip/hdmi/rk_hdmi.h"
#endif
@@ -790,6 +794,30 @@ static struct platform_device device_ion = {
};
#endif
#ifdef CONFIG_SND_SOC_RK3028
struct rk3028_codec_pdata rk3028_codec_pdata_info={
.spk_ctl_gpio = INVALID_GPIO,
.hp_ctl_gpio = RK2928_PIN3_PD4,
};
static struct resource resources_acodec[] = {
{
.start = RK2928_ACODEC_PHYS,
.end = RK2928_ACODEC_PHYS + RK2928_ACODEC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device rk3028_codec = {
.name = "rk3028-codec",
.id = -1,
.resource = resources_acodec,
.dev = {
.platform_data = &rk3028_codec_pdata_info,
}
};
#endif
/***********************************************************
* pwm regulator
************************************************************/
@@ -1099,6 +1127,9 @@ static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_RFKILL_RK
&device_rfkill_rk,
#endif
#ifdef CONFIG_SND_SOC_RK3028
&rk3028_codec,
#endif
};
static void rk30_pm_power_off(void)

4
sound/soc/codecs/Kconfig
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@@ -466,3 +466,7 @@ config SND_SOC_WM9090
config SND_SOC_RK2928
tristate
depends on ARCH_RK2928
config SND_SOC_RK3028
tristate
depends on ARCH_RK3028

2
sound/soc/codecs/Makefile
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@@ -100,6 +100,7 @@ snd-soc-rt5640-objs := rt5640.o rt5640-dsp.o rt5640_ioctl.o rt56xx_ioctl.o
snd-soc-rt3261-objs := rt3261.o rt3261-dsp.o rt3261_ioctl.o rt_codec_ioctl.o
snd-soc-rt3224-objs := rt3261.o rt3261_ioctl.o rt_codec_ioctl.o
snd-soc-rk2928-objs := rk2928_codec.o
snd-soc-rk3028-objs := rk3028_codec.o
snd-soc-rt5639-objs := rt5639.o rt5639_ioctl.o rt56xx_ioctl.o
# Amp
@@ -211,6 +212,7 @@ obj-$(CONFIG_SND_SOC_RK1000) += snd-soc-rk1000.o
obj-$(CONFIG_SND_SOC_RK610) += snd-soc-rk610.o
obj-$(CONFIG_SND_SOC_RK616) += snd-soc-rk616.o
obj-$(CONFIG_SND_SOC_RK2928) += snd-soc-rk2928.o
obj-$(CONFIG_SND_SOC_RK3028) += snd-soc-rk3028.o
# Amp
obj-$(CONFIG_SND_SOC_LM4857) += snd-soc-lm4857.o

2174
sound/soc/codecs/rk3028_codec.c Normal file
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File diff suppressed because it is too large Load Diff

547
sound/soc/codecs/rk3028_codec.h Normal file
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@@ -0,0 +1,547 @@
/*
* rk3028.h -- RK3028 CODEC ALSA SoC audio driver
*
* Copyright 2013 Rockship
* Author: chenjq <chenjq@rock-chips.com>
*
*/
#ifndef __RK3028_CODEC_H__
#define __RK3028_CODEC_H__
/* codec register */
#define RK3028_CODEC_BASE (0x0)
#define RK3028_RESET (RK3028_CODEC_BASE + 0x00)
#define RK3028_ADC_INT_CTL1 (RK3028_CODEC_BASE + 0x08)
#define RK3028_ADC_INT_CTL2 (RK3028_CODEC_BASE + 0x0c)
#define RK3028_DAC_INT_CTL1 (RK3028_CODEC_BASE + 0x10)
#define RK3028_DAC_INT_CTL2 (RK3028_CODEC_BASE + 0x14)
#define RK3028_ADC_MIC_CTL (RK3028_CODEC_BASE + 0x88)
#define RK3028_BST_CTL (RK3028_CODEC_BASE + 0x8c)
#define RK3028_ALC_MUNIN_CTL (RK3028_CODEC_BASE + 0x90)
#define RK3028_BSTL_ALCL_CTL (RK3028_CODEC_BASE + 0x94)
#define RK3028_ALCR_GAIN_CTL (RK3028_CODEC_BASE + 0x98)
#define RK3028_ADC_ENABLE (RK3028_CODEC_BASE + 0x9c)
#define RK3028_DAC_CTL (RK3028_CODEC_BASE + 0xa0)
#define RK3028_DAC_ENABLE (RK3028_CODEC_BASE + 0xa4)
#define RK3028_HPMIX_CTL (RK3028_CODEC_BASE + 0xa8)
#define RK3028_HPMIX_S_SELECT (RK3028_CODEC_BASE + 0xac)
#define RK3028_HPOUT_CTL (RK3028_CODEC_BASE + 0xB0)
#define RK3028_HPOUTL_GAIN (RK3028_CODEC_BASE + 0xB4)
#define RK3028_HPOUTR_GAIN (RK3028_CODEC_BASE + 0xB8)
#define RK3028_SELECT_CURRENT (RK3028_CODEC_BASE + 0xBC)
#define RK3028_PGAL_AGC_CTL1 (RK3028_CODEC_BASE + 0xc0)
#define RK3028_PGAL_AGC_CTL2 (RK3028_CODEC_BASE + 0xc4)
#define RK3028_PGAL_AGC_CTL3 (RK3028_CODEC_BASE + 0xc8)
#define RK3028_PGAL_AGC_CTL4 (RK3028_CODEC_BASE + 0xcc)
#define RK3028_PGAL_ASR_CTL (RK3028_CODEC_BASE + 0xd0)
#define RK3028_PGAL_AGC_MAX_H (RK3028_CODEC_BASE + 0xd4)
#define RK3028_PGAL_AGC_MAX_L (RK3028_CODEC_BASE + 0xd8)
#define RK3028_PGAL_AGC_MIN_H (RK3028_CODEC_BASE + 0xdc)
#define RK3028_PGAL_AGC_MIN_L (RK3028_CODEC_BASE + 0xe0)
#define RK3028_PGAL_AGC_CTL5 (RK3028_CODEC_BASE + 0xe4)
#define RK3028_PGAR_AGC_CTL1 (RK3028_CODEC_BASE + 0x100)
#define RK3028_PGAR_AGC_CTL2 (RK3028_CODEC_BASE + 0x104)
#define RK3028_PGAR_AGC_CTL3 (RK3028_CODEC_BASE + 0x108)
#define RK3028_PGAR_AGC_CTL4 (RK3028_CODEC_BASE + 0x10c)
#define RK3028_PGAR_ASR_CTL (RK3028_CODEC_BASE + 0x110)
#define RK3028_PGAR_AGC_MAX_H (RK3028_CODEC_BASE + 0x114)
#define RK3028_PGAR_AGC_MAX_L (RK3028_CODEC_BASE + 0x118)
#define RK3028_PGAR_AGC_MIN_H (RK3028_CODEC_BASE + 0x11c)
#define RK3028_PGAR_AGC_MIN_L (RK3028_CODEC_BASE + 0x120)
#define RK3028_PGAR_AGC_CTL5 (RK3028_CODEC_BASE + 0x124)
/* ADC Interface Control 1 (0x08) */
#define RK3028_ALRCK_POL_MASK (0x1 << 7)
#define RK3028_ALRCK_POL_SFT 7
#define RK3028_ALRCK_POL_EN (0x1 << 7)
#define RK3028_ALRCK_POL_DIS (0x0 << 7)
#define RK3028_ADC_VWL_MASK (0x3 << 5)
#define RK3028_ADC_VWL_SFT 5
#define RK3028_ADC_VWL_32 (0x3 << 5)
#define RK3028_ADC_VWL_24 (0x2 << 5)
#define RK3028_ADC_VWL_20 (0x1 << 5)
#define RK3028_ADC_VWL_16 (0x0 << 5)
#define RK3028_ADC_DF_MASK (0x3 << 3)
#define RK3028_ADC_DF_SFT 3
#define RK3028_ADC_DF_PCM (0x3 << 3)
#define RK3028_ADC_DF_I2S (0x2 << 3)
#define RK3028_ADC_DF_LJ (0x1 << 3)
#define RK3028_ADC_DF_RJ (0x0 << 3)
#define RK3028_ADC_SWAP_MASK (0x1 << 1)
#define RK3028_ADC_SWAP_SFT 1
#define RK3028_ADC_SWAP_EN (0x1 << 1)
#define RK3028_ADC_SWAP_DIS (0x0 << 1)
#define RK3028_ADC_TYPE_MASK 0x1
#define RK3028_ADC_TYPE_SFT 0
#define RK3028_ADC_TYPE_MONO 0x1
#define RK3028_ADC_TYPE_STEREO 0x0
/* ADC Interface Control 2 (0x0c) */
#define RK3028_I2S_MODE_MASK (0x1 << 4)
#define RK3028_I2S_MODE_SFT (4)
#define RK3028_I2S_MODE_MST (0x1 << 4)
#define RK3028_I2S_MODE_SLV (0x0 << 4)
#define RK3028_ADC_WL_MASK (0x3 << 2)
#define RK3028_ADC_WL_SFT (2)
#define RK3028_ADC_WL_32 (0x3 << 2)
#define RK3028_ADC_WL_24 (0x2 << 2)
#define RK3028_ADC_WL_20 (0x1 << 2)
#define RK3028_ADC_WL_16 (0x0 << 2)
#define RK3028_ADC_RST_MASK (0x1 << 1)
#define RK3028_ADC_RST_SFT 91)
#define RK3028_ADC_RST_DIS (0x1 << 1)
#define RK3028_ADC_RST_EN (0x0 << 1)
#define RK3028_ABCLK_POL_MASK 0x1
#define RK3028_ABCLK_POL_SFT 0
#define RK3028_ABCLK_POL_EN 0x1
#define RK3028_ABCLK_POL_DIS 0x0
/* DAC Interface Control 1 (0x10) */
#define RK3028_DLRCK_POL_MASK (0x1 << 7)
#define RK3028_DLRCK_POL_SFT 7
#define RK3028_DLRCK_POL_EN (0x1 << 7)
#define RK3028_DLRCK_POL_DIS (0x0 << 7)
#define RK3028_DAC_VWL_MASK (0x3 << 5)
#define RK3028_DAC_VWL_SFT 5
#define RK3028_DAC_VWL_32 (0x3 << 5)
#define RK3028_DAC_VWL_24 (0x2 << 5)
#define RK3028_DAC_VWL_20 (0x1 << 5)
#define RK3028_DAC_VWL_16 (0x0 << 5)
#define RK3028_DAC_DF_MASK (0x3 << 3)
#define RK3028_DAC_DF_SFT 3
#define RK3028_DAC_DF_PCM (0x3 << 3)
#define RK3028_DAC_DF_I2S (0x2 << 3)
#define RK3028_DAC_DF_LJ (0x1 << 3)
#define RK3028_DAC_DF_RJ (0x0 << 3)
#define RK3028_DAC_SWAP_MASK (0x1 << 2)
#define RK3028_DAC_SWAP_SFT 2
#define RK3028_DAC_SWAP_EN (0x1 << 2)
#define RK3028_DAC_SWAP_DIS (0x0 << 2)
/* DAC Interface Control 2 (0x14) */
#define RK3028_DAC_WL_MASK (0x3 << 2)
#define RK3028_DAC_WL_SFT 2
#define RK3028_DAC_WL_32 (0x3 << 2)
#define RK3028_DAC_WL_24 (0x2 << 2)
#define RK3028_DAC_WL_20 (0x1 << 2)
#define RK3028_DAC_WL_16 (0x0 << 2)
#define RK3028_DAC_RST_MASK (0x1 << 1)
#define RK3028_DAC_RST_SFT 1
#define RK3028_DAC_RST_DIS (0x1 << 1)
#define RK3028_DAC_RST_EN (0x0 << 1)
#define RK3028_DBCLK_POL_MASK 0x1
#define RK3028_DBCLK_POL_SFT 0
#define RK3028_DBCLK_POL_EN 0x1
#define RK3028_DBCLK_POL_DIS 0x0
/* ADC & MICBIAS (0x88) */
#define RK3028_ADC_CURRENT_ENABLE (0x1 << 7)
#define RK3028_ADC_CURRENT_DISABLE (0x0 << 7)
#define RK3028_MICBIAS_VOL_ENABLE (0x1 << 6)
#define RK3028_MICBIAS_VOL_DISABLE (0x0 << 6)
#define RK3028_ADCL_ZERO_DET_EN (0x1 << 5)
#define RK3028_ADCL_ZERO_DET_DIS (0x0 << 5)
#define RK3028_ADCR_ZERO_DET_EN (0x1 << 4)
#define RK3028_ADCR_ZERO_DET_DIS (0x0 << 4)
#define RK3028_MICBIAS_VOL_SHT 0
#define RK3028_MICBIAS_VOL_MSK 7
#define RK3028_MICBIAS_VOL_MIN (0x0 << 0)
#define RK3028_MICBIAS_VOL_MAX (0x7 << 0)
/* BST_L BST_R CONTROL (0x8C) */
#define RK3028_BSTL_PWRD_SFT (6)
#define RK3028_BSTL_EN (0x1 << 6)
#define RK3028_BSTL_DIS (0x0 << 6)
#define RK3028_BSTL_GAIN_SHT (5)
#define RK3028_BSTL_GAIN_20 (0x1 << 5)
#define RK3028_BSTL_GAIN_0 (0x0 << 5)
#define RK3028_BSTL_MUTE_SHT (4)
#define RK3028_BSTR_PWRD_SFT (2)
#define RK3028_BSTR_EN (0x1 << 2)
#define RK3028_BSTR_DIS (0x0 << 2)
#define RK3028_BSTR_GAIN_SHT (1)
#define RK3028_BSTR_GAIN_20 (0x1 << 1)
#define RK3028_BSTR_GAIN_0 (0x0 << 1)
#define RK3028_BSTR_MUTE_SHT (0)
/* MUXINL ALCL MUXINR ALCR (0x90) */
#define RK3028_MUXINL_F_SHT (6)
#define RK3028_MUXINL_F_INL (0x02 << 6)
#define RK3028_MUXINL_F_BSTL (0x01 << 6)
#define RK3028_ALCL_PWR_SHT (5)
#define RK3028_ALCL_EN (0x1 << 5)
#define RK3028_ALCL_DIS (0x0 << 5)
#define RK3028_ALCL_MUTE_SHT (4)
#define RK3028_MUXINR_F_SHT (2)
#define RK3028_MUXINR_F_INR (0x02 << 2)
#define RK3028_MUXINR_F_BSTR (0x01 << 2)
#define RK3028_ALCR_PWR_SHT (1)
#define RK3028_ALCR_EN (0x1 << 1)
#define RK3028_ALCR_DIS (0x0 << 1)
#define RK3028_ALCR_MUTE_SHT (0)
/* BST_L MODE & ALC_L GAIN (0x94) */
#define RK3028_BSTL_MODE_SFT (5)
#define RK3028_BSTL_MODE_SINGLE (0x1 << 5)
#define RK3028_BSTL_MODE_DIFF (0x0 << 5)
#define RK3028_ALCL_GAIN_SHT (0)
#define RK3028_ALCL_GAIN_MSK (0x1f)
/* ALC_R GAIN (0x98) */
#define RK3028_ALCR_GAIN_SHT (0)
#define RK3028_ALCR_GAIN_MSK (0x1f)
/* ADC control (0x9C) */
#define RK3028_ADCL_REF_VOL_EN (0x1 << 7)
#define RK3028_ADCL_REF_VOL_DIS (0x0 << 7)
#define RK3028_ADCL_CLK_EN (0x1 << 6)
#define RK3028_ADCL_CLK_DIS (0x0 << 6)
#define RK3028_ADCL_AMP_EN (0x1 << 5)
#define RK3028_ADCL_AMP_DIS (0x0 << 5)
#define RK3028_ADCL_RST_EN (0x1 << 4)
#define RK3028_ADCL_RST_DIS (0x0 << 4)
#define RK3028_ADCR_REF_VOL_EN (0x1 << 3)
#define RK3028_ADCR_REF_VOL_DIS (0x0 << 3)
#define RK3028_ADCR_CLK_EN (0x1 << 2)
#define RK3028_ADCR_CLK_DIS (0x0 << 2)
#define RK3028_ADCR_AMP_EN (0x1 << 1)
#define RK3028_ADCR_AMP_DIS (0x0 << 1)
#define RK3028_ADCR_RST_EN (0x1 << 0)
#define RK3028_ADCR_RST_DIS (0x0 << 0)
/* DAC & VOUT Control (0xa0) */
#define RK3028_CURRENT_EN (0x1 << 6)
#define RK3028_CURRENT_DIS (0x0 << 6)
#define RK3028_REF_VOL_DACL_EN (0x1 << 5)
#define RK3028_REF_VOL_DACL_DIS (0x0 << 5)
#define RK3028_ZO_DET_VOUTL_EN (0x1 << 4)
#define RK3028_ZO_DET_VOUTL_DIS (0x0 << 4)
#define RK3028_DET_ERAPHONE_DIS (0x0 << 3)
#define RK3028_DET_ERAPHONE_EN (0x1 << 3)
#define RK3028_REF_VOL_DACR_EN (0x1 << 1)
#define RK3028_REF_VOL_DACR_DIS (0x0 << 1)
#define RK3028_ZO_DET_VOUTR_EN (0x1 << 0)
#define RK3028_ZO_DET_VOUTR_DIS (0x0 << 0)
/* DAC control (0xa4) */
#define RK3028_DACL_REF_VOL_EN (0x1 << 7)
#define RK3028_DACL_REF_VOL_DIS (0x0 << 7)
#define RK3028_DACL_CLK_EN (0x1 << 6)
#define RK3028_DACL_CLK_DIS (0x0 << 6)
#define RK3028_DACL_EN (0x1 << 5)
#define RK3028_DACL_DIS (0x0 << 5)
#define RK3028_DACL_INIT (0x0 << 4)
#define RK3028_DACL_WORK (0x1 << 4)
#define RK3028_DACR_REF_VOL_EN (0x1 << 3)
#define RK3028_DACR_REF_VOL_DIS (0x0 << 3)
#define RK3028_DACR_CLK_EN (0x1 << 2)
#define RK3028_DACR_CLK_DIS (0x0 << 2)
#define RK3028_DACR_EN (0x1 << 1)
#define RK3028_DACR_DIS (0x0 << 1)
#define RK3028_DACR_INIT (0x0 << 0)
#define RK3028_DACR_WORK (0x1 << 0)
/* HPMIXL HPMIXR Control (0xa8) */
#define RK3028_HPMIXL_SFT (6)
#define RK3028_HPMIXL_EN (0x1 << 6)
#define RK3028_HPMIXL_DIS (0x0 << 6)
#define RK3028_HPMIXL_INIT1 (0x0 << 5)
#define RK3028_HPMIXL_WORK1 (0x1 << 5)
#define RK3028_HPMIXL_INIT2 (0x0 << 4)
#define RK3028_HPMIXL_WORK2 (0x1 << 4)
#define RK3028_HPMIXR_SFT (6)
#define RK3028_HPMIXR_EN (0x1 << 2)
#define RK3028_HPMIXR_DIS (0x0 << 2)
#define RK3028_HPMIXR_INIT1 (0x0 << 1)
#define RK3028_HPMIXR_WORK1 (0x1 << 1)
#define RK3028_HPMIXR_INIT2 (0x0 << 0)
#define RK3028_HPMIXR_WORK2 (0x1 << 0)
/* HPMIXL Control (0xac) */
#define RK3028_HPMIXL_BYPASS_SFT (0x1 << 7)
#define RK3028_HPMIXL_SEL_ALCL_SFT (0x1 << 6)
#define RK3028_HPMIXL_SEL_ALCR_SFT (0x1 << 5)
#define RK3028_HPMIXL_SEL_DACL_SFT (0x1 << 4)
#define RK3028_HPMIXR_BYPASS_SFT (0x1 << 3)
#define RK3028_HPMIXR_SEL_ALCL_SFT (0x1 << 2)
#define RK3028_HPMIXR_SEL_ALCR_SFT (0x1 << 1)
#define RK3028_HPMIXR_SEL_DACR_SFT (0x1 << 0)
/* HPOUT Control (0xb0) */
#define RK3028_HPOUTL_PWR_SHT (7)
#define RK3028_HPOUTL_MSK (0x1 << 7)
#define RK3028_HPOUTL_EN (0x1 << 7)
#define RK3028_HPOUTL_DIS (0x0 << 7)
#define RK3028_HPOUTL_INIT_MSK (0x1 << 6)
#define RK3028_HPOUTL_INIT (0x0 << 6)
#define RK3028_HPOUTL_WORK (0x1 << 6)
#define RK3028_HPOUTL_MUTE_SHT (5)
#define RK3028_HPOUTL_MUTE_MSK (0x1 << 5)
#define RK3028_HPOUTL_MUTE_EN (0x0 << 5)
#define RK3028_HPOUTL_MUTE_DIS (0x1 << 5)
#define RK3028_HPOUTR_PWR_SHT (4)
#define RK3028_HPOUTR_MSK (0x1 << 4)
#define RK3028_HPOUTR_EN (0x1 << 4)
#define RK3028_HPOUTR_DIS (0x0 << 4)
#define RK3028_HPOUTR_INIT_MSK (0x1 << 3)
#define RK3028_HPOUTR_WORK (0x1 << 3)
#define RK3028_HPOUTR_INIT (0x0 << 3)
#define RK3028_HPOUTR_MUTE_SHT (2)
#define RK3028_HPOUTR_MUTE_MSK (0x1 << 2)
#define RK3028_HPOUTR_MUTE_EN (0x0 << 2)
#define RK3028_HPOUTR_MUTE_DIS (0x1 << 2)
#define RK3028_HPVREF_PWR_SHT (1)
#define RK3028_HPVREF_EN (0x1 << 1)
#define RK3028_HPVREF_DIS (0x0 << 1)
#define RK3028_HPVREF_WORK (0x1 << 0)
#define RK3028_HPVREF_INIT (0x0 << 0)
/* HPOUT GAIN (0xb4 0xb8) */
#define RK3028_HPOUT_GAIN_SFT (0)
/* SELECT CURR prechagrge/discharge (0xbc) */
#define RK3028_PRE_HPOUT (0x1 << 5)
#define RK3028_DIS_HPOUT (0x0 << 5)
#define RK3028_CUR_10UA_EN (0x0 << 4)
#define RK3028_CUR_10UA_DIS (0x1 << 4)
#define RK3028_CUR_I_EN (0x0 << 3)
#define RK3028_CUR_I_DIS (0x1 << 3)
#define RK3028_CUR_2I_EN (0x0 << 2)
#define RK3028_CUR_2I_DIS (0x1 << 2)
#define RK3028_CUR_4I_EN (0x0 << 0)
#define RK3028_CUR_4I_DIS (0x3 << 0)
/* PGA AGC control 1 (0xc0 0x100) */
#define RK3028_PGA_AGC_WAY_MASK (0x1 << 6)
#define RK3028_PGA_AGC_WAY_SFT 6
#define RK3028_PGA_AGC_WAY_JACK (0x1 << 6)
#define RK3028_PGA_AGC_WAY_NOR (0x0 << 6)
#define RK3028_PGA_AGC_BK_WAY_SFT 4
#define RK3028_PGA_AGC_BK_WAY_JACK1 (0x1 << 4)
#define RK3028_PGA_AGC_BK_WAY_NOR (0x0 << 4)
#define RK3028_PGA_AGC_BK_WAY_JACK2 (0x2 << 4)
#define RK3028_PGA_AGC_BK_WAY_JACK3 (0x3 << 4)
#define RK3028_PGA_AGC_HOLD_T_MASK 0xf
#define RK3028_PGA_AGC_HOLD_T_SFT 0
#define RK3028_PGA_AGC_HOLD_T_1024 0xa
#define RK3028_PGA_AGC_HOLD_T_512 0x9
#define RK3028_PGA_AGC_HOLD_T_256 0x8
#define RK3028_PGA_AGC_HOLD_T_128 0x7
#define RK3028_PGA_AGC_HOLD_T_64 0x6
#define RK3028_PGA_AGC_HOLD_T_32 0x5
#define RK3028_PGA_AGC_HOLD_T_16 0x4
#define RK3028_PGA_AGC_HOLD_T_8 0x3
#define RK3028_PGA_AGC_HOLD_T_4 0x2
#define RK3028_PGA_AGC_HOLD_T_2 0x1
#define RK3028_PGA_AGC_HOLD_T_0 0x0
/* PGA AGC control 2 (0xc4 0x104) */
#define RK3028_PGA_AGC_GRU_T_MASK (0xf << 4)
#define RK3028_PGA_AGC_GRU_T_SFT 4
#define RK3028_PGA_AGC_GRU_T_512 (0xa << 4)
#define RK3028_PGA_AGC_GRU_T_256 (0x9 << 4)
#define RK3028_PGA_AGC_GRU_T_128 (0x8 << 4)
#define RK3028_PGA_AGC_GRU_T_64 (0x7 << 4)
#define RK3028_PGA_AGC_GRU_T_32 (0x6 << 4)
#define RK3028_PGA_AGC_GRU_T_16 (0x5 << 4)
#define RK3028_PGA_AGC_GRU_T_8 (0x4 << 4)
#define RK3028_PGA_AGC_GRU_T_4 (0x3 << 4)
#define RK3028_PGA_AGC_GRU_T_2 (0x2 << 4)
#define RK3028_PGA_AGC_GRU_T_1 (0x1 << 4)
#define RK3028_PGA_AGC_GRU_T_0_5 (0x0 << 4)
#define RK3028_PGA_AGC_GRD_T_MASK 0xf
#define RK3028_PGA_AGC_GRD_T_SFT 0
#define RK3028_PGA_AGC_GRD_T_128_32 0xa
#define RK3028_PGA_AGC_GRD_T_64_16 0x9
#define RK3028_PGA_AGC_GRD_T_32_8 0x8
#define RK3028_PGA_AGC_GRD_T_16_4 0x7
#define RK3028_PGA_AGC_GRD_T_8_2 0x6
#define RK3028_PGA_AGC_GRD_T_4_1 0x5
#define RK3028_PGA_AGC_GRD_T_2_0_512 0x4
#define RK3028_PGA_AGC_GRD_T_1_0_256 0x3
#define RK3028_PGA_AGC_GRD_T_0_500_128 0x2
#define RK3028_PGA_AGC_GRD_T_0_250_64 0x1
#define RK3028_PGA_AGC_GRD_T_0_125_32 0x0
/* PGA AGC control 3 (0xc8 0x108) */
#define RK3028_PGA_AGC_MODE_MASK (0x1 << 7)
#define RK3028_PGA_AGC_MODE_SFT 7
#define RK3028_PGA_AGC_MODE_LIMIT (0x1 << 7)
#define RK3028_PGA_AGC_MODE_NOR (0x0 << 7)
#define RK3028_PGA_AGC_ZO_MASK (0x1 << 6)
#define RK3028_PGA_AGC_ZO_SFT 6
#define RK3028_PGA_AGC_ZO_EN (0x1 << 6)
#define RK3028_PGA_AGC_ZO_DIS (0x0 << 6)
#define RK3028_PGA_AGC_REC_MODE_MASK (0x1 << 5)
#define RK3028_PGA_AGC_REC_MODE_SFT 5
#define RK3028_PGA_AGC_REC_MODE_AC (0x1 << 5)
#define RK3028_PGA_AGC_REC_MODE_RN (0x0 << 5)
#define RK3028_PGA_AGC_FAST_D_MASK (0x1 << 4)
#define RK3028_PGA_AGC_FAST_D_SFT 4
#define RK3028_PGA_AGC_FAST_D_EN (0x1 << 4)
#define RK3028_PGA_AGC_FAST_D_DIS (0x0 << 4)
#define RK3028_PGA_AGC_NG_MASK (0x1 << 3)
#define RK3028_PGA_AGC_NG_SFT 3
#define RK3028_PGA_AGC_NG_EN (0x1 << 3)
#define RK3028_PGA_AGC_NG_DIS (0x0 << 3)
#define RK3028_PGA_AGC_NG_THR_MASK 0x7
#define RK3028_PGA_AGC_NG_THR_SFT 0
#define RK3028_PGA_AGC_NG_THR_N81DB 0x7
#define RK3028_PGA_AGC_NG_THR_N75DB 0x6
#define RK3028_PGA_AGC_NG_THR_N69DB 0x5
#define RK3028_PGA_AGC_NG_THR_N63DB 0x4
#define RK3028_PGA_AGC_NG_THR_N57DB 0x3
#define RK3028_PGA_AGC_NG_THR_N51DB 0x2
#define RK3028_PGA_AGC_NG_THR_N45DB 0x1
#define RK3028_PGA_AGC_NG_THR_N39DB 0x0
/* PGA AGC Control 4 (0xcc 0x10c) */
#define RK3028_PGA_AGC_ZO_MODE_MASK (0x1 << 5)
#define RK3028_PGA_AGC_ZO_MODE_SFT 5
#define RK3028_PGA_AGC_ZO_MODE_UWRC (0x1 << 5)
#define RK3028_PGA_AGC_ZO_MODE_UARC (0x0 << 5)
#define RK3028_PGA_AGC_VOL_MASK 0x1f
#define RK3028_PGA_AGC_VOL_SFT 0
/* PGA ASR Control (0xd0 0x110) */
#define RK3028_PGA_SLOW_CLK_MASK (0x1 << 3)
#define RK3028_PGA_SLOW_CLK_SFT 3
#define RK3028_PGA_SLOW_CLK_EN (0x1 << 3)
#define RK3028_PGA_SLOW_CLK_DIS (0x0 << 3)
#define RK3028_PGA_ASR_MASK 0x7
#define RK3028_PGA_ASR_SFT 0
#define RK3028_PGA_ASR_8KHz 0x7
#define RK3028_PGA_ASR_12KHz 0x6
#define RK3028_PGA_ASR_16KHz 0x5
#define RK3028_PGA_ASR_24KHz 0x4
#define RK3028_PGA_ASR_32KHz 0x3
#define RK3028_PGA_ASR_441KHz 0x2
#define RK3028_PGA_ASR_48KHz 0x1
#define RK3028_PGA_ASR_96KHz 0x0
/* PGA AGC Control 5 (0xe4 0x124) */
#define RK3028_PGA_AGC_MASK (0x1 << 6)
#define RK3028_PGA_AGC_SFT 6
#define RK3028_PGA_AGC_EN (0x1 << 6)
#define RK3028_PGA_AGC_DIS (0x0 << 6)
#define RK3028_PGA_AGC_MAX_G_MASK (0x7 << 3)
#define RK3028_PGA_AGC_MAX_G_SFT 3
#define RK3028_PGA_AGC_MAX_G_28_5DB (0x7 << 3)
#define RK3028_PGA_AGC_MAX_G_22_5DB (0x6 << 3)
#define RK3028_PGA_AGC_MAX_G_16_5DB (0x5 << 3)
#define RK3028_PGA_AGC_MAX_G_10_5DB (0x4 << 3)
#define RK3028_PGA_AGC_MAX_G_4_5DB (0x3 << 3)
#define RK3028_PGA_AGC_MAX_G_N1_5DB (0x2 << 3)
#define RK3028_PGA_AGC_MAX_G_N7_5DB (0x1 << 3)
#define RK3028_PGA_AGC_MAX_G_N13_5DB (0x0 << 3)
#define RK3028_PGA_AGC_MIN_G_MASK 0x7
#define RK3028_PGA_AGC_MIN_G_SFT 0
#define RK3028_PGA_AGC_MIN_G_24DB 0x7
#define RK3028_PGA_AGC_MIN_G_18DB 0x6
#define RK3028_PGA_AGC_MIN_G_12DB 0x5
#define RK3028_PGA_AGC_MIN_G_6DB 0x4
#define RK3028_PGA_AGC_MIN_G_0DB 0x3
#define RK3028_PGA_AGC_MIN_G_N6DB 0x2
#define RK3028_PGA_AGC_MIN_G_N12DB 0x1
#define RK3028_PGA_AGC_MIN_G_N18DB 0x0
enum {
RK3028_HIFI,
RK3028_VOICE,
};
enum {
RK3028_MONO = 1,
RK3028_STEREO,
};
enum {
OFF,
RCV,
SPK_PATH,
HP_PATH,
HP_NO_MIC,
BT,
SPK_HP,
RING_SPK,
RING_HP,
RING_HP_NO_MIC,
RING_SPK_HP,
};
enum {
MIC_OFF,
Main_Mic,
Hands_Free_Mic,
BT_Sco_Mic,
};
struct rk3028_reg_val_typ {
unsigned int reg;
unsigned int value;
};
struct rk3028_init_bit_typ {
unsigned int reg;
unsigned int power_bit;
unsigned int init_bit;
};
bool get_hdmi_state(void);
struct rk3028_codec_pdata {
int spk_ctl_gpio;
int hp_ctl_gpio;
};
#endif //__RK3028_CODEC_H__

10
sound/soc/rk29/Kconfig
View File

@@ -295,6 +295,16 @@ config SND_RK_SOC_RK2928
Say Y if you want to add support for SoC audio on rockchip
with the RK2928 internal codec.
config SND_RK_SOC_RK3028
tristate "SoC I2S Audio support for rockchip - RK3026&R3028A"
depends on SND_RK29_SOC && ARCH_RK3026
select SND_RK29_SOC_I2S
select SND_SOC_RK3028
select SND_RK29_CODEC_SOC_SLAVE
help
Say Y if you want to add support for SoC audio on rockchip
with the RK3028 internal codec.
if SND_RK29_SOC_I2S_2CH || SND_RK29_SOC_I2S_8CH || SND_RK_SOC_I2S2_2CH
choice
bool "Set i2s type"

2
sound/soc/rk29/Makefile
View File

@@ -32,6 +32,7 @@ snd-soc-rk616-objs := rk_rk616.o
snd-soc-aic3262-objs := rk29_aic3262.o
snd-soc-rk2928-objs := rk2928-card.o
snd-soc-es8323-objs := rk29_es8323.o
snd-soc-rk3028-objs := rk_rk3028.o
snd-soc-hdmi-i2s-objs := rk_hdmi_i2s.o
snd-soc-hdmi-spdif-objs := rk_hdmi_spdif.o
@@ -57,3 +58,4 @@ obj-$(CONFIG_SND_RK_SOC_HDMI_I2S) += snd-soc-hdmi-i2s.o
obj-$(CONFIG_SND_RK_SOC_HDMI_SPDIF) += snd-soc-hdmi-spdif.o
obj-$(CONFIG_SND_RK_SOC_RK2928) += snd-soc-rk2928.o
obj-$(CONFIG_SND_RK29_SOC_ES8323) += snd-soc-es8323.o
obj-$(CONFIG_SND_RK_SOC_RK3028) += snd-soc-rk3028.o

2
sound/soc/rk29/rk30_i2s.c
View File

@@ -477,7 +477,7 @@ static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME, GPIO0D_I2S2_2CH_SDO);
break;
#endif
#ifdef CONFIG_ARCH_RK2928
#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
case 0:
#if 0 //iomux --> gps(.ko)
rk30_mux_api_set(GPIO1A0_I2S_MCLK_NAME, GPIO1A_I2S_MCLK);