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UPSTREAM: clk: rockchip: Add 1.6GHz PLL rate for rk3399

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We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 4ee3fd4abe)

Change-Id: I118c877882d694b358697470225d8d94cb1271b5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Derek Basehore
2018-03-13 13:37:19 -07:00
committed by Tao Huang
parent e73ac0e248
commit 77a209b4ae
1 changed files with 1 additions and 0 deletions
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drivers/clk/rockchip/clk-rk3399.c
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@@ -57,6 +57,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),