diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 127456162e9f..62e6cd89733e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -396,6 +396,50 @@ opp-microvolt-L0 = <925000 925000 1150000>; clock-latency-ns = <40000>; }; + /* + * The Max frequency is 1200MHz in default normal mode. + * The Max frequency is 1800MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, especially in high + * temperature condition. Disable overdrive opps by default + * and you can enable them in dts file. + */ + cpu_opp_j_od_1416000000: opp-j-od-1416000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1000000 1000000 1150000>; + opp-microvolt-L0 = <1000000 1000000 1150000>; + opp-microvolt-L1 = <975000 975000 1150000>; + opp-microvolt-L2 = <950000 950000 1150000>; + opp-microvolt-L3 = <925000 925000 1150000>; + opp-microvolt-L4 = <900000 900000 1150000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; + cpu_opp_j_od_1608000000: opp-j-od-1608000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1037500 1037500 1150000>; + opp-microvolt-L0 = <1037500 1037500 1150000>; + opp-microvolt-L1 = <1012500 1012500 1150000>; + opp-microvolt-L2 = <987500 987500 1150000>; + opp-microvolt-L3 = <962500 962500 1150000>; + opp-microvolt-L4 = <937500 937500 1150000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; + cpu_opp_j_od_1800000000: opp-j-od-1800000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1125000 1125000 1150000>; + opp-microvolt-L0 = <1125000 1125000 1150000>; + opp-microvolt-L1 = <1100000 1100000 1150000>; + opp-microvolt-L2 = <1075000 1075000 1150000>; + opp-microvolt-L3 = <1050000 1050000 1150000>; + opp-microvolt-L4 = <1025000 1025000 1150000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; }; arm_pmu: arm-pmu { @@ -1654,8 +1698,47 @@ opp-j-700000000 { opp-supported-hw = <0x04 0xffff>; opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <925000 925000 1000000>; + opp-microvolt = <900000 900000 1000000>; opp-microvolt-L0 = <925000 925000 1000000>; + }; + /* The Max frequency is 700MHz in default normal mode. + * The Max frequency is 1000MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, especially in high + * temperature condition. Disable overdrive opps by default + * and you can enable them in dts file. + */ + npu_opp_j_od_800000000: opp-j-od-800000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <975000 975000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <950000 950000 1000000>; + opp-microvolt-L2 = <925000 925000 1000000>; + opp-microvolt-L3 = <900000 900000 1000000>; + opp-microvolt-L4 = <900000 900000 1000000>; + status = "disabled"; + }; + npu_opp_j_od_900000000: opp-j-od-900000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <1000000 1000000 1000000>; + opp-microvolt-L2 = <975000 975000 1000000>; + opp-microvolt-L3 = <950000 950000 1000000>; + opp-microvolt-L4 = <925000 925000 1000000>; + status = "disabled"; + }; + npu_opp_j_od_1000000000: opp-j-od-1000000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <1000000 1000000 1000000>; + opp-microvolt-L2 = <1000000 1000000 1000000>; + opp-microvolt-L3 = <975000 975000 1000000>; + opp-microvolt-L4 = <950000 950000 1000000>; status = "disabled"; }; }; @@ -1802,6 +1885,35 @@ opp-hz = /bits/ 64 <700000000>; opp-microvolt = <900000 900000 1000000>; }; + /* The Max frequency is 700MHz in default normal mode. + * The Max frequency is 900MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, especially in high + * temperature condition. Disable overdrive opps by default + * and you can enable them in dts file. + */ + gpu_opp_j_od_800000000: opp-j-od-800000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <950000 950000 1000000>; + opp-microvolt-L0 = <950000 950000 1000000>; + opp-microvolt-L1 = <925000 925000 1000000>; + opp-microvolt-L2 = <900000 900000 1000000>; + opp-microvolt-L3 = <875000 875000 1000000>; + opp-microvolt-L4 = <850000 850000 1000000>; + status = "disabled"; + }; + gpu_opp_j_od_900000000: opp-j-od-900000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <950000 950000 1000000>; + opp-microvolt-L3 = <925000 925000 1000000>; + opp-microvolt-L4 = <900000 900000 1000000>; + status = "disabled"; + }; }; rkvdec: rkvdec@ff340100 { diff --git a/arch/arm64/boot/dts/rockchip/rk3562j.dtsi b/arch/arm64/boot/dts/rockchip/rk3562j.dtsi index 5b660f7f4a5d..593e9e8b8360 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562j.dtsi @@ -4,27 +4,3 @@ */ #include "rk3562.dtsi" - -/ { - can0: can@ff600000 { - compatible = "rockchip,rk3562-can"; - reg = <0x0 0xff600000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; - clock-names = "baudclk", "apb_pclk"; - resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; - reset-names = "can", "can-apb"; - status = "disabled"; - }; - - can1: can@ff610000 { - compatible = "rockchip,rk3562-can"; - reg = <0x0 0xff610000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; - clock-names = "baudclk", "apb_pclk"; - resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; - reset-names = "can", "can-apb"; - status = "disabled"; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi index 03683b2bb432..e9959357b042 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi @@ -43,6 +43,8 @@ &dmc { wait-mode = ; + upthreshold = <50>; + downdifferential = <25>; }; &ebc { diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c index 6c487b615466..8e2995088253 100644 --- a/drivers/gpu/drm/rockchip/dw-dp.c +++ b/drivers/gpu/drm/rockchip/dw-dp.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 5ac2e5bd0272..4c19dc98ccce 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -1506,6 +1507,9 @@ static int rk_pcie_really_probe(void *p) if (ret) goto release_driver; + pm_runtime_enable(dev); + pm_runtime_get_sync(pci->dev); + reset_control_assert(rk_pcie->rsts); udelay(10); @@ -1576,7 +1580,8 @@ static int rk_pcie_really_probe(void *p) dw_pcie_dbi_ro_wr_dis(pci); /* 7. framework misc settings */ - device_init_wakeup(dev, true); + if (rk_pcie->skip_scan_in_resume) + device_init_wakeup(dev, true); device_enable_async_suspend(dev); /* Enable async system PM for multiports SoC */ return 0; @@ -1591,6 +1596,8 @@ disable_phy: disable_clk: clk_bulk_disable_unprepare(rk_pcie->clk_cnt, rk_pcie->clks); disable_vpcie3v3: + pm_runtime_put(dev); + pm_runtime_disable(dev); rk_pcie_disable_power(rk_pcie); release_driver: if (IS_ENABLED(CONFIG_PCIE_RK_THREADED_INIT)) @@ -1741,8 +1748,10 @@ static int __maybe_unused rockchip_dw_pcie_suspend(struct device *dev) */ if (rk_pcie->skip_scan_in_resume) { rfkill_get_wifi_power_state(&power); - if (!power) + if (!power) { + device_init_wakeup(dev, false); goto no_l2; + } } /* 2. Broadcast PME_Turn_Off Message */ @@ -1856,6 +1865,8 @@ static int __maybe_unused rockchip_dw_pcie_resume(struct device *dev) dw_pcie_dbi_ro_wr_dis(rk_pcie->pci); rk_pcie->in_suspend = false; + if (rk_pcie->skip_scan_in_resume) + device_init_wakeup(dev, true); return 0; err: