From c4d496df3b0b4aa2e87e92b1cf869177eb4e3f46 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 14 Oct 2024 16:02:57 +0800 Subject: [PATCH 1/6] arm64: dts: rockchip: rk3562j: remove duplicate can node Signed-off-by: Elaine Zhang Change-Id: I7396ebf0e9a02b395a222a7bedb2d6a353faa544 --- arch/arm64/boot/dts/rockchip/rk3562j.dtsi | 24 ----------------------- 1 file changed, 24 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562j.dtsi b/arch/arm64/boot/dts/rockchip/rk3562j.dtsi index 5b660f7f4a5d..593e9e8b8360 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562j.dtsi @@ -4,27 +4,3 @@ */ #include "rk3562.dtsi" - -/ { - can0: can@ff600000 { - compatible = "rockchip,rk3562-can"; - reg = <0x0 0xff600000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; - clock-names = "baudclk", "apb_pclk"; - resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; - reset-names = "can", "can-apb"; - status = "disabled"; - }; - - can1: can@ff610000 { - compatible = "rockchip,rk3562-can"; - reg = <0x0 0xff610000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; - clock-names = "baudclk", "apb_pclk"; - resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; - reset-names = "can", "can-apb"; - status = "disabled"; - }; -}; From 6ddfd0766a2019bd0ef2708b93e9436d233810d3 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Sat, 12 Oct 2024 16:52:48 +0800 Subject: [PATCH 2/6] arm64: dts: rockchip: rk3562j: add opp-table for overdrive mode Change-Id: I4c39b4e252ec445c080ed0a165853e76c9d1b25c Signed-off-by: Liang Chen --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 114 ++++++++++++++++++++++- 1 file changed, 113 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 127456162e9f..62e6cd89733e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -396,6 +396,50 @@ opp-microvolt-L0 = <925000 925000 1150000>; clock-latency-ns = <40000>; }; + /* + * The Max frequency is 1200MHz in default normal mode. + * The Max frequency is 1800MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, especially in high + * temperature condition. Disable overdrive opps by default + * and you can enable them in dts file. + */ + cpu_opp_j_od_1416000000: opp-j-od-1416000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1000000 1000000 1150000>; + opp-microvolt-L0 = <1000000 1000000 1150000>; + opp-microvolt-L1 = <975000 975000 1150000>; + opp-microvolt-L2 = <950000 950000 1150000>; + opp-microvolt-L3 = <925000 925000 1150000>; + opp-microvolt-L4 = <900000 900000 1150000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; + cpu_opp_j_od_1608000000: opp-j-od-1608000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1037500 1037500 1150000>; + opp-microvolt-L0 = <1037500 1037500 1150000>; + opp-microvolt-L1 = <1012500 1012500 1150000>; + opp-microvolt-L2 = <987500 987500 1150000>; + opp-microvolt-L3 = <962500 962500 1150000>; + opp-microvolt-L4 = <937500 937500 1150000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; + cpu_opp_j_od_1800000000: opp-j-od-1800000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1125000 1125000 1150000>; + opp-microvolt-L0 = <1125000 1125000 1150000>; + opp-microvolt-L1 = <1100000 1100000 1150000>; + opp-microvolt-L2 = <1075000 1075000 1150000>; + opp-microvolt-L3 = <1050000 1050000 1150000>; + opp-microvolt-L4 = <1025000 1025000 1150000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; }; arm_pmu: arm-pmu { @@ -1654,8 +1698,47 @@ opp-j-700000000 { opp-supported-hw = <0x04 0xffff>; opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <925000 925000 1000000>; + opp-microvolt = <900000 900000 1000000>; opp-microvolt-L0 = <925000 925000 1000000>; + }; + /* The Max frequency is 700MHz in default normal mode. + * The Max frequency is 1000MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, especially in high + * temperature condition. Disable overdrive opps by default + * and you can enable them in dts file. + */ + npu_opp_j_od_800000000: opp-j-od-800000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <975000 975000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <950000 950000 1000000>; + opp-microvolt-L2 = <925000 925000 1000000>; + opp-microvolt-L3 = <900000 900000 1000000>; + opp-microvolt-L4 = <900000 900000 1000000>; + status = "disabled"; + }; + npu_opp_j_od_900000000: opp-j-od-900000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <1000000 1000000 1000000>; + opp-microvolt-L2 = <975000 975000 1000000>; + opp-microvolt-L3 = <950000 950000 1000000>; + opp-microvolt-L4 = <925000 925000 1000000>; + status = "disabled"; + }; + npu_opp_j_od_1000000000: opp-j-od-1000000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <1000000 1000000 1000000>; + opp-microvolt-L2 = <1000000 1000000 1000000>; + opp-microvolt-L3 = <975000 975000 1000000>; + opp-microvolt-L4 = <950000 950000 1000000>; status = "disabled"; }; }; @@ -1802,6 +1885,35 @@ opp-hz = /bits/ 64 <700000000>; opp-microvolt = <900000 900000 1000000>; }; + /* The Max frequency is 700MHz in default normal mode. + * The Max frequency is 900MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, especially in high + * temperature condition. Disable overdrive opps by default + * and you can enable them in dts file. + */ + gpu_opp_j_od_800000000: opp-j-od-800000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <950000 950000 1000000>; + opp-microvolt-L0 = <950000 950000 1000000>; + opp-microvolt-L1 = <925000 925000 1000000>; + opp-microvolt-L2 = <900000 900000 1000000>; + opp-microvolt-L3 = <875000 875000 1000000>; + opp-microvolt-L4 = <850000 850000 1000000>; + status = "disabled"; + }; + gpu_opp_j_od_900000000: opp-j-od-900000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <950000 950000 1000000>; + opp-microvolt-L3 = <925000 925000 1000000>; + opp-microvolt-L4 = <900000 900000 1000000>; + status = "disabled"; + }; }; rkvdec: rkvdec@ff340100 { From ba115076501e0f0391a6c70def7932ed6fa35fc5 Mon Sep 17 00:00:00 2001 From: Weixin Zhou Date: Wed, 16 Oct 2024 16:30:14 +0800 Subject: [PATCH 3/6] arm64: dts: rockchip: rk3576-eink: adjust dmc freq threshold In order to reduce the power consumption Change-Id: I251d142bf22526889f7bd7afe3d8a96db2c5dcac Signed-off-by: Weixin Zhou --- arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi index 03683b2bb432..e9959357b042 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi @@ -43,6 +43,8 @@ &dmc { wait-mode = ; + upthreshold = <50>; + downdifferential = <25>; }; &ebc { From 7073ff96a51624de69f6d608677985e6c4940474 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Mon, 21 Oct 2024 17:28:48 +0800 Subject: [PATCH 4/6] drm/rockchip: dw-dp: Include linux/random.h drivers/gpu/drm/rockchip/dw-dp.c:567:9: error: implicit declaration of function 'get_random_bytes' Fixes: 7d048d6dac94 ("drm/rockchip: dw-dp: Add HDCP function support") Signed-off-by: Tao Huang Change-Id: Id1c9fc3570877fb6b9900e0a107cff7efb6a91da --- drivers/gpu/drm/rockchip/dw-dp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c index 6c487b615466..8e2995088253 100644 --- a/drivers/gpu/drm/rockchip/dw-dp.c +++ b/drivers/gpu/drm/rockchip/dw-dp.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include From 666775e30a724da77ad75de1d4e9cfc3ed783297 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 14 Oct 2024 10:29:44 +0800 Subject: [PATCH 5/6] PCI: rockchip: dw: Add runtime pm support Currently, the PCIe pd is in unsupported state which fails to power down it even if not devices attached.This patch is required when the pcie controller sits on a bus with its own power domain and clocks which are controlled via a bus driver like simple pm bus. Change-Id: Ic0fbaec82a25b92e9b874aa3003f0b18451985a6 Signed-off-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 5ac2e5bd0272..d13194f311bf 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -1506,6 +1507,9 @@ static int rk_pcie_really_probe(void *p) if (ret) goto release_driver; + pm_runtime_enable(dev); + pm_runtime_get_sync(pci->dev); + reset_control_assert(rk_pcie->rsts); udelay(10); @@ -1591,6 +1595,8 @@ disable_phy: disable_clk: clk_bulk_disable_unprepare(rk_pcie->clk_cnt, rk_pcie->clks); disable_vpcie3v3: + pm_runtime_put(dev); + pm_runtime_disable(dev); rk_pcie_disable_power(rk_pcie); release_driver: if (IS_ENABLED(CONFIG_PCIE_RK_THREADED_INIT)) From e15707617c807e82a706dfdd2240c83d62f2634e Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 14 Oct 2024 10:39:40 +0800 Subject: [PATCH 6/6] PCI: rockchip: dw: remove wakeup if attached device is down device_init_wakeup is used for PD driver to leave power-domain opened during suspend. This feature was originally designed for Wi-Fi. Check Wi-Fi's power to see if we need to remove wakeup support before into suspend. Change-Id: I468157b1d5f9775e3c961d1d059b167c0bb95395 Signed-off-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index d13194f311bf..4c19dc98ccce 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -1580,7 +1580,8 @@ static int rk_pcie_really_probe(void *p) dw_pcie_dbi_ro_wr_dis(pci); /* 7. framework misc settings */ - device_init_wakeup(dev, true); + if (rk_pcie->skip_scan_in_resume) + device_init_wakeup(dev, true); device_enable_async_suspend(dev); /* Enable async system PM for multiports SoC */ return 0; @@ -1747,8 +1748,10 @@ static int __maybe_unused rockchip_dw_pcie_suspend(struct device *dev) */ if (rk_pcie->skip_scan_in_resume) { rfkill_get_wifi_power_state(&power); - if (!power) + if (!power) { + device_init_wakeup(dev, false); goto no_l2; + } } /* 2. Broadcast PME_Turn_Off Message */ @@ -1862,6 +1865,8 @@ static int __maybe_unused rockchip_dw_pcie_resume(struct device *dev) dw_pcie_dbi_ro_wr_dis(rk_pcie->pci); rk_pcie->in_suspend = false; + if (rk_pcie->skip_scan_in_resume) + device_init_wakeup(dev, true); return 0; err: