From 79ce61131167faaf5dbe82acead880d1f3d715da Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Mon, 19 Oct 2020 16:11:32 +0800 Subject: [PATCH] media: rockchip: ispp: enable sharp dma to ddr default disable sharp dma to ddr, sharp will goto idle early, and sharp may be abnormal, output image error. Enable default to fix this bug. Change-Id: I2882394e461b257a1734342cf08a8a3ddc465360 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/ispp/hw.c | 1 - drivers/media/platform/rockchip/ispp/stream.c | 28 +++++++++---------- 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/media/platform/rockchip/ispp/hw.c b/drivers/media/platform/rockchip/ispp/hw.c index 21af9f27f971..24a8a033a540 100644 --- a/drivers/media/platform/rockchip/ispp/hw.c +++ b/drivers/media/platform/rockchip/ispp/hw.c @@ -323,7 +323,6 @@ static int __maybe_unused rkispp_runtime_resume(struct device *dev) writel(SW_SCL_BYPASS, base + RKISPP_SCL2_CTRL); writel(OTHER_FORCE_UPD, base + RKISPP_CTRL_UPDATE); writel(GATE_DIS_ALL, base + RKISPP_CTRL_CLKGATE); - writel(SW_SHP_DMA_DIS, base + RKISPP_SHARP_CORE_CTRL); writel(SW_FEC2DDR_DIS, base + RKISPP_FEC_CORE_CTRL); writel(0xfffffff, base + RKISPP_CTRL_INT_MSK); writel(GATE_DIS_NR, base + RKISPP_CTRL_CLKGATE); diff --git a/drivers/media/platform/rockchip/ispp/stream.c b/drivers/media/platform/rockchip/ispp/stream.c index e10a14e81cc8..ff9283e5ed42 100644 --- a/drivers/media/platform/rockchip/ispp/stream.c +++ b/drivers/media/platform/rockchip/ispp/stream.c @@ -666,9 +666,6 @@ static int nr_init_buf(struct rkispp_device *dev, u32 size) if (vdev->module_ens & ISPP_MODULE_FEC) cnt = RKISPP_BUF_MAX; - else if (dev->inp == INP_ISP && - !(dev->isp_mode & ISP_ISPP_QUICK)) - cnt = 0; for (i = 0; i < cnt; i++) { buf = &vdev->nr.buf.wr[i]; buf->size = size; @@ -790,7 +787,15 @@ static int config_nr_shp(struct rkispp_device *dev) rkispp_write(dev, RKISPP_SHARP_WR_VIR_STRIDE, ALIGN(width * mult, 16) >> 2); rkispp_set_bits(dev, RKISPP_SHARP_CTRL, SW_SHP_WR_FORMAT_MASK, fmt & (~FMT_FBC)); - rkispp_clear_bits(dev, RKISPP_SHARP_CORE_CTRL, SW_SHP_DMA_DIS); + } else { + stream = &vdev->stream[STREAM_MB]; + if (!stream->streaming) { + val = vdev->nr.buf.wr[0].dma_addr; + rkispp_write(dev, RKISPP_SHARP_WR_Y_BASE, val); + rkispp_write(dev, RKISPP_SHARP_WR_UV_BASE, val); + rkispp_write(dev, RKISPP_SHARP_WR_VIR_STRIDE, ALIGN(width * mult, 16) >> 2); + rkispp_set_bits(dev, RKISPP_SHARP_CTRL, SW_SHP_WR_FORMAT_MASK, FMT_FBC); + } } val = vdev->nr.buf.tmp_yuv.dma_addr; @@ -1089,7 +1094,6 @@ static int is_stopped_mb(struct rkispp_stream *stream) { struct rkispp_device *dev = stream->isppdev; struct rkispp_stream_vdev *vdev = &dev->stream_vdev; - void __iomem *base = dev->hw_dev->base_addr; bool is_stopped = true; u32 val; @@ -1100,16 +1104,10 @@ static int is_stopped_mb(struct rkispp_stream *stream) 0, SW_FEC2DDR_DIS); } else if (vdev->module_ens & (ISPP_MODULE_NR | ISPP_MODULE_SHP)) { - val = readl(base + RKISPP_CTRL_QUICK); - if (val & GLB_QUICK_EN) { - val = dev->stream_vdev.nr.buf.wr[0].dma_addr; - writel(val, base + RKISPP_SHARP_WR_Y_BASE); - writel(val, base + RKISPP_SHARP_WR_UV_BASE); - } else { - rkispp_clear_bits(dev, RKISPP_SHARP_CTRL, FMT_FBC); - rkispp_set_bits(dev, RKISPP_SHARP_CORE_CTRL, - 0, SW_SHP_DMA_DIS); - } + val = dev->stream_vdev.nr.buf.wr[0].dma_addr; + rkispp_write(dev, RKISPP_SHARP_WR_Y_BASE, val); + rkispp_write(dev, RKISPP_SHARP_WR_UV_BASE, val); + rkispp_set_bits(dev, RKISPP_SHARP_CTRL, SW_SHP_WR_FORMAT_MASK, FMT_FBC); } /* for wait last frame */