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Revert "PCI: Add locking to RMW PCI Express Capability Register accessors"

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This reverts commit f2d7da8faf which is
commit 5e70d0acf0 upstream.

It breaks the Android API and is not needed for any Android-specific
platforms, so it can be dropped for now.  If it is needed in the future,
it can be brought back in an abi-safe way.

Bug: 161946584
Change-Id: Ic12bc34085f8c7ecea1899f7e14b6ba2a920beba
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Greg Kroah-Hartman
2023-10-12 12:04:03 +00:00
parent 41aa552887
commit 79dd1a60c7
3 changed files with 5 additions and 50 deletions
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20
drivers/pci/access.c
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@@ -491,8 +491,8 @@ int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
} }
EXPORT_SYMBOL(pcie_capability_write_dword); EXPORT_SYMBOL(pcie_capability_write_dword);
int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos, int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
u16 clear, u16 set) u16 clear, u16 set)
{ {
int ret; int ret;
u16 val; u16 val;
@@ -506,21 +506,7 @@ int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
return ret; return ret;
} }
EXPORT_SYMBOL(pcie_capability_clear_and_set_word_unlocked); EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
u16 clear, u16 set)
{
unsigned long flags;
int ret;
spin_lock_irqsave(&dev->pcie_cap_lock, flags);
ret = pcie_capability_clear_and_set_word_unlocked(dev, pos, clear, set);
spin_unlock_irqrestore(&dev->pcie_cap_lock, flags);
return ret;
}
EXPORT_SYMBOL(pcie_capability_clear_and_set_word_locked);
int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
u32 clear, u32 set) u32 clear, u32 set)

1
drivers/pci/probe.c
View File

@@ -2313,7 +2313,6 @@ struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
.end = -1, .end = -1,
}; };
spin_lock_init(&dev->pcie_cap_lock);
#ifdef CONFIG_PCI_MSI #ifdef CONFIG_PCI_MSI
raw_spin_lock_init(&dev->msi_lock); raw_spin_lock_init(&dev->msi_lock);
#endif #endif

34
include/linux/pci.h
View File

@@ -467,7 +467,6 @@ struct pci_dev {
pci_dev_flags_t dev_flags; pci_dev_flags_t dev_flags;
atomic_t enable_cnt; /* pci_enable_device has been called */ atomic_t enable_cnt; /* pci_enable_device has been called */
spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */
u32 saved_config_space[16]; /* Config space saved at suspend time */ u32 saved_config_space[16]; /* Config space saved at suspend time */
struct hlist_head saved_cap_space; struct hlist_head saved_cap_space;
int rom_attr_enabled; /* Display of ROM attribute enabled? */ int rom_attr_enabled; /* Display of ROM attribute enabled? */
@@ -1234,40 +1233,11 @@ int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos, int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
u16 clear, u16 set); u16 clear, u16 set);
int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
u16 clear, u16 set);
int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
u32 clear, u32 set); u32 clear, u32 set);
/**
* pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers
* @dev: PCI device structure of the PCI Express device
* @pos: PCI Express Capability Register
* @clear: Clear bitmask
* @set: Set bitmask
*
* Perform a Read-Modify-Write (RMW) operation using @clear and @set
* bitmasks on PCI Express Capability Register at @pos. Certain PCI Express
* Capability Registers are accessed concurrently in RMW fashion, hence
* require locking which is handled transparently to the caller.
*/
static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev,
int pos,
u16 clear, u16 set)
{
switch (pos) {
case PCI_EXP_LNKCTL:
case PCI_EXP_RTCTL:
return pcie_capability_clear_and_set_word_locked(dev, pos,
clear, set);
default:
return pcie_capability_clear_and_set_word_unlocked(dev, pos,
clear, set);
}
}
static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
u16 set) u16 set)
{ {