From 7a2e9b2ecc7890de025eda43bfb7207e0ddd5e73 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 25 Apr 2025 12:05:56 +0800 Subject: [PATCH] net: phy: rockchip-fephy: Add 24M clock rate setting Change-Id: Ie1f51e419bddb458e03be1e048260660a63f020a Signed-off-by: David Wu --- drivers/net/phy/rockchip-fephy.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/net/phy/rockchip-fephy.c b/drivers/net/phy/rockchip-fephy.c index 4cf793a4a789..2acae6b0321c 100644 --- a/drivers/net/phy/rockchip-fephy.c +++ b/drivers/net/phy/rockchip-fephy.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #define INTERNAL_FEPHY_ID 0x06808101 @@ -58,6 +59,7 @@ enum { struct rockchip_fephy_priv { struct phy_device *phydev; + unsigned int clk_rate; int old_link; int wol_irq; }; @@ -91,6 +93,7 @@ static int rockchip_fephy_bank_write(struct phy_device *phydev, u8 bank, static int rockchip_fephy_config_init(struct phy_device *phydev) { + struct rockchip_fephy_priv *priv = phydev->priv; int ret; /* LED Control, default:0x7f */ @@ -108,6 +111,23 @@ static int rockchip_fephy_config_init(struct phy_device *phydev) if (ret) return ret; + if (priv->clk_rate == 24000000) { + int sel; + + /* pll cp cur sel */ + sel = rockchip_fephy_bank_read(phydev, BANK_AFE, 0x3); + if (sel < 0) + return sel; + ret = rockchip_fephy_bank_write(phydev, BANK_AFE, 0x3, sel | 0x2); + if (ret) + return ret; + + /* pll lpf res sel */ + ret = rockchip_fephy_bank_write(phydev, BANK_DSP0, 0x1a, 0x6); + if (ret) + return ret; + } + return ret; } @@ -210,6 +230,9 @@ static int rockchip_fephy_probe(struct phy_device *phydev) return -ENOMEM; phydev->priv = priv; + if (device_property_read_u32(&phydev->mdio.dev, "clock-frequency", &priv->clk_rate)) + priv->clk_rate = 24000000; + priv->wol_irq = platform_get_irq_byname_optional(to_platform_device(&phydev->mdio.dev), "wol_irq"); if (priv->wol_irq == -EPROBE_DEFER)