From 7a58edc59d492486cd3929cf3c6fb04b24912e06 Mon Sep 17 00:00:00 2001
From: Simon Xue <xxm@rock-chips.com>
Date: Mon, 28 Feb 2022 10:40:46 +0800
Subject: [PATCH] ARM: dts: rockchip: rv1106: add saradc/wdt_ns/hw_decompress

Change-Id: I727e614a6c4385f49737e5bf013f677cc1676067
Signed-off-by: Simon Xue <xxm@rock-chips.com>
---
 arch/arm/boot/dts/rv1106.dtsi | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi
index 8c1f50285a70..79798e2e617a 100644
--- a/arch/arm/boot/dts/rv1106.dtsi
+++ b/arch/arm/boot/dts/rv1106.dtsi
@@ -212,6 +212,18 @@
 			<200000000>;
 	};
 
+	saradc: saradc@ff3c0000 {
+		compatible = "rockchip,rk3588-saradc";
+		reg = <0xff3c0000 0x100>;
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		#io-channel-cells = <1>;
+		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_P_SARADC>;
+		reset-names = "saradc-apb";
+		status = "disabled";
+	};
+
 	u2phy: usb2-phy@ff3e0000 {
 		compatible = "rockchip,rv1106-usb2phy";
 		reg = <0xff3e0000 0x8000>;
@@ -394,11 +406,30 @@
 		status = "disabled";
 	};
 
+	hw_decompress: decompress@ff520000 {
+		compatible = "rockchip,hw-decompress";
+		reg = <0xff520000 0x1000>;
+		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
+		clock-names = "aclk", "dclk", "pclk";
+		resets = <&cru SRST_D_DECOM>;
+		reset-names = "dresetn";
+		status = "disabled";
+	};
+
 	ioc: syscon@ff538000 {
 		compatible = "rockchip,rv1106-ioc", "syscon";
 		reg = <0xff538000 0x40000>;
 	};
 
+	wdt: watchdog@ff5a0000 {
+		compatible = "rockchip,rv1126-wdt", "snps,dw-wdt";
+		reg = <0xff5a0000 0x100>;
+		clocks = <&cru PCLK_WDT_NS>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
 	vop: vop@ff990000 {
 		compatible = "rockchip,rv1106-vop";
 		reg = <0xff990000 0x200>;