From 7a64b622460d1140daf4d29eedac2bb79dc8ff4c Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 16 Mar 2023 15:36:13 +0800 Subject: [PATCH] PCI: rockchip: dw: Support BAR4 for standard ep Change-Id: Ia6182f410681b76f2d7c8225d0d8467c5664452f Signed-off-by: Jon Lin --- .../pci/controller/dwc/pcie-dw-ep-rockchip.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c index b315bb97a70f..943b23d2c35b 100644 --- a/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c @@ -482,23 +482,26 @@ static void rockchip_pcie_resize_bar(struct rockchip_pcie *rockchip) resbar_base = rockchip_pci_find_resbar_capability(rockchip); /* Resize BAR0 4M 32bits, BAR2 64M 64bits-pref */ - bar = 0; + bar = BAR_0; dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0); dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x2c0); - rockchip_pcie_ep_set_bar_flag(rockchip, BAR_0, PCI_BASE_ADDRESS_MEM_TYPE_32); + rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32); - bar = 2; + bar = BAR_2; dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0); dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x6c0); - rockchip_pcie_ep_set_bar_flag(rockchip, BAR_2, + rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64); + bar = BAR_4; + dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0); + dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0xc0); + rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32); + /* Disable BAR1 BAR4 BAR5*/ - bar = 1; + bar = BAR_1; dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0); - bar = 4; - dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0); - bar = 5; + bar = BAR_5; dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + bar * 4, 0); }