From f82e27936cdfaba6628d31591026ba2cf0789e22 Mon Sep 17 00:00:00 2001 From: Joy Cho Date: Fri, 28 Dec 2018 15:39:57 +0900 Subject: [PATCH] ODROID-COMMON: hdmitx: add hdmi phy custombuilt mode Change-Id: I2ee9c9eccda7d54e6a801ed6b90039deb3c3fc75 Signed-off-by: Dongjin Kim --- .../vout/hdmitx/hdmi_common/hdmi_parameters.c | 183 ++++++++++++++++++ .../vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c | 1 + .../vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c | 9 + .../vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c | 11 ++ .../vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c | 50 ++++- .../vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c | 20 ++ .../media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c | 20 ++ .../media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c | 28 +++ .../amlogic/media/vout/hdmi_tx/hdmi_common.h | 1 + .../media/vout/hdmi_tx/hdmi_tx_module.h | 3 + 10 files changed, 322 insertions(+), 4 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c b/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c index ef04459e7ad9..ad32252b4955 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c @@ -17,8 +17,35 @@ #include #include +#include #include +#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) +struct modeline_table { + /* resolutions */ + unsigned int horpixels; + unsigned int verpixels; + /* clock and frequency */ + unsigned int pixel_clock; + unsigned int hor_freq; + unsigned int ver_freq; + /* htimings */ + unsigned int hdisp; + unsigned int hsyncstart; + unsigned int hsyncend; + unsigned int htotal; + /* vtiminigs */ + unsigned int vdisp; + unsigned int vsyncstart; + unsigned int vsyncend; + unsigned int vtotal; + /* polarity and scan mode */ + unsigned int hsync_polarity; /* 1:+hsync, 0:-hsync */ + unsigned int vsync_polarity; /* 1:+vsync, 0:-vsync */ + unsigned int progress_mode; /* 1:progress, 0:interlaced */ +}; +#endif + static struct hdmi_format_para fmt_para_1920x1080p60_16x9 = { .vic = HDMI_1920x1080p60_16x9, .name = "1920x1080p60hz", @@ -1478,6 +1505,27 @@ static struct hdmi_format_para fmt_para_480x800p60_4x3 = { .viu_mux = VIU_MUX_ENCP, }, }; + +static struct hdmi_format_para fmt_para_custombuilt = { + .vic = HDMI_CUSTOMBUILT, + .name = "custombuilt", + .sname = "custombuilt", + .pixel_repetition_factor = 0, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .timing = { + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "custombuilt", + .mode = VMODE_HDMI, + .aspect_ratio_num = 16, + .aspect_ratio_den = 9, + .sync_duration_den = 1, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; #endif static struct hdmi_format_para fmt_para_non_hdmi_fmt = { @@ -2796,6 +2844,7 @@ static struct hdmi_format_para *all_fmt_paras[] = { &fmt_para_vesa_2560x1440p60_16x9, &fmt_para_480x320p60_4x3, &fmt_para_480x800p60_4x3, + &fmt_para_custombuilt, #endif &fmt_para_null_hdmi_fmt, &fmt_para_non_hdmi_fmt, @@ -2813,6 +2862,140 @@ struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic) return &fmt_para_non_hdmi_fmt; } +#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) +void debug_hdmi_fmt_param(struct hdmi_format_para param) +{ + /* timing */ + pr_info("fmt_para.timing\n"); + pr_info(" - pixel_freq %d, frac_freq %d\n", + param.timing.pixel_freq, param.timing.frac_freq); + pr_info(" - h_freq %d, v_freq %d\n", + param.timing.h_freq, param.timing.v_freq); + pr_info(" - hsync_polarity %d, vsync_polarity %d\n", + param.timing.hsync_polarity, + param.timing.vsync_polarity); + pr_info(" - h_active %d, h_total %d\n", + param.timing.h_active, param.timing.h_total); + pr_info(" - h_blank %d, h_front %d, h_sync %d, h_back %d\n", + param.timing.h_blank, param.timing.h_front, + param.timing.h_sync, param.timing.h_back); + pr_info(" - v_active %d, v_total %d\n", + param.timing.v_active, param.timing.v_total); + pr_info(" - v_blank %d, v_front %d, v_sync %d, v_back %d\n", + param.timing.v_blank, param.timing.v_front, + param.timing.v_sync, param.timing.v_back); + pr_info(" - v_sync_ln %d\n", param.timing.v_sync_ln); + + /* hdmitx_vinfo */ + pr_info("fmt_para.hdmitx_vinfo\n"); + pr_info(" - name %s, mode %d\n", + param.hdmitx_vinfo.name, param.hdmitx_vinfo.mode); + pr_info(" - width %d, height %d, field_height %d\n", + param.hdmitx_vinfo.width, param.hdmitx_vinfo.height, + param.hdmitx_vinfo.field_height); + pr_info(" - aspect_ratio_num %d, aspect_ratio_den %d\n", + param.hdmitx_vinfo.aspect_ratio_num, + param.hdmitx_vinfo.aspect_ratio_den); + pr_info(" - video_clk %d\n", param.hdmitx_vinfo.video_clk); + pr_info(" - htotal %d, vtotal %d\n", + param.hdmitx_vinfo.htotal, param.hdmitx_vinfo.vtotal); + pr_info(" - viu_color_fmt %d, viu_mux %d\n", + param.hdmitx_vinfo.viu_color_fmt, + param.hdmitx_vinfo.viu_mux); +} + +/* + * assuming modeline information from command line is as following. + * setenv modeline + * "horpixels,verpixels,pixel_clock,hor_freq,ver_freq + * ,hdisp,hsyncstart,hsyncend,htotal,vdisp,vsyncstart,vsyncend,vtotal + * ,hsync_polarity,vsync_polarity,progress_mode" + */ +static int __init setup_modeline(char *s) +{ + struct hdmi_cea_timing *custom_timing; + struct modeline_table tbl; + unsigned int *buf; + char *item = NULL; + unsigned long temp = 0; + int ret; + int i = 0; + + /* 1. parsing modeline information from command line */ + buf = (unsigned int *)&(tbl.horpixels); + + while (s != NULL) { + item = strsep(&s, ","); + ret = kstrtoul(item, 0, &temp); + *(buf + i) = temp; + i++; + } + + /* 2. build hdmi_format_para */ + fmt_para_custombuilt.progress_mode = tbl.progress_mode; + fmt_para_custombuilt.tmds_clk = tbl.pixel_clock; + + /* timing */ + fmt_para_custombuilt.timing.pixel_freq = tbl.pixel_clock; + fmt_para_custombuilt.timing.frac_freq = tbl.pixel_clock; + fmt_para_custombuilt.timing.h_freq = tbl.hor_freq; + fmt_para_custombuilt.timing.v_freq = (tbl.ver_freq * 1000); + fmt_para_custombuilt.timing.hsync_polarity = tbl.hsync_polarity; + fmt_para_custombuilt.timing.vsync_polarity = tbl.vsync_polarity; + /* h_active = hdisp */ + fmt_para_custombuilt.timing.h_active = tbl.hdisp; + /* h_total = htotal */ + fmt_para_custombuilt.timing.h_total = tbl.htotal; + /* h_blank = htotal - hdisp */ + fmt_para_custombuilt.timing.h_blank = tbl.htotal - tbl.hdisp; + /* h_front = hsyncstart - hdisp */ + fmt_para_custombuilt.timing.h_front = tbl.hsyncstart - tbl.hdisp; + /* h_sync = hsyncend - hsyncstart */ + fmt_para_custombuilt.timing.h_sync = tbl.hsyncend - tbl.hsyncstart; + /* h_back = (h_blank - (h_front + h_sync))*/ + fmt_para_custombuilt.timing.h_back + = fmt_para_custombuilt.timing.h_blank + - fmt_para_custombuilt.timing.h_front + - fmt_para_custombuilt.timing.h_sync; + /* v_active = vdisp */ + fmt_para_custombuilt.timing.v_active = tbl.vdisp; + /* v_total = vtotal */ + fmt_para_custombuilt.timing.v_total = tbl.vtotal; + /* v_blank = vtotal - vdisp */ + fmt_para_custombuilt.timing.v_blank = tbl.vtotal - tbl.vdisp; + /* v_front = vsyncstart - vdisp */ + fmt_para_custombuilt.timing.v_front = tbl.vsyncstart - tbl.vdisp; + /* v_sync = vsyncend - vsyncstart */ + fmt_para_custombuilt.timing.v_sync = tbl.vsyncend - tbl.vsyncstart; + /* v_back = (v_blank - (v_front + v_sync)) */ + fmt_para_custombuilt.timing.v_back + = fmt_para_custombuilt.timing.v_blank + - fmt_para_custombuilt.timing.v_front + - fmt_para_custombuilt.timing.v_sync; + fmt_para_custombuilt.timing.v_sync_ln = 1; + + /* hdmitx_vinfo */ + fmt_para_custombuilt.hdmitx_vinfo.width = tbl.hdisp; + fmt_para_custombuilt.hdmitx_vinfo.height = tbl.vdisp; + fmt_para_custombuilt.hdmitx_vinfo.field_height = tbl.vdisp; + fmt_para_custombuilt.hdmitx_vinfo.sync_duration_num = tbl.ver_freq; + fmt_para_custombuilt.hdmitx_vinfo.video_clk = (tbl.pixel_clock * 1000); + fmt_para_custombuilt.hdmitx_vinfo.htotal = tbl.htotal; + fmt_para_custombuilt.hdmitx_vinfo.vtotal = tbl.vtotal; + + /* check parameters */ + debug_hdmi_fmt_param(fmt_para_custombuilt); + + /* 3. copy custom-built timing information for backup */ + custom_timing = get_custom_timing(); + memcpy(custom_timing, &fmt_para_custombuilt.timing, + sizeof(fmt_para_custombuilt.timing)); + + return 0; +} +__setup("modeline=", setup_modeline); +#endif + struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t) { int i; diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c index 55efbb12dbc5..c3797cd11b3c 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c @@ -2631,6 +2631,7 @@ static struct dispmode_vic dispmode_vic_tab[] = { #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) {"480x320p60hz", HDMI_480x320p60_4x3}, {"480x800p60hz", HDMI_480x800p60_4x3}, + {"custombuilt", HDMI_CUSTOMBUILT}, #endif }; diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c index 5ddd65bd673a..c8d910070c1e 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c @@ -123,6 +123,15 @@ struct extcon_dev *hdmitx_extcon_cedst; */ int hdr_status_pos; +#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) +static struct hdmi_cea_timing custom_timing; +struct hdmi_cea_timing *get_custom_timing(void) +{ + return &custom_timing; +} +EXPORT_SYMBOL(get_custom_timing); +#endif + static inline void hdmitx_notify_hpd(int hpd) { if (hpd) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c index 417a134438ce..de0eabe874d8 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c @@ -832,6 +832,17 @@ static struct hdmitx_vidpara hdmi_tx_video_params[] = { .ss = SS_SCAN_UNDER, .sc = SC_SCALE_HORIZ_VERT, }, + { + .VIC = HDMI_CUSTOMBUILT, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = ASPECT_RATIO_SAME_AS_SOURCE, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, #endif }; diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c index df902882e19b..a1ee610047f3 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c @@ -1747,6 +1747,40 @@ static struct vic_tvregs_set tvregsTab_3dfp[] = { {HDMI_1280x720p50_16x9, tvregs_3dfp_720p50}, }; +#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) +void build_custom_vic_tvregs(void) +{ + struct hdmi_cea_timing *custom_timing = get_custom_timing(); + + hd_write_reg(P_VENC_VDAC_SETTING, 0xff); + + hd_write_reg(P_ENCP_VIDEO_EN, 0); + hd_write_reg(P_ENCI_VIDEO_EN, 0); + + hd_write_reg(P_ENCP_VIDEO_MODE, 0x4040); + hd_write_reg(P_ENCP_VIDEO_MODE_ADV, 0x18); + + hd_write_reg(P_ENCP_VIDEO_MAX_PXCNT, (custom_timing->h_total - 1)); + hd_write_reg(P_ENCP_VIDEO_MAX_LNCNT, (custom_timing->v_total - 1)); + + hd_write_reg(P_ENCP_VIDEO_HAVON_BEGIN, custom_timing->h_back); + hd_write_reg(P_ENCP_VIDEO_HAVON_END, + ((custom_timing->h_back + custom_timing->h_active) - 1)); + hd_write_reg(P_ENCP_VIDEO_VAVON_BLINE, custom_timing->v_back); + hd_write_reg(P_ENCP_VIDEO_VAVON_ELINE, + ((custom_timing->v_back + custom_timing->v_active) - 1)); + + hd_write_reg(P_ENCP_VIDEO_HSO_BEGIN, 0); + hd_write_reg(P_ENCP_VIDEO_HSO_END, custom_timing->h_sync); + hd_write_reg(P_ENCP_VIDEO_VSO_BEGIN, 0x1E); + hd_write_reg(P_ENCP_VIDEO_VSO_END, 0x32); + hd_write_reg(P_ENCP_VIDEO_VSO_BLINE, 0x0); + hd_write_reg(P_ENCP_VIDEO_VSO_ELINE, custom_timing->v_sync); + hd_write_reg(P_ENCP_VIDEO_EN, 1); + hd_write_reg(P_ENCI_VIDEO_EN, 0); +} +#endif + static inline void setreg(const struct reg_s *r) { hd_write_reg(r->reg, r->val); @@ -1774,17 +1808,25 @@ static const struct reg_s *tvregs_setting_mode(struct hdmitx_dev *hdev) void set_vmode_enc_hw(struct hdmitx_dev *hdev) { - const struct reg_s *s = tvregs_setting_mode(hdev); - /* Turn off VDAC, no need any more for HDMITX */ + const struct reg_s *s; +#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) + if (hdev->cur_video_param->VIC == HDMI_CUSTOMBUILT) { + build_custom_vic_tvregs(); + return; + } +#endif + s = tvregs_setting_mode(hdev); + + /* Turn off VDAC, no need any more for HDMITX */ /*hd_set_reg_bits(P_VENC_VDAC_SETTING, 0x1f, 0, 5);*/ if (s) { pr_info("set enc for VIC: %d\n", - hdev->cur_video_param->VIC); + hdev->cur_video_param->VIC); while (s->reg != MREG_END_MARKER) setreg(s++); } else pr_info("set enc not find VIC: %d\n", - hdev->cur_video_param->VIC); + hdev->cur_video_param->VIC); } diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index f1e6314bd713..e453e4bb1b83 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -1503,6 +1503,9 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param) unsigned long vso_begin_evn = 0; struct hdmi_format_para *hdmi_encp_para = NULL; struct hdmi_cea_timing *hdmi_encp_timing = NULL; +#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) + struct hdmi_cea_timing *custom_timing; +#endif if ((param->VIC & HDMITX_VESA_OFFSET) == HDMITX_VESA_OFFSET) { /* VESA modes setting */ @@ -1972,6 +1975,23 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param) VSYNC_LINES = 3; SOF_LINES = 29; break; + case HDMI_CUSTOMBUILT: + custom_timing = get_custom_timing(); + INTERLACE_MODE = 0U; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = custom_timing->h_active; + ACTIVE_LINES = custom_timing->v_active; + LINES_F0 = custom_timing->v_total; + LINES_F1 = custom_timing->v_total; + FRONT_PORCH = custom_timing->h_front; + HSYNC_PIXELS = custom_timing->h_sync; + BACK_PORCH = custom_timing->h_back; + EOF_LINES = custom_timing->v_front; + VSYNC_LINES = custom_timing->v_sync; + SOF_LINES = custom_timing->v_back; + TOTAL_FRAMES = 4; + break; #endif default: break; diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c index 54e87c5986ae..6dd21ea79688 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c @@ -831,6 +831,10 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = { {{HDMI_480x800p60_4x3, HDMI_VIC_END}, 2560000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + {{HDMI_CUSTOMBUILT, + HDMI_VIC_END}, + /* default 1080p60hz */ + 5940000, 4, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, #endif {{HDMI_VIC_FAKE, HDMI_VIC_END}, @@ -1075,6 +1079,9 @@ static void hdmitx_set_clk_(struct hdmitx_dev *hdev) enum hdmi_vic vic = hdev->cur_VIC; enum hdmi_color_space cs = hdev->para->cs; enum hdmi_color_depth cd = hdev->para->cd; +#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) + struct hdmi_cea_timing *custom_timing; +#endif /* YUV 422 always use 24B mode */ if (cs == COLORSPACE_YUV422) @@ -1145,6 +1152,19 @@ static void hdmitx_set_clk_(struct hdmitx_dev *hdev) return; } next: +#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) + /* FIXME : consider pixel clocks over 200MHz */ + if (vic == HDMI_CUSTOMBUILT) { + pr_info("[n2][%s] vic == HDMI_CUSTOMBUILT\n", __func__); + custom_timing = get_custom_timing(); + p_enc[j].hpll_clk_out = (custom_timing->frac_freq * 10); + /* control od dividers */ + p_enc[j].od1 = 1; + p_enc[j].od2 = 1; + p_enc[j].od3 = 2; + } +#endif + hdmitx_set_cts_sys_clk(hdev); set_hpll_clk_out(p_enc[j].hpll_clk_out); if ((cd == COLORDEPTH_24B) && (hdev->sspll)) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c index 63be2cc4e1f9..c41047e2c0f6 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c @@ -564,6 +564,34 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk) #endif default: pr_info("error hpll clk: %d\n", clk); + +#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) + { + unsigned int m, m1, m2; + + /* FIXME : consider pixel clocks over 200MHz */ + /* calculate "m" */ + m1 = (clk * 0x3A) / 1422000; + m2 = (clk * 0xE1) / 5405400; + m = ((m1 + m2) / 2) + 1; + m &= 0xff; + m |= 0x3b000400; + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, m); + pr_info("m1 0x%x, m2 0x%x, m 0x%x\n", m1, m2, m); + + /* check pll LOCK time */ + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000); + + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + } +#endif break; } } diff --git a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h index abf83c880e4f..b545e6aa9691 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h +++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h @@ -161,6 +161,7 @@ enum hdmi_vic { #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) HDMI_480x320p60_4x3, HDMI_480x800p60_4x3, + HDMI_CUSTOMBUILT, #endif /* diff --git a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h index 453b46eaeeac..0ae433ac54ea 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h +++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h @@ -848,6 +848,9 @@ struct Hdcp_Sub { unsigned int hdcp_sub_addr_start; unsigned int hdcp_sub_len; }; +#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON) +extern struct hdmi_cea_timing *get_custom_timing(void); +#endif extern void setup_attr(const char *buf); extern unsigned int hd_read_reg(unsigned int addr); extern void hd_write_reg(unsigned int addr, unsigned int val);