From 7b43769a169946eec7ac9a7f0403eebbe67732fe Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 31 Mar 2022 16:40:07 +0800 Subject: [PATCH] clk: rockchip: rk3588: Remove CLK_IGNORE_UNUSED for lpll, b0pll and b1pll Signed-off-by: Finley Xiao Change-Id: Iafdd1ae6e545fd018dd4becab0083a60a0570fb1 --- drivers/clk/rockchip/clk-rk3588.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index f9bf956d4848..b5ad51b8df7e 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -644,13 +644,13 @@ static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata = static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p, - CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0), + 0, RK3588_B0_PLL_CON(0), RK3588_BIGCORE0_CLKSEL_CON(0), 6, 15, 0, rk3588_pll_rates), [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p, - CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8), + 0, RK3588_B1_PLL_CON(8), RK3588_BIGCORE1_CLKSEL_CON(0), 6, 15, 0, rk3588_pll_rates), [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, - CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16), + 0, RK3588_LPLL_CON(16), RK3588_DSU_CLKSEL_CON(5), 14, 15, 0, rk3588_pll_rates), [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p, 0, RK3588_PLL_CON(88),