From 7b7167fa0f2d402475e3859cd1b9298fee27896b Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 22 Aug 2017 15:39:17 +0800 Subject: [PATCH] clk: rockchip: rk3368: fix NPLL with NB parameter types RK3066_PLL_RATE_NB with the NB parameter,can adjust the jitter of the output PLL. make the npll jitter is better,make it more suitable for DCLK display. Change-Id: I9d819bdc2b520205a7d63ee8ed83643601ccc821 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3368.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 5fd091973db9..00cf63d64a1f 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -96,6 +96,24 @@ static struct rockchip_pll_rate_table rk3368_pll_rates[] = { { /* sentinel */ }, }; +static struct rockchip_pll_rate_table rk3368_npll_rates[] = { + RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32), + RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32), + RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32), + RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32), + RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32), + RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32), + RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16), + RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32), + RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32), + RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32), + RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32), + RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32), + RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32), + RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32), + RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32), +}; + PNAME(mux_pll_p) = { "xin24m", "xin32k" }; PNAME(mux_armclkb_p) = { "apllb_core", "gpllb_core" }; PNAME(mux_armclkl_p) = { "aplll_core", "gplll_core" }; @@ -148,7 +166,7 @@ static struct rockchip_pll_clock rk3368_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16), RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20), - RK3368_PLL_CON(23), 8, 5, 0, rk3368_pll_rates), + RK3368_PLL_CON(23), 8, 5, 0, rk3368_npll_rates), }; static struct clk_div_table div_ddrphy_t[] = {