diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c index 9829984cecdf..8c33c8c1b20c 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c @@ -778,11 +778,12 @@ void hdmirx_get_vsi_info(struct tvin_sig_property_s *prop) if ((rx.vs_info_details.dolby_vision == true) && (rx.vs_info_details.dolby_timeout <= dv_nopacket_timeout) && - (rx.vs_info_details.dolby_timeout != 0)) + (rx.vs_info_details.dolby_timeout != 0)) { rx.vs_info_details.dolby_timeout--; - if (rx.vs_info_details.dolby_timeout == 0) { - rx.vs_info_details.dolby_vision = false; - rx_pr("dv timeout\n"); + if (rx.vs_info_details.dolby_timeout == 0) { + rx.vs_info_details.dolby_vision = false; + rx_pr("dv type 0x18 timeout\n"); + } } if (log_level & VSI_LOG) { rx_pr("prop->dolby_vision:%d\n", prop->dolby_vision); diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h index 1a070863ecbe..c14642fde7cc 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h @@ -46,7 +46,7 @@ * * */ -#define RX_VER2 "ver.2019/04/02" +#define RX_VER2 "ver.2019/04/07" /*print type*/ #define LOG_EN 0x01 diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_edid.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_edid.c index e103a7a3ee7a..7c24d1164ef4 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_edid.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_edid.c @@ -928,6 +928,7 @@ void rx_edid_fill_to_register( u_int i; u_int checksum = 0; u_int value = 0; + u_int tmp_addr; if (!(pedid && pphy_addr && pchecksum)) return; @@ -944,11 +945,35 @@ void rx_edid_fill_to_register( } /* physical address info at second block */ + if (rx.chip_id < CHIP_ID_TL1) + tmp_addr = TOP_EDID_OFFSET; + else + tmp_addr = TOP_EDID_ADDR_S; for (i = 0; i <= 255; i++) { /* fill first edid buffer */ - hdmirx_wr_top(TOP_EDID_OFFSET + i, pedid[i]); + hdmirx_wr_top(tmp_addr + i, + pedid[i]); /* fill second edid buffer */ - hdmirx_wr_top(TOP_EDID_OFFSET + 0x100 + i, pedid[i]); + hdmirx_wr_top(tmp_addr + 0x100 + i, + pedid[i]); + } + if (rx.chip_id == CHIP_ID_TM2) { + for (i = 0; i <= 255; i++) { + /* fill first edid buffer */ + hdmirx_wr_top(TOP_EDID_PORT2_ADDR_S + i, + pedid[i]); + /* fill second edid buffer */ + hdmirx_wr_top(TOP_EDID_PORT2_ADDR_S + 0x100 + i, + pedid[i]); + } + for (i = 0; i <= 255; i++) { + /* fill first edid buffer */ + hdmirx_wr_top(TOP_EDID_PORT3_ADDR_S + i, + pedid[i]); + /* fill second edid buffer */ + hdmirx_wr_top(TOP_EDID_PORT3_ADDR_S + 0x100 + i, + pedid[i]); + } } /* caculate 4 port check sum */ if (brepeat) { @@ -971,7 +996,7 @@ void rx_edid_update_overlay( u_int *pphy_addr, u_char *pchecksum) { - //u_int i; + u_int tmp_addr; if (!(pphy_addr && pchecksum)) return; @@ -985,6 +1010,13 @@ void rx_edid_update_overlay( (((pphy_addr[E_PORT1] >> 8) & 0xFF)<<8) | (((pphy_addr[E_PORT2] >> 8) & 0xFF)<<16) | (((pphy_addr[E_PORT3] >> 8) & 0xFF)<<24)); + + if (rx.chip_id == CHIP_ID_TM2) { + tmp_addr = TOP_EDID_ADDR_S + phy_addr_offset + 1; + hdmirx_wr_top(tmp_addr, pphy_addr[E_PORT0] >> 8); + hdmirx_wr_top(tmp_addr + 0x200, pphy_addr[E_PORT1] >> 8); + hdmirx_wr_top(tmp_addr + 0x400, pphy_addr[E_PORT2] >> 8); + } /* physical address byte 0 */ hdmirx_wr_top(TOP_EDID_RAM_OVR1, phy_addr_offset | (0x0f<<16)); @@ -993,6 +1025,12 @@ void rx_edid_update_overlay( ((pphy_addr[E_PORT2] & 0xFF)<<16) | ((pphy_addr[E_PORT3] & 0xFF) << 24)); + if (rx.chip_id == CHIP_ID_TM2) { + tmp_addr = TOP_EDID_ADDR_S + phy_addr_offset; + hdmirx_wr_top(tmp_addr, pphy_addr[E_PORT0] & 0xff); + hdmirx_wr_top(tmp_addr + 0x200, pphy_addr[E_PORT1] & 0xff); + hdmirx_wr_top(tmp_addr + 0x400, pphy_addr[E_PORT2] & 0xff); + } /* checksum */ hdmirx_wr_top(TOP_EDID_RAM_OVR0, 0xff | (0x0f<<16)); @@ -1000,6 +1038,12 @@ void rx_edid_update_overlay( pchecksum[E_PORT0]|(pchecksum[E_PORT1]<<8)| (pchecksum[E_PORT2]<<16) | (pchecksum[E_PORT3] << 24)); + if (rx.chip_id == CHIP_ID_TM2) { + tmp_addr = TOP_EDID_ADDR_S + 0xff; + hdmirx_wr_top(tmp_addr, pchecksum[E_PORT0]); + hdmirx_wr_top(tmp_addr + 0x200, pchecksum[E_PORT1]); + hdmirx_wr_top(tmp_addr + 0x400, pchecksum[E_PORT2]); + } /* replace the second edid ram data */ /* physical address byte 1 */ @@ -1197,7 +1241,8 @@ unsigned int hdmi_rx_top_edid_update(void) phy_addr, checksum); if (sts) { /* update physical and checksum */ - rx_edid_update_overlay(phy_addr_offset, phy_addr, checksum); + rx_edid_update_overlay(phy_addr_offset, + phy_addr, checksum); } return 1; } diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c index 10a8d47d2ef0..de8a22cf494b 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c @@ -286,18 +286,15 @@ unsigned int hdmirx_rd_top(unsigned int addr) ulong flags; int data; unsigned int dev_offset = 0; - unsigned int tempaddr = 0; if (rx.chip_id >= CHIP_ID_TL1) { spin_lock_irqsave(®_rw_lock, flags); dev_offset = TOP_DWC_BASE_OFFSET + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr; - if ((addr >= TOP_EDID_OFFSET) && - (addr <= (TOP_EDID_OFFSET + 0x1ff))) { - /*edid address range*/ - tempaddr = TOP_EDID_ADDR_S + (addr - 0x200); + if ((addr >= TOP_EDID_ADDR_S) && + (addr <= (TOP_EDID_PORT3_ADDR_E))) { data = rd_reg_b(MAP_ADDR_MODULE_TOP, - dev_offset + tempaddr); + dev_offset + addr); } else { data = rd_reg(MAP_ADDR_MODULE_TOP, dev_offset + (addr<<2)); @@ -335,18 +332,15 @@ void hdmirx_wr_top(unsigned int addr, unsigned int data) { ulong flags; unsigned long dev_offset = 0; - unsigned int tempaddr = 0; if (rx.chip_id >= CHIP_ID_TL1) { spin_lock_irqsave(®_rw_lock, flags); dev_offset = TOP_DWC_BASE_OFFSET + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr; - if ((addr >= TOP_EDID_OFFSET) && - (addr <= (TOP_EDID_OFFSET + 0x1ff))) { - /*edid address range*/ - tempaddr = TOP_EDID_ADDR_S + (addr - 0x200); + if ((addr >= TOP_EDID_ADDR_S) && + (addr <= (TOP_EDID_PORT3_ADDR_E))) { wr_reg_b(MAP_ADDR_MODULE_TOP, - dev_offset + tempaddr, (unsigned char)data); + dev_offset + addr, (unsigned char)data); } else { wr_reg(MAP_ADDR_MODULE_TOP, dev_offset + (addr<<2), data); @@ -3159,15 +3153,54 @@ void dump_edid_reg(void) rx_pr("0x4 1.4 edid with 420 video data\n"); rx_pr("0x5 2.0 edid with HDR,DV,420\n"); rx_pr("********************************\n"); - - for (i = 0; i < 16; i++) { - rx_pr("[%2d] ", i); - for (j = 0; j < 16; j++) { - rx_pr("0x%02lx, ", - hdmirx_rd_top(TOP_EDID_OFFSET + - (i * 16 + j))); + if (rx.chip_id < CHIP_ID_TL1) { + for (i = 0; i < 16; i++) { + rx_pr("[%2d] ", i); + for (j = 0; j < 16; j++) { + rx_pr("0x%02lx, ", + hdmirx_rd_top(TOP_EDID_OFFSET + + (i * 16 + j))); + } + rx_pr("\n"); + } + } else if (rx.chip_id == CHIP_ID_TL1) { + for (i = 0; i < 16; i++) { + rx_pr("[%2d] ", i); + for (j = 0; j < 16; j++) { + rx_pr("0x%02lx, ", + hdmirx_rd_top(TOP_EDID_ADDR_S + + (i * 16 + j))); + } + rx_pr("\n"); + } + } else { + for (i = 0; i < 16; i++) { + rx_pr("[%2d] ", i); + for (j = 0; j < 16; j++) { + rx_pr("0x%02lx, ", + hdmirx_rd_top(TOP_EDID_ADDR_S + + (i * 16 + j))); + } + rx_pr("\n"); + } + for (i = 0; i < 16; i++) { + rx_pr("[%2d] ", i); + for (j = 0; j < 16; j++) { + rx_pr("0x%02lx, ", + hdmirx_rd_top(TOP_EDID_PORT2_ADDR_S + + (i * 16 + j))); + } + rx_pr("\n"); + } + for (i = 0; i < 16; i++) { + rx_pr("[%2d] ", i); + for (j = 0; j < 16; j++) { + rx_pr("0x%02lx, ", + hdmirx_rd_top(TOP_EDID_PORT3_ADDR_S + + (i * 16 + j))); + } + rx_pr("\n"); } - rx_pr("\n"); } } diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h index 7184d16ee5a5..4b1e000cd418 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h @@ -261,6 +261,8 @@ #define TOP_DUK_3 0x06d #define TOP_NSEC_SCRATCH 0x06e #define TOP_SEC_SCRATCH 0x06f +#define TOP_EDID_OFFSET 0x200 + /* TL1 */ #define TOP_EMP_DDR_START_A 0x070 #define TOP_EMP_DDR_START_B 0x071 @@ -282,15 +284,20 @@ #define TOP_MISC_STAT0 0x084 #define TOP_EDID_ADDR_S 0x1000 #define TOP_EDID_ADDR_E 0x11ff + +/* TM2 */ +#define TOP_EDID_PORT2_ADDR_S 0x1200 +#define TOP_EDID_PORT2_ADDR_E 0x13ff +#define TOP_EDID_PORT3_ADDR_S 0x1400 +#define TOP_EDID_PORT3_ADDR_E 0x15ff + + #define TOP_DWC_BASE_OFFSET 0x8000 #define TOP_DONT_TOUCH0 0x0fe #define TOP_DONT_TOUCH1 0x0ff -/* hdmi2.0 new end */ -#define TOP_EDID_OFFSET 0x200 - /* * HDMI registers */ diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c index 085433dac48f..c3db51d4acc3 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c @@ -1362,7 +1362,7 @@ void rx_get_vsi_info(void) rx.vs_info_details._3d_ext_data = 0; rx.vs_info_details.low_latency = false; rx.vs_info_details.backlt_md_bit = false; - rx.vs_info_details.dolby_timeout = 0xffff; + /* rx.vs_info_details.dolby_timeout = 0xffff; */ if ((pkt->length == E_DV_LENGTH_27) && (pkt->ieee == 0x00d046)) { /* dolby1.5 */ @@ -1381,9 +1381,11 @@ void rx_get_vsi_info(void) /* dobly10 */ if (pkt->length == E_DV_LENGTH_24) { rx.vs_info_details.dolby_vision = true; - if ((pkt->sbpkt.payload.data[0] & 0xffff) == 0) + if ((pkt->sbpkt.payload.data[0] & 0xffff) == 0) { rx.vs_info_details.dolby_timeout = dv_nopacket_timeout; + pkt->sbpkt.payload.data[0] = 0xffff; + } } else if ((pkt->length == E_DV_LENGTH_5) && (pkt->sbpkt.payload.data[0] & 0xffff)) { rx.vs_info_details.dolby_vision = false; diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c index b323eff37b87..b5d67336311f 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c @@ -2876,7 +2876,7 @@ void hdmirx_timer_handler(unsigned long arg) rx_clkrate_monitor(); rx_main_state_machine(); } - rx_pkt_check_content(); + /* rx_pkt_check_content(); */ rx_err_monitor(); #ifdef K_TEST_CHK_ERR_CNT if (err_chk_en)