From 7bc0d73f22abf63d9b81a3dfcec47f083d9d1c0a Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Thu, 19 Dec 2024 09:50:57 +0800 Subject: [PATCH] drm/rockchip: bridge: analogix_dp: fix the regs settings for TEST_PATTERN_80BIT According to the DP PHY CTS v1.2b 3.2.3 and 3.3.3 chapters, the PreEmphasis Level Test Pattern(PLTPAT), which also was called 80-bit custom pattern, should be: 1111100000 1111100000 1111100000 1111100000 1111100000 1111100000 1111100000 1111100000 It is used to verify the HBR2 in "Non Pre-Emphasis Level Verification Testing" and "Pre-Emphasis Level Verification and Maximum Pk-Pk Differential Voltage Testing". Without this patch, the PLTPAT pattern is incorrect. Fixes: 304dbb104da1 ("drm/bridge: analogix_dp: Add DP Test Automation") Change-Id: I4b00acd0a360a8ba3f3eaf32fb30e0a18a451f5c Signed-off-by: Damon Ding --- drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c index 83ff85d873a9..8b89e45d2fda 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -738,9 +738,9 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, case TEST_PATTERN_80BIT: reg = 0x3e0f83e0; analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN0, reg); - reg = 0x0f83e0f8; + reg = 0x3e0f83e0; analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN1, reg); - reg = 0x0000f83e; + reg = 0x000f83e0; analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN2, reg); reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_80BIT; analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);