From 7bf7b500bfd19dd79ceb7ab08fdc9722fa40ca8e Mon Sep 17 00:00:00 2001 From: Peter Wang Date: Thu, 23 Jun 2022 11:50:47 +0800 Subject: [PATCH] FROMGIT: scsi: ufs: ufs-mediatek: Prevent host hang by setting CLK_CG early Some UFSHCI hosts in MediaTek UFS platform need workaround to prevent host hang issue by setting CLK_CG bit before host is enabled. This operation shall have no side effect on those platforms which do not support this bit. Link: https://lore.kernel.org/r/20220623035052.18802-4-stanley.chu@mediatek.com Reviewed-by: Stanley Chu Reviewed-by: Bart Van Assche Signed-off-by: Peter Wang Signed-off-by: Stanley Chu Signed-off-by: Martin K. Petersen (cherry picked from commit 2bae03a6ac985fe80a7a228af3bcc2d5dbe43381 git://git.kernel.org/pub/scm/linux/kernel/git/mkp/scsi.git for-next) Bug: 239946304 Signed-off-by: Bart Van Assche Change-Id: I1250357f44930a75f9873ae064cbfdfbb365fe64 --- drivers/ufs/host/ufs-mediatek.c | 8 ++++++++ drivers/ufs/host/ufs-mediatek.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index b8f2a74d2a51..b15351c2235b 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -183,6 +183,14 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT; hba->ahit = 0; } + + /* + * Turn on CLK_CG early to bypass abnormal ERR_CHK signal + * to prevent host hang issue + */ + ufshcd_writel(hba, + ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80, + REG_UFS_XOUFS_CTRL); } return 0; diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h index 49a2137fb251..f5c1c643dd52 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -12,6 +12,7 @@ /* * Vendor specific UFSHCI Registers */ +#define REG_UFS_XOUFS_CTRL 0x140 #define REG_UFS_REFCLK_CTRL 0x144 #define REG_UFS_EXTREG 0x2100 #define REG_UFS_MPHYCTRL 0x2200