diff --git a/drivers/video/rockchip/rga3/include/rga2_reg_info.h b/drivers/video/rockchip/rga3/include/rga2_reg_info.h index cd84951aa0ff..0cbf924ba1ee 100644 --- a/drivers/video/rockchip/rga3/include/rga2_reg_info.h +++ b/drivers/video/rockchip/rga3/include/rga2_reg_info.h @@ -4,32 +4,95 @@ #include "rga_drv.h" -#define RGA2_USE_MASTER_MODE 1 +#define RGA2_USE_MASTER_MODE 1 -/* General Registers */ -#define RGA2_SYS_CTRL 0x000 -#define RGA2_CMD_CTRL 0x004 -#define RGA2_CMD_BASE 0x008 -#define RGA2_STATUS 0x00c -#define RGA2_INT 0x010 -#define RGA2_MMU_CTRL0 0x018 -#define RGA2_MMU_CMD_BASE 0x01c -#define RGA2_VERSION_NUM 0x028 +#define RGA2_SYS_REG_BASE 0x000 +#define RGA2_CSC_REG_BASE 0x060 +#define RGA2_CMD_REG_BASE 0x100 -#define rRGA_SYS_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_SYS_CTRL_OFFSET)) -#define rRGA_CMD_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_CTRL_OFFSET)) -#define rRGA_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_BASE_OFFSET)) -#define rRGA_STATUS (*(volatile u32 *)(RGA2_BASE + RGA2_STATUS_OFFSET)) -#define rRGA_INT (*(volatile u32 *)(RGA2_BASE + RGA2_INT_OFFSET)) -#define rRGA_MMU_CTRL0 (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CTRL0_OFFSET)) -#define rRGA_MMU_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CMD_BASE_OFFSET)) -#define rRGA_CMD_ADDR (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_ADDR)) -#define rRGA_READ_LINE_CNT_TH (*(volatile u32 *)(RGA2_BASE + RGA2_READ_LINE_CNT_OFFSET)) -#define rRGA_WRITE_LINE_CNT_TH (*(volatile u32 *)(RGA2_BASE + RGA2_WRITE_LINE_CNT_OFFSET)) -#define rRGA_INT_LINE_CNT (*(volatile u32 *)(RGA2_BASE + RGA2_LINE_CNT_OFFSET)) -#define rRGA_PERF_CTRL0 (*(volatile u32 *)(RGA2_BASE + RGA2_PERF_CTRL0_OFFSET)) -#define rRGA_OSD_CUR_FLAGS0 (*(volatile u32 *)(RGA2_BASE + RGA2_OSD_CUR_FLAGS0)) -#define rRGA_OSD_CUR_FLAGS1 (*(volatile u32 *)(RGA2_BASE + RGA2_OSD_CUR_FLAGS1)) +/* sys reg */ +#define RGA2_SYS_CTRL 0x000 +#define RGA2_CMD_CTRL 0x004 +#define RGA2_CMD_BASE 0x008 +#define RGA2_STATUS1 0x00c +#define RGA2_INT 0x010 +#define RGA2_MMU_CTRL0 0x014 +#define RGA2_MMU_CMD_BASE 0x018 +#define RGA2_STATUS2 0x01c +#define RGA2_VERSION_NUM 0x028 +#define RGA2_READ_LINE_CNT 0x030 +#define RGA2_WRITE_LINE_CNT 0x034 +#define RGA2_LINE_CNT 0x038 +#define RGA2_PERF_CTRL0 0x040 + +/* full csc reg */ +#define RGA2_DST_CSC_00 0x060 +#define RGA2_DST_CSC_01 0x064 +#define RGA2_DST_CSC_02 0x068 +#define RGA2_DST_CSC_OFF0 0x06c +#define RGA2_DST_CSC_10 0x070 +#define RGA2_DST_CSC_11 0x074 +#define RGA2_DST_CSC_12 0x078 +#define RGA2_DST_CSC_OFF1 0x07c +#define RGA2_DST_CSC_20 0x080 +#define RGA2_DST_CSC_21 0x084 +#define RGA2_DST_CSC_22 0x088 +#define RGA2_DST_CSC_OFF2 0x08c + +/* osd read-back reg */ +#define RGA2_OSD_CUR_FLAGS0 0x090 +#define RGA2_OSD_CUR_FLAGS1 0x09c + +/* mode ctrl */ +#define RGA2_MODE_CTRL_OFFSET 0x000 +#define RGA2_SRC_INFO_OFFSET 0x004 +#define RGA2_SRC_BASE0_OFFSET 0x008 +#define RGA2_SRC_BASE1_OFFSET 0x00c +#define RGA2_SRC_BASE2_OFFSET 0x010 +#define RGA2_SRC_BASE3_OFFSET 0x014 +#define RGA2_SRC_VIR_INFO_OFFSET 0x018 +#define RGA2_SRC_ACT_INFO_OFFSET 0x01c +#define RGA2_SRC_X_FACTOR_OFFSET 0x020 +#define RGA2_OSD_CTRL0_OFFSET 0x020 // repeat +#define RGA2_SRC_Y_FACTOR_OFFSET 0x024 +#define RGA2_OSD_CTRL1_OFFSET 0x024 // repeat +#define RGA2_SRC_BG_COLOR_OFFSET 0x028 +#define RGA2_OSD_COLOR0_OFFSET 0x028 // repeat +#define RGA2_SRC_FG_COLOR_OFFSET 0x02c +#define RGA2_OSD_COLOR1_OFFSET 0x02c // repeat +#define RGA2_SRC_TR_COLOR0_OFFSET 0x030 +#define RGA2_CF_GR_A_OFFSET 0x030 // repeat +#define RGA2_OSD_LAST_FLAGS0_OFFSET 0x030 // repeat +#define RGA2_MOSAIC_MODE_OFFSET 0x030 // repeat +#define RGA2_SRC_TR_COLOR1_OFFSET 0x034 +#define RGA2_CF_GR_B_OFFSET 0x034 // repeat +#define RGA2_OSD_LAST_FLAGS1_OFFSET 0x034 // repeat +#define RGA2_DST_INFO_OFFSET 0x038 +#define RGA2_DST_BASE0_OFFSET 0x03c +#define RGA2_DST_BASE1_OFFSET 0x040 +#define RGA2_DST_BASE2_OFFSET 0x044 +#define RGA2_DST_VIR_INFO_OFFSET 0x048 +#define RGA2_DST_ACT_INFO_OFFSET 0x04c +#define RGA2_ALPHA_CTRL0_OFFSET 0x050 +#define RGA2_ALPHA_CTRL1_OFFSET 0x054 +#define RGA2_FADING_CTRL_OFFSET 0x058 +#define RGA2_PAT_CON_OFFSET 0x05c +#define RGA2_ROP_CTRL0_OFFSET 0x060 +#define RGA2_CF_GR_G_OFFSET 0x060 // repeat +#define RGA2_DST_Y4MAP_LUT0_OFFSET 0x060 // repeat +#define RGA2_DST_QUANTIZE_SCALE_OFFSET 0x060 // repeat +#define RGA2_OSD_INVERTSION_CAL0_OFFSET 0x060 // repeat +#define RGA2_ROP_CTRL1_OFFSET 0x064 +#define RGA2_CF_GR_R_OFFSET 0x064 // repeat +#define RGA2_DST_Y4MAP_LUT1_OFFSET 0x064 // repeat +#define RGA2_DST_QUANTIZE_OFFSET_OFFSET 0x064 // repeat +#define RGA2_OSD_INVERTSION_CAL1_OFFSET 0x064 // repeat +#define RGA2_MASK_BASE_OFFSET 0x068 +#define RGA2_MMU_CTRL1_OFFSET 0x06c +#define RGA2_MMU_SRC_BASE_OFFSET 0x070 +#define RGA2_MMU_SRC1_BASE_OFFSET 0x074 +#define RGA2_MMU_DST_BASE_OFFSET 0x078 +#define RGA2_MMU_ELS_BASE_OFFSET 0x07c /*RGA_SYS*/ #define m_RGA2_SYS_HOLD_MODE_EN (1 << 9) @@ -37,6 +100,11 @@ #define s_RGA2_SYS_HOLD_MODE_EN(x) ((x & 0x1) << 9) #define s_RGA2_SYS_CMD_CONTINUE(x) ((x & 0x1) << 10) +/* RGA_STATUS1 */ +#define m_RGA2_STATUS1_SW_CMD_TOTAL_NUM (0xfff << 8) +#define m_RGA2_STATUS1_SW_CMD_CUR_NUM (0xfff << 8) +#define m_RGA2_STATUS1_SW_RGA_STA (0x1 << 0) + /*RGA_INT*/ #define m_RGA2_INT_LINE_WR_CLEAR (1 << 16) #define m_RGA2_INT_LINE_RD_CLEAR (1 << 15) @@ -325,88 +393,6 @@ #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_EN(x) ((x & 0x1) << 12) #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH(x) ((x & 0x1) << 13) -/* sys ctrl */ -#define RGA2_SYS_CTRL_OFFSET 0x0 -#define RGA2_CMD_CTRL_OFFSET 0x4 -#define RGA2_CMD_BASE_OFFSET 0x8 -#define RGA2_STATUS_OFFSET 0xc -#define RGA2_INT_OFFSET 0x10 -#define RGA2_MMU_CTRL0_OFFSET 0x14 -#define RGA2_MMU_CMD_BASE_OFFSET 0x18 -#define RGA2_READ_LINE_CNT_OFFSET 0x30 -#define RGA2_WRITE_LINE_CNT_OFFSET 0x34 -#define RGA2_LINE_CNT_OFFSET 0x38 -#define RGA2_PERF_CTRL0_OFFSET 0x40 -#define RGA2_DST_CSC_00_OFFSET 0x60 -#define RGA2_DST_CSC_01_OFFSET 0x64 -#define RGA2_DST_CSC_02_OFFSET 0x68 -#define RGA2_DST_CSC_OFF0_OFFSET 0x6c -#define RGA2_DST_CSC_10_OFFSET 0x70 -#define RGA2_DST_CSC_11_OFFSET 0x74 -#define RGA2_DST_CSC_12_OFFSET 0x78 -#define RGA2_DST_CSC_OFF1_OFFSET 0x7c -#define RGA2_DST_CSC_20_OFFSET 0x80 -#define RGA2_DST_CSC_21_OFFSET 0x84 -#define RGA2_DST_CSC_22_OFFSET 0x88 -#define RGA2_DST_CSC_OFF2_OFFSET 0x8c -#define RGA2_OSD_CUR_FLAGS0_OFFSET 0x90 -#define RGA2_OSD_CUR_FLAGS1_OFFSET 0x9c - -/* mode ctrl */ -#define RGA2_MODE_CTRL_OFFSET 0x00 -#define RGA2_SRC_INFO_OFFSET 0x04 -#define RGA2_SRC_BASE0_OFFSET 0x08 -#define RGA2_SRC_BASE1_OFFSET 0x0c -#define RGA2_SRC_BASE2_OFFSET 0x10 -#define RGA2_SRC_BASE3_OFFSET 0x14 -#define RGA2_SRC_VIR_INFO_OFFSET 0x18 -#define RGA2_SRC_ACT_INFO_OFFSET 0x1c -#define RGA2_SRC_X_FACTOR_OFFSET 0x20 -#define RGA2_OSD_CTRL0_OFFSET 0x20 // repeat -#define RGA2_SRC_Y_FACTOR_OFFSET 0x24 -#define RGA2_OSD_CTRL1_OFFSET 0x24 // repeat -#define RGA2_SRC_BG_COLOR_OFFSET 0x28 -#define RGA2_OSD_COLOR0_OFFSET 0x28 // repeat -#define RGA2_SRC_FG_COLOR_OFFSET 0x2c -#define RGA2_OSD_COLOR1_OFFSET 0x2c // repeat -#define RGA2_SRC_TR_COLOR0_OFFSET 0x30 -#define RGA2_CF_GR_A_OFFSET 0x30 // repeat -#define RGA2_OSD_LAST_FLAGS0_OFFSET 0x30 // repeat -#define RGA2_MOSAIC_MODE_OFFSET 0x30 // repeat -#define RGA2_SRC_TR_COLOR1_OFFSET 0x34 -#define RGA2_CF_GR_B_OFFSET 0x34 // repeat -#define RGA2_OSD_LAST_FLAGS1_OFFSET 0x34 // repeat -#define RGA2_DST_INFO_OFFSET 0x38 -#define RGA2_DST_BASE0_OFFSET 0x3c -#define RGA2_DST_BASE1_OFFSET 0x40 -#define RGA2_DST_BASE2_OFFSET 0x44 -#define RGA2_DST_VIR_INFO_OFFSET 0x48 -#define RGA2_DST_ACT_INFO_OFFSET 0x4c -#define RGA2_ALPHA_CTRL0_OFFSET 0x50 -#define RGA2_ALPHA_CTRL1_OFFSET 0x54 -#define RGA2_FADING_CTRL_OFFSET 0x58 -#define RGA2_PAT_CON_OFFSET 0x5c -#define RGA2_ROP_CTRL0_OFFSET 0x60 -#define RGA2_CF_GR_G_OFFSET 0x60 // repeat -#define RGA2_DST_Y4MAP_LUT0_OFFSET 0x60 // repeat -#define RGA2_DST_QUANTIZE_SCALE_OFFSET 0x60 // repeat -#define RGA2_OSD_INVERTSION_CAL0_OFFSET 0x60 // repeat -#define RGA2_ROP_CTRL1_OFFSET 0x64 -#define RGA2_CF_GR_R_OFFSET 0x64 // repeat -#define RGA2_DST_Y4MAP_LUT1_OFFSET 0x64 // repeat -#define RGA2_DST_QUANTIZE_OFFSET_OFFSET 0x64 // repeat -#define RGA2_OSD_INVERTSION_CAL1_OFFSET 0x64 // repeat -#define RGA2_MASK_BASE_OFFSET 0x68 -#define RGA2_MMU_CTRL1_OFFSET 0x6c -#define RGA2_MMU_SRC_BASE_OFFSET 0x70 -#define RGA2_MMU_SRC1_BASE_OFFSET 0x74 -#define RGA2_MMU_DST_BASE_OFFSET 0x78 -#define RGA2_MMU_ELS_BASE_OFFSET 0x7c - -#define RGA2_SYS_REG_BASE 0x0 -#define RGA2_CSC_REG_BASE 0x60 -#define RGA2_CMD_REG_BASE 0x100 - int rga2_gen_reg_info(unsigned char *base, struct rga2_req *msg); void rga2_soft_reset(struct rga_scheduler_t *scheduler); diff --git a/drivers/video/rockchip/rga3/include/rga3_reg_info.h b/drivers/video/rockchip/rga3/include/rga3_reg_info.h index d8eba9f06ad7..2267e4531ed9 100644 --- a/drivers/video/rockchip/rga3/include/rga3_reg_info.h +++ b/drivers/video/rockchip/rga3/include/rga3_reg_info.h @@ -4,442 +4,423 @@ #include "rga_drv.h" -//General Registers -/* yqw: status和int寄存器尚不明了，无法进行修改。 */ -//#define RGA2_STATUS 0x00c -//#define RGA2_INT 0x010 +/* sys reg */ +#define RGA3_SYS_CTRL 0x000 +#define RGA3_CMD_CTRL 0x004 +#define RGA3_CMD_ADDR 0x008 +#define RGA3_MI_GROUP_CTRL 0x00c +#define RGA3_ARQOS_CTRL 0x010 +#define RGA3_VERSION_NUM 0x018 +#define RGA3_VERSION_TIM 0x01c +#define RGA3_INT_EN 0x020 +#define RGA3_INT_RAW 0x024 +#define RGA3_INT_MSK 0x028 +#define RGA3_INT_CLR 0x02c +#define RGA3_RO_SRST 0x030 +#define RGA3_STATUS0 0x034 +#define RGA3_SCAN_CNT 0x038 +#define RGA3_CMD_STATE 0x040 -#define RGA3_SYS_CTRL 0x000 -#define RGA3_CMD_CTRL 0x004 -#define RGA3_CMD_ADDR 0x008 -#define RGA3_MI_GROUP_CTRL 0x00c -#define RGA3_ARQOS_CTRL 0x010 -#define RGA3_VERSION_NUM 0x018 -#define RGA3_VERSION_TIM 0x01c -#define RGA3_INT_EN 0x020 -#define RGA3_INT_RAW 0x024 -#define RGA3_INT_MSK 0x028 -#define RGA3_INT_CLR 0x02c -#define RGA3_RO_SRST 0x030 -#define RGA3_STATUS0 0x034 -#define RGA3_SCAN_CNT 0x038 -#define RGA3_STATUS1 0x03c -#define RGA3_CMD_STATE 0x040 +/* cmd reg */ +#define RGA3_WIN0_RD_CTRL_OFFSET 0x000 +#define RGA3_WIN0_Y_BASE_OFFSET 0x010 +#define RGA3_WIN0_U_BASE_OFFSET 0x014 +#define RGA3_WIN0_V_BASE_OFFSET 0x018 +#define RGA3_WIN0_VIR_STRIDE_OFFSET 0x01c +#define RGA3_WIN0_FBC_OFF_OFFSET 0x020 +#define RGA3_WIN0_SRC_SIZE_OFFSET 0x024 +#define RGA3_WIN0_ACT_OFF_OFFSET 0x028 +#define RGA3_WIN0_ACT_SIZE_OFFSET 0x02c +#define RGA3_WIN0_DST_SIZE_OFFSET 0x030 +#define RGA3_WIN0_SCL_FAC_OFFSET 0x034 +#define RGA3_WIN0_UV_VIR_STRIDE_OFFSET 0x038 +#define RGA3_WIN1_RD_CTRL_OFFSET 0x040 +#define RGA3_WIN1_Y_BASE_OFFSET 0x050 +#define RGA3_WIN1_U_BASE_OFFSET 0x054 +#define RGA3_WIN1_V_BASE_OFFSET 0x058 +#define RGA3_WIN1_VIR_STRIDE_OFFSET 0x05c +#define RGA3_WIN1_FBC_OFF_OFFSET 0x060 +#define RGA3_WIN1_SRC_SIZE_OFFSET 0x064 +#define RGA3_WIN1_ACT_OFF_OFFSET 0x068 +#define RGA3_WIN1_ACT_SIZE_OFFSET 0x06c +#define RGA3_WIN1_DST_SIZE_OFFSET 0x070 +#define RGA3_WIN1_SCL_FAC_OFFSET 0x074 +#define RGA3_WIN1_UV_VIR_STRIDE_OFFSET 0x078 +#define RGA3_OVLP_CTRL_OFFSET 0x080 +#define RGA3_OVLP_OFF_OFFSET 0x084 +#define RGA3_OVLP_TOP_KEY_MIN_OFFSET 0x088 +#define RGA3_OVLP_TOP_KEY_MAX_OFFSET 0x08c +#define RGA3_OVLP_TOP_CTRL_OFFSET 0x090 +#define RGA3_OVLP_BOT_CTRL_OFFSET 0x094 +#define RGA3_OVLP_TOP_ALPHA_OFFSET 0x098 +#define RGA3_OVLP_BOT_ALPHA_OFFSET 0x09c +#define RGA3_WR_CTRL_OFFSET 0x0a0 +#define RGA3_WR_FBCE_CTRL_OFFSET 0x0a4 +#define RGA3_WR_VIR_STRIDE_OFFSET 0x0a8 +#define RGA3_WR_PL_VIR_STRIDE_OFFSET 0x0ac +#define RGA3_WR_Y_BASE_OFFSET 0x0b0 +#define RGA3_WR_U_BASE_OFFSET 0x0b4 +#define RGA3_WR_V_BASE_OFFSET 0x0b8 +#define RGA3_MMU_DTE_ADDR_OFFSET 0xf00 +#define RGA3_MMU_STATUS_OFFSET 0xf04 +#define RGA3_MMU_COMMAND_OFFSET 0xf08 +#define RGA3_MMU_PAGE_FAULT_ADDR_OFFSET 0xf0c +#define RGA3_MMU_ZAP_ONE_LINE_OFFSET 0xf10 +#define RGA3_MMU_INT_RAWSTAT_OFFSET 0xf14 +#define RGA3_MMU_INT_CLEAR_OFFSET 0xf18 +#define RGA3_MMU_INT_MASK_OFFSET 0xf1c +#define RGA3_MMU_INT_STATUS_OFFSET 0xf20 +#define RGA3_MMU_AUTO_GATING_OFFSET 0xf24 +#define RGA3_MMU_REG_LOAD_EN_OFFSET 0xf28 /* TODO: RGA_INT */ +/* RGA3_CMD_STATE */ +#define m_RGA3_CMD_STATE_CMD_CNT_CUR (0xfff << 16) +#define m_RGA3_CMD_STATE_CMD_WORKING (0x1 << 0) + /* RGA3_WIN0_RD_CTRL */ -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ENABLE (0x1 << 0) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_MODE (0x3 << 1) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_PIC_FORMAT (0xf << 4) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_FORMAT (0x3 << 8) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YUV10B_COMPACT (0x1 << 10) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ENDIAN_MODE (0x1 << 11) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ENABLE (0x1 << 0) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_MODE (0x3 << 1) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_PIC_FORMAT (0xf << 4) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_FORMAT (0x3 << 8) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YUV10B_COMPACT (0x1 << 10) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ENDIAN_MODE (0x1 << 11) #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_PIX_SWAP (0x1 << 12) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YC_SWAP (0x1 << 13) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT (0x1 << 16) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_XMIRROR (0x1 << 17) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR (0x1 << 18) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY (0x1 << 20) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP (0x1 << 21) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY (0x1 << 22) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP (0x1 << 23) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_Y2R_EN (0x1 << 24) -#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_R2Y_EN (0x1 << 25) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YC_SWAP (0x1 << 13) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT (0x1 << 16) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_XMIRROR (0x1 << 17) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR (0x1 << 18) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY (0x1 << 20) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP (0x1 << 21) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY (0x1 << 22) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP (0x1 << 23) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_Y2R_EN (0x1 << 24) +#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_R2Y_EN (0x1 << 25) #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_CSC_MODE (0x3 << 26) #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_PERF_OPT_DIS (0x1 << 29) #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_ALIGN_DIS (0x1 << 30) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ENABLE(x) ((x & 0x1) << 0) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_MODE(x) ((x & 0x3) << 1) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PIC_FORMAT(x) ((x & 0xf) << 4) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ENABLE(x) ((x & 0x1) << 0) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_MODE(x) ((x & 0x3) << 1) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PIC_FORMAT(x) ((x & 0xf) << 4) #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_FORMAT(x) ((x & 0x3) << 8) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YUV10B_COMPACT(x) ((x & 0x1) << 10) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ENDIAN_MODE(x) ((x & 0x1) << 11) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PIX_SWAP(x) ((x & 0x1) << 12) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YC_SWAP(x) ((x & 0x1) << 13) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT(x) ((x & 0x1) << 16) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_XMIRROR(x) ((x & 0x1) << 17) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR(x) ((x & 0x1) << 18) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY(x) ((x & 0x1) << 20) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP(x) ((x & 0x1) << 21) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY(x) ((x & 0x1) << 22) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP(x) ((x & 0x1) << 23) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_Y2R_EN(x) ((x & 0x1) << 24) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_R2Y_EN(x) ((x & 0x1) << 25) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_CSC_MODE(x) ((x & 0x3) << 26) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PERF_OPT_DIS(x) ((x & 0x1) << 29) -#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_ALIGN_DIS(x) ((x & 0x1) << 30) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YUV10B_COMPACT(x) ((x & 0x1) << 10) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ENDIAN_MODE(x) ((x & 0x1) << 11) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PIX_SWAP(x) ((x & 0x1) << 12) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YC_SWAP(x) ((x & 0x1) << 13) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT(x) ((x & 0x1) << 16) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_XMIRROR(x) ((x & 0x1) << 17) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR(x) ((x & 0x1) << 18) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY(x) ((x & 0x1) << 20) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP(x) ((x & 0x1) << 21) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY(x) ((x & 0x1) << 22) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP(x) ((x & 0x1) << 23) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_Y2R_EN(x) ((x & 0x1) << 24) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_R2Y_EN(x) ((x & 0x1) << 25) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_CSC_MODE(x) ((x & 0x3) << 26) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PERF_OPT_DIS(x) ((x & 0x1) << 29) +#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_ALIGN_DIS(x) ((x & 0x1) << 30) /* RGA3_WIN0_FBC_OFF */ #define m_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_XOFF (0x1fff << 0) #define m_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_YOFF (0x1fff << 16) -#define s_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_XOFF(x) ((x & 0x1fff) << 0) -#define s_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_YOFF(x) ((x & 0x1fff) << 16) +#define s_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_XOFF(x) ((x & 0x1fff) << 0) +#define s_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_YOFF(x) ((x & 0x1fff) << 16) /* RGA3_WIN0_SRC_SIZE */ -#define m_RGA3_WIN0_SRC_SIZE_SW_WIN0_SRC_WIDTH (0x1fff << 0) -#define m_RGA3_WIN0_SRC_SIZE_SW_WIN0_SRC_HEIGHT (0x1fff << 16) +#define m_RGA3_WIN0_SRC_SIZE_SW_WIN0_SRC_WIDTH (0x1fff << 0) +#define m_RGA3_WIN0_SRC_SIZE_SW_WIN0_SRC_HEIGHT (0x1fff << 16) -#define s_RGA3_WIN0_SRC_OFF_SW_WIN0_SRC_WIDTH(x) ((x & 0x1fff) << 0) -#define s_RGA3_WIN0_SRC_OFF_SW_WIN0_SRC_HEIGHT(x) ((x & 0x1fff) << 16) +#define s_RGA3_WIN0_SRC_OFF_SW_WIN0_SRC_WIDTH(x) ((x & 0x1fff) << 0) +#define s_RGA3_WIN0_SRC_OFF_SW_WIN0_SRC_HEIGHT(x) ((x & 0x1fff) << 16) /* RGA3_WIN0_ACT_OFF */ #define m_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_XOFF (0x1fff << 0) #define m_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_YOFF (0x1fff << 16) -#define s_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_XOFF(x) ((x & 0x1fff) << 0) -#define s_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_YOFF(x) ((x & 0x1fff) << 16) +#define s_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_XOFF(x) ((x & 0x1fff) << 0) +#define s_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_YOFF(x) ((x & 0x1fff) << 16) /* RGA3_WIN0_ACT_SIZE */ -#define m_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_WIDTH (0x1fff << 0) -#define m_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_HEIGHT (0x1fff << 16) +#define m_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_WIDTH (0x1fff << 0) +#define m_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_HEIGHT (0x1fff << 16) -#define s_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_WIDTH(x) ((x & 0x1fff) << 0) -#define s_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_HEIGHT(x) ((x & 0x1fff) << 16) +#define s_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_WIDTH(x) ((x & 0x1fff) << 0) +#define s_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_HEIGHT(x) ((x & 0x1fff) << 16) /* RGA3_WIN0_DST_SIZE */ -#define m_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_WIDTH (0x1fff << 0) -#define m_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_HEIGHT (0x1fff << 16) +#define m_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_WIDTH (0x1fff << 0) +#define m_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_HEIGHT (0x1fff << 16) -#define s_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_WIDTH(x) ((x & 0x1fff) << 0) -#define s_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_HEIGHT(x) ((x & 0x1fff) << 16) +#define s_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_WIDTH(x) ((x & 0x1fff) << 0) +#define s_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_HEIGHT(x) ((x & 0x1fff) << 16) /* RGA3_WIN0_SCL_FAC */ -#define m_RGA3_WIN0_SCL_FAC_SW_WIN0_VER_FAC (0xffff << 0) -#define m_RGA3_WIN0_SCL_FAC_SW_WIN0_HOR_FAC (0xffff << 16) +#define m_RGA3_WIN0_SCL_FAC_SW_WIN0_VER_FAC (0xffff << 0) +#define m_RGA3_WIN0_SCL_FAC_SW_WIN0_HOR_FAC (0xffff << 16) -#define s_RGA3_WIN0_SCL_FAC_SW_WIN0_VER_FAC(x) ((x & 0xffff) << 0) -#define s_RGA3_WIN0_SCL_FAC_SW_WIN0_HOR_FAC(x) ((x & 0xffff) << 16) +#define s_RGA3_WIN0_SCL_FAC_SW_WIN0_VER_FAC(x) ((x & 0xffff) << 0) +#define s_RGA3_WIN0_SCL_FAC_SW_WIN0_HOR_FAC(x) ((x & 0xffff) << 16) /* RGA3_WIN1_RD_CTRL */ -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ENABLE (0x1 << 0) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_MODE (0x3 << 1) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_PIC_FORMAT (0xf << 4) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_FORMAT (0x3 << 8) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YUV10B_COMPACT (0x1 << 10) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ENDIAN_MODE (0x1 << 11) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ENABLE (0x1 << 0) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_MODE (0x3 << 1) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_PIC_FORMAT (0xf << 4) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_FORMAT (0x3 << 8) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YUV10B_COMPACT (0x1 << 10) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ENDIAN_MODE (0x1 << 11) #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_PIX_SWAP (0x1 << 12) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YC_SWAP (0x1 << 13) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ROT (0x1 << 16) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_XMIRROR (0x1 << 17) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YMIRROR (0x1 << 18) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_BY (0x1 << 20) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_UP (0x1 << 21) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_BY (0x1 << 22) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_UP (0x1 << 23) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_Y2R_EN (0x1 << 24) -#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_R2Y_EN (0x1 << 25) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YC_SWAP (0x1 << 13) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ROT (0x1 << 16) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_XMIRROR (0x1 << 17) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YMIRROR (0x1 << 18) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_BY (0x1 << 20) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_UP (0x1 << 21) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_BY (0x1 << 22) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_UP (0x1 << 23) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_Y2R_EN (0x1 << 24) +#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_R2Y_EN (0x1 << 25) #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_CSC_MODE (0x3 << 26) #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_PERF_OPT_DIS (0x1 << 29) #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_ALIGN_DIS (0x1 << 30) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ENABLE(x) ((x & 0x1) << 0) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_MODE(x) ((x & 0x3) << 1) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PIC_FORMAT(x) ((x & 0xf) << 4) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ENABLE(x) ((x & 0x1) << 0) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_MODE(x) ((x & 0x3) << 1) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PIC_FORMAT(x) ((x & 0xf) << 4) #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_FORMAT(x) ((x & 0x3) << 8) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YUV10B_COMPACT(x) ((x & 0x1) << 10) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ENDIAN_MODE(x) ((x & 0x1) << 11) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PIX_SWAP(x) ((x & 0x1) << 12) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YC_SWAP(x) ((x & 0x1) << 13) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ROT(x) ((x & 0x1) << 16) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_XMIRROR(x) ((x & 0x1) << 17) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YMIRROR(x) ((x & 0x1) << 18) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_BY(x) ((x & 0x1) << 20) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_UP(x) ((x & 0x1) << 21) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_BY(x) ((x & 0x1) << 22) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_UP(x) ((x & 0x1) << 23) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_Y2R_EN(x) ((x & 0x1) << 24) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_R2Y_EN(x) ((x & 0x1) << 25) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_CSC_MODE(x) ((x & 0x3) << 26) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PERF_OPT_DIS(x) ((x & 0x1) << 29) -#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_ALIGN_DIS(x) ((x & 0x1) << 30) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YUV10B_COMPACT(x) ((x & 0x1) << 10) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ENDIAN_MODE(x) ((x & 0x1) << 11) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PIX_SWAP(x) ((x & 0x1) << 12) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YC_SWAP(x) ((x & 0x1) << 13) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ROT(x) ((x & 0x1) << 16) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_XMIRROR(x) ((x & 0x1) << 17) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YMIRROR(x) ((x & 0x1) << 18) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_BY(x) ((x & 0x1) << 20) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_UP(x) ((x & 0x1) << 21) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_BY(x) ((x & 0x1) << 22) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_UP(x) ((x & 0x1) << 23) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_Y2R_EN(x) ((x & 0x1) << 24) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_R2Y_EN(x) ((x & 0x1) << 25) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_CSC_MODE(x) ((x & 0x3) << 26) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PERF_OPT_DIS(x) ((x & 0x1) << 29) +#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_ALIGN_DIS(x) ((x & 0x1) << 30) /* RGA3_WIN1_FBC_OFF */ #define m_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_XOFF (0x1fff << 0) #define m_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_YOFF (0x1fff << 16) -#define s_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_XOFF(x) ((x & 0x1fff) << 0) -#define s_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_YOFF(x) ((x & 0x1fff) << 16) +#define s_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_XOFF(x) ((x & 0x1fff) << 0) +#define s_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_YOFF(x) ((x & 0x1fff) << 16) /* RGA3_WIN1_SRC_SIZE */ -#define m_RGA3_WIN1_SRC_SIZE_SW_WIN1_SRC_WIDTH (0x1fff << 0) -#define m_RGA3_WIN1_SRC_SIZE_SW_WIN1_SRC_HEIGHT (0x1fff << 16) +#define m_RGA3_WIN1_SRC_SIZE_SW_WIN1_SRC_WIDTH (0x1fff << 0) +#define m_RGA3_WIN1_SRC_SIZE_SW_WIN1_SRC_HEIGHT (0x1fff << 16) -#define s_RGA3_WIN1_SRC_OFF_SW_WIN1_SRC_WIDTH(x) ((x & 0x1fff) << 0) -#define s_RGA3_WIN1_SRC_OFF_SW_WIN1_SRC_HEIGHT(x) ((x & 0x1fff) << 16) +#define s_RGA3_WIN1_SRC_OFF_SW_WIN1_SRC_WIDTH(x) ((x & 0x1fff) << 0) +#define s_RGA3_WIN1_SRC_OFF_SW_WIN1_SRC_HEIGHT(x) ((x & 0x1fff) << 16) /* RGA3_WIN1_ACT_OFF */ #define m_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_XOFF (0x1fff << 0) #define m_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_YOFF (0x1fff << 16) -#define s_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_XOFF(x) ((x & 0x1fff) << 0) -#define s_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_YOFF(x) ((x & 0x1fff) << 16) +#define s_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_XOFF(x) ((x & 0x1fff) << 0) +#define s_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_YOFF(x) ((x & 0x1fff) << 16) /* RGA3_WIN1_ACT_SIZE */ -#define m_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_WIDTH (0x1fff << 0) -#define m_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_HEIGHT (0x1fff << 16) +#define m_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_WIDTH (0x1fff << 0) +#define m_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_HEIGHT (0x1fff << 16) -#define s_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_WIDTH(x) ((x & 0x1fff) << 0) -#define s_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_HEIGHT(x) ((x & 0x1fff) << 16) +#define s_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_WIDTH(x) ((x & 0x1fff) << 0) +#define s_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_HEIGHT(x) ((x & 0x1fff) << 16) /* RGA3_WIN1_DST_SIZE */ -#define m_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_WIDTH (0x1fff << 0) -#define m_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_HEIGHT (0x1fff << 16) +#define m_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_WIDTH (0x1fff << 0) +#define m_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_HEIGHT (0x1fff << 16) -#define s_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_WIDTH(x) ((x & 0x1fff) << 0) -#define s_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_HEIGHT(x) ((x & 0x1fff) << 16) +#define s_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_WIDTH(x) ((x & 0x1fff) << 0) +#define s_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_HEIGHT(x) ((x & 0x1fff) << 16) /* RGA3_WIN1_SCL_FAC */ -#define m_RGA3_WIN1_SCL_FAC_SW_WIN1_VER_FAC (0xffff << 0) -#define m_RGA3_WIN1_SCL_FAC_SW_WIN1_HOR_FAC (0xffff << 16) +#define m_RGA3_WIN1_SCL_FAC_SW_WIN1_VER_FAC (0xffff << 0) +#define m_RGA3_WIN1_SCL_FAC_SW_WIN1_HOR_FAC (0xffff << 16) -#define s_RGA3_WIN1_SCL_FAC_SW_WIN1_VER_FAC(x) ((x & 0xffff) << 0) -#define s_RGA3_WIN1_SCL_FAC_SW_WIN1_HOR_FAC(x) ((x & 0xffff) << 16) +#define s_RGA3_WIN1_SCL_FAC_SW_WIN1_VER_FAC(x) ((x & 0xffff) << 0) +#define s_RGA3_WIN1_SCL_FAC_SW_WIN1_HOR_FAC(x) ((x & 0xffff) << 16) /* RGA3_OVLP_CTRL */ -#define m_RGA3_OVLP_CTRL_SW_OVLP_MODE (0x3 << 0) -#define m_RGA3_OVLP_CTRL_SW_OVLP_FIELD (0x1 << 2) -#define m_RGA3_OVLP_CTRL_SW_TOP_SWAP (0x1 << 3) -#define m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN (0x1 << 4) -#define m_RGA3_OVLP_CTRL_SW_TOP_KEY_EN (0x7FFF << 5) -#define m_RGA3_OVLP_CTRL_SW_OVLP_Y2R_EN (0x1 << 20) -#define m_RGA3_OVLP_CTRL_SW_OVLP_R2Y_EN (0x1 << 21) -#define m_RGA3_OVLP_CTRL_SW_OVLP_CSC_MODE (0x3 << 22) +#define m_RGA3_OVLP_CTRL_SW_OVLP_MODE (0x3 << 0) +#define m_RGA3_OVLP_CTRL_SW_OVLP_FIELD (0x1 << 2) +#define m_RGA3_OVLP_CTRL_SW_TOP_SWAP (0x1 << 3) +#define m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN (0x1 << 4) +#define m_RGA3_OVLP_CTRL_SW_TOP_KEY_EN (0x7FFF << 5) +#define m_RGA3_OVLP_CTRL_SW_OVLP_Y2R_EN (0x1 << 20) +#define m_RGA3_OVLP_CTRL_SW_OVLP_R2Y_EN (0x1 << 21) +#define m_RGA3_OVLP_CTRL_SW_OVLP_CSC_MODE (0x3 << 22) -#define s_RGA3_OVLP_CTRL_SW_OVLP_MODE(x) ((x & 0x3) << 0) -#define s_RGA3_OVLP_CTRL_SW_OVLP_FIELD(x) ((x & 0x1) << 2) -#define s_RGA3_OVLP_CTRL_SW_TOP_SWAP(x) ((x & 0x1) << 3) -#define s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(x) ((x & 0x1) << 4) -#define s_RGA3_OVLP_CTRL_SW_TOP_KEY_EN(x) ((x & 0x7FFF) << 5) -#define s_RGA3_OVLP_CTRL_SW_OVLP_Y2R_EN(x) ((x & 0x1) << 20) -#define s_RGA3_OVLP_CTRL_SW_OVLP_R2Y_EN(x) ((x & 0x1) << 21) -#define s_RGA3_OVLP_CTRL_SW_OVLP_CSC_MODE(x) ((x & 0x3) << 22) +#define s_RGA3_OVLP_CTRL_SW_OVLP_MODE(x) ((x & 0x3) << 0) +#define s_RGA3_OVLP_CTRL_SW_OVLP_FIELD(x) ((x & 0x1) << 2) +#define s_RGA3_OVLP_CTRL_SW_TOP_SWAP(x) ((x & 0x1) << 3) +#define s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(x) ((x & 0x1) << 4) +#define s_RGA3_OVLP_CTRL_SW_TOP_KEY_EN(x) ((x & 0x7FFF) << 5) +#define s_RGA3_OVLP_CTRL_SW_OVLP_Y2R_EN(x) ((x & 0x1) << 20) +#define s_RGA3_OVLP_CTRL_SW_OVLP_R2Y_EN(x) ((x & 0x1) << 21) +#define s_RGA3_OVLP_CTRL_SW_OVLP_CSC_MODE(x) ((x & 0x3) << 22) /* RGA3_OVLP_OFF */ -#define m_RGA3_OVLP_OFF_SW_OVLP_XOFF (0x1fff << 0) -#define m_RGA3_OVLP_OFF_SW_OVLP_YOFF (0x1fff << 16) +#define m_RGA3_OVLP_OFF_SW_OVLP_XOFF (0x1fff << 0) +#define m_RGA3_OVLP_OFF_SW_OVLP_YOFF (0x1fff << 16) -#define s_RGA3_OVLP_OFF_SW_OVLP_XOFF(x) ((x & 0x1fff) << 0) -#define s_RGA3_OVLP_OFF_SW_OVLP_YOFF(x) ((x & 0x1fff) << 16) +#define s_RGA3_OVLP_OFF_SW_OVLP_XOFF(x) ((x & 0x1fff) << 0) +#define s_RGA3_OVLP_OFF_SW_OVLP_YOFF(x) ((x & 0x1fff) << 16) /* RGA3_OVLP_TOP_KEY_MIN */ -#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_YG_MIN (0x3ff << 0) -#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_UB_MIN (0x3ff << 10) -#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_VR_MIN (0x3ff << 20) +#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_YG_MIN (0x3ff << 0) +#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_UB_MIN (0x3ff << 10) +#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_VR_MIN (0x3ff << 20) -#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_YG_MIN(x) ((x & 0x3f)f << 0) -#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_UB_MIN(x) ((x & 0x3ff) << 10) -#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_VR_MIN(x) ((x & 0x3ff) << 20) +#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_YG_MIN(x) ((x & 0x3f)f << 0) +#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_UB_MIN(x) ((x & 0x3ff) << 10) +#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_VR_MIN(x) ((x & 0x3ff) << 20) /* RGA3_OVLP_TOP_KEY_MAX */ -#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_YG_MAX (0x3ff << 0) -#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_UB_MAX (0x3ff << 10) -#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_VR_MAX (0x3ff << 20) +#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_YG_MAX (0x3ff << 0) +#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_UB_MAX (0x3ff << 10) +#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_VR_MAX (0x3ff << 20) -#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_YG_MAX(x) ((x & 0x3ff) << 0) -#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_UB_MAX(x) ((x & 0x3ff) << 10) -#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_VR_MAX(x) ((x & 0x3ff) << 20) +#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_YG_MAX(x) ((x & 0x3ff) << 0) +#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_UB_MAX(x) ((x & 0x3ff) << 10) +#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_VR_MAX(x) ((x & 0x3ff) << 20) /* RGA3_OVLP_TOP_CTRL */ #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0 (0x1 << 0) #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0 (0x1 << 1) #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0 (0x3 << 2) #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0 (0x1 << 4) -#define m_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0 (0x7 << 5) +#define m_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0 (0x7 << 5) #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA (0xff << 16) -#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0(x) ((x & 0x1) << 0) -#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0(x) ((x & 0x1) << 1) -#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0(x) ((x & 0x3) << 2) -#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0(x) ((x & 0x1) << 4) +#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0(x) ((x & 0x1) << 0) +#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0(x) ((x & 0x1) << 1) +#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0(x) ((x & 0x3) << 2) +#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0(x) ((x & 0x1) << 4) #define s_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0(x) ((x & 0x7) << 5) -#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA(x) ((x & 0xff) << 16) +#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA(x) ((x & 0xff) << 16) /* RGA3_OVLP_BOT_CTRL */ #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0 (0x1 << 0) #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0 (0x1 << 1) #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0 (0x3 << 2) #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0 (0x1 << 4) -#define m_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0 (0x7 << 5) +#define m_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0 (0x7 << 5) #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA (0xff << 16) -#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0(x) ((x & 0x1) << 0) -#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0(x) ((x & 0x1) << 1) -#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0(x) ((x & 0x3) << 2) -#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0(x) ((x & 0x1) << 4) +#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0(x) ((x & 0x1) << 0) +#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0(x) ((x & 0x1) << 1) +#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0(x) ((x & 0x3) << 2) +#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0(x) ((x & 0x1) << 4) #define s_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0(x) ((x & 0x7) << 5) -#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA(x) ((x & 0xff) << 16) +#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA(x) ((x & 0xff) << 16) /* RGA3_OVLP_TOP_ALPHA */ -#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1 (0x1 << 1) -#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1 (0x3 << 2) -#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1 (0x1 << 4) -#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1 (0x7 << 5) +#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1 (0x1 << 1) +#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1 (0x3 << 2) +#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1 (0x1 << 4) +#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1 (0x7 << 5) #define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1(x) ((x & 0x1) << 1) #define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1(x) ((x & 0x3) << 2) -#define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1(x) ((x & 0x1) << 4) -#define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1(x) ((x & 0x7) << 5) +#define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1(x) ((x & 0x1) << 4) +#define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1(x) ((x & 0x7) << 5) /* RGA3_OVLP_BOT_ALPHA */ -#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1 (0x1 << 1) -#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1 (0x3 << 2) -#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1 (0x1 << 4) -#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1 (0x7 << 5) +#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1 (0x1 << 1) +#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1 (0x3 << 2) +#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1 (0x1 << 4) +#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1 (0x7 << 5) #define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1(x) ((x & 0x1) << 1) #define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1(x) ((x & 0x3) << 2) -#define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1(x) ((x & 0x1) << 4) -#define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1(x) ((x & 0x7) << 5) +#define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1(x) ((x & 0x1) << 4) +#define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1(x) ((x & 0x7) << 5) /* RGA3_WR_CTRL */ -#define m_RGA3_WR_CTRL_SW_WR_MODE (0x3 << 0) -#define m_RGA3_WR_CTRL_SW_WR_FBCE_SPARSE_EN (0x1 << 2) -#define m_RGA3_WR_CTRL_SW_WR_PIC_FORMAT (0xf << 4) +#define m_RGA3_WR_CTRL_SW_WR_MODE (0x3 << 0) +#define m_RGA3_WR_CTRL_SW_WR_FBCE_SPARSE_EN (0x1 << 2) +#define m_RGA3_WR_CTRL_SW_WR_PIC_FORMAT (0xf << 4) #define m_RGA3_WR_CTRL_SW_WR_FORMAT (0x3 << 8) -#define m_RGA3_WR_CTRL_SW_WR_YUV10B_COMPACT (0x1 << 10) -#define m_RGA3_WR_CTRL_SW_WR_ENDIAN_MODE (0x1 << 11) -#define m_RGA3_WR_CTRL_SW_WR_PIX_SWAP (0x1 << 12) -#define m_RGA3_WR_CTRL_SW_OUTSTANDING_MAX (0x3f << 13) -#define m_RGA3_WR_CTRL_SW_WR_YC_SWAP (0x1 << 20) +#define m_RGA3_WR_CTRL_SW_WR_YUV10B_COMPACT (0x1 << 10) +#define m_RGA3_WR_CTRL_SW_WR_ENDIAN_MODE (0x1 << 11) +#define m_RGA3_WR_CTRL_SW_WR_PIX_SWAP (0x1 << 12) +#define m_RGA3_WR_CTRL_SW_OUTSTANDING_MAX (0x3f << 13) +#define m_RGA3_WR_CTRL_SW_WR_YC_SWAP (0x1 << 20) -#define s_RGA3_WR_CTRL_SW_WR_MODE(x) ((x & 0x3) << 0) -#define s_RGA3_WR_CTRL_SW_WR_FBCE_SPARSE_EN(x) ((x & 0x1) << 2) -#define s_RGA3_WR_CTRL_SW_WR_PIC_FORMAT(x) ((x & 0xf) << 4) -#define s_RGA3_WR_CTRL_SW_WR_FORMAT(x) ((x & 0x3) << 8) -#define s_RGA3_WR_CTRL_SW_WR_YUV10B_COMPACT(x) ((x & 0x1) << 10) -#define s_RGA3_WR_CTRL_SW_WR_ENDIAN_MODE(x) ((x & 0x1) << 11) -#define s_RGA3_WR_CTRL_SW_WR_PIX_SWAP(x) ((x & 0x1) << 12) -#define s_RGA3_WR_CTRL_SW_OUTSTANDING_MAX(x) ((x & 0x3f) << 13) -#define s_RGA3_WR_CTRL_SW_WR_YC_SWAP(x) ((x & 0x1) << 20) +#define s_RGA3_WR_CTRL_SW_WR_MODE(x) ((x & 0x3) << 0) +#define s_RGA3_WR_CTRL_SW_WR_FBCE_SPARSE_EN(x) ((x & 0x1) << 2) +#define s_RGA3_WR_CTRL_SW_WR_PIC_FORMAT(x) ((x & 0xf) << 4) +#define s_RGA3_WR_CTRL_SW_WR_FORMAT(x) ((x & 0x3) << 8) +#define s_RGA3_WR_CTRL_SW_WR_YUV10B_COMPACT(x) ((x & 0x1) << 10) +#define s_RGA3_WR_CTRL_SW_WR_ENDIAN_MODE(x) ((x & 0x1) << 11) +#define s_RGA3_WR_CTRL_SW_WR_PIX_SWAP(x) ((x & 0x1) << 12) +#define s_RGA3_WR_CTRL_SW_OUTSTANDING_MAX(x) ((x & 0x3f) << 13) +#define s_RGA3_WR_CTRL_SW_WR_YC_SWAP(x) ((x & 0x1) << 20) /* RGA3_WR_FBCE_CTRL */ -#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_BLKBD_OPT_DIS (0x1 << 0) +#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_BLKBD_OPT_DIS (0x1 << 0) #define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_HOFF_DISS (0x1 << 1) -#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO0_WATERMARK (0x3f << 2) -#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO1_WATERMARK (0x3f << 8) -#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_SIZE_ALIGN_DIS (0x1 << 31) +#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO0_WATERMARK (0x3f << 2) +#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO1_WATERMARK (0x3f << 8) +#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_SIZE_ALIGN_DIS (0x1 << 31) -#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_BLKBD_OPT_DIS(x) ((x & 0x1) << 0) +#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_BLKBD_OPT_DIS(x) ((x & 0x1) << 0) #define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_HOFF_DISS(x) ((x & 0x1) << 1) -#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO0_WATERMARK(x) ((x & 0x3f) << 2) -#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO1_WATERMARK(x) ((x & 0x3f) << 8) -#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_SIZE_ALIGN_DIS(x) ((x & 0x1) << 31) +#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO0_WATERMARK(x) ((x & 0x3f) << 2) +#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO1_WATERMARK(x) ((x & 0x3f) << 8) +#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_SIZE_ALIGN_DIS(x) ((x & 0x1) << 31) /* RGA3_MMU_STATUS read_only */ -#define m_RGA3_MMU_STATUS_PAGING_ENABLED (0x1 << 0) -#define m_RGA3_MMU_STATUS_PAGE_FAULT_ACTIVE (0x1 << 1) -#define m_RGA3_MMU_STATUS_STAIL_ACTIVE (0x1 << 2) -#define m_RGA3_MMU_STATUS_MMU_IDLE (0x1 << 3) -#define m_RGA3_MMU_STATUS_REPLAY_BUFFER_EMPTY (0x1 << 4) -#define m_RGA3_MMU_STATUS_PAGE_FAULT_IS_WRITE (0x1 << 5) -#define m_RGA3_MMU_STATUS_PAGE_FAULT_BUS_ID (0x1f << 6) +#define m_RGA3_MMU_STATUS_PAGING_ENABLED (0x1 << 0) +#define m_RGA3_MMU_STATUS_PAGE_FAULT_ACTIVE (0x1 << 1) +#define m_RGA3_MMU_STATUS_STAIL_ACTIVE (0x1 << 2) +#define m_RGA3_MMU_STATUS_MMU_IDLE (0x1 << 3) +#define m_RGA3_MMU_STATUS_REPLAY_BUFFER_EMPTY (0x1 << 4) +#define m_RGA3_MMU_STATUS_PAGE_FAULT_IS_WRITE (0x1 << 5) +#define m_RGA3_MMU_STATUS_PAGE_FAULT_BUS_ID (0x1f << 6) /* RGA3_MMU_INT_RAWSTAT read_only */ -#define m_RGA3_MMU_INT_RAWSTAT_READ_BUS_ERROR (0x1 << 0) -#define m_RGA3_MMU_INT_RAWSTAT_PAGE_FAULT (0x1 << 1) +#define m_RGA3_MMU_INT_RAWSTAT_READ_BUS_ERROR (0x1 << 0) +#define m_RGA3_MMU_INT_RAWSTAT_PAGE_FAULT (0x1 << 1) /* RGA3_MMU_INT_CLEAR write_only */ -#define m_RGA3_MMU_INT_CLEAR_READ_BUS_ERROR (0x1 << 0) -#define m_RGA3_MMU_INT_CLEAR_PAGE_FAULT (0x1 << 1) +#define m_RGA3_MMU_INT_CLEAR_READ_BUS_ERROR (0x1 << 0) +#define m_RGA3_MMU_INT_CLEAR_PAGE_FAULT (0x1 << 1) -#define s_RGA3_MMU_INT_CLEAR_READ_BUS_ERROR(x) ((x & 0x1) << 0) -#define s_RGA3_MMU_INT_CLEAR_PAGE_FAULT(x) ((x & 0x1) << 1) +#define s_RGA3_MMU_INT_CLEAR_READ_BUS_ERROR(x) ((x & 0x1) << 0) +#define s_RGA3_MMU_INT_CLEAR_PAGE_FAULT(x) ((x & 0x1) << 1) /* RGA3_MMU_INT_MASK */ -#define m_RGA3_MMU_INT_MASK_READ_BUS_ERROR (0x1 << 0) -#define m_RGA3_MMU_INT_MASK_PAGE_FAULT (0x1 << 1) +#define m_RGA3_MMU_INT_MASK_READ_BUS_ERROR (0x1 << 0) +#define m_RGA3_MMU_INT_MASK_PAGE_FAULT (0x1 << 1) -#define s_RGA3_MMU_INT_MASK_READ_BUS_ERROR(x) ((x & 0x1) << 0) -#define s_RGA3_MMU_INT_MASK_PAGE_FAULT(x) ((x & 0x1) << 1) +#define s_RGA3_MMU_INT_MASK_READ_BUS_ERROR(x) ((x & 0x1) << 0) +#define s_RGA3_MMU_INT_MASK_PAGE_FAULT(x) ((x & 0x1) << 1) /* RGA3_MMU_INT_STATUS read_only */ -#define m_RGA3_MMU_INT_STATUS_READ_BUS_ERROR (0x1 << 0) +#define m_RGA3_MMU_INT_STATUS_READ_BUS_ERROR (0x1 << 0) #define m_RGA3_MMU_INT_STATUS_PAGE_FAULT (0x1 << 1) /* RGA3_MMU_AUTO_GATING */ -#define m_RGA3_MMU_AUTO_GATING_MMU_AUTO_GATING (0x1 << 1) -#define m_RGA3_MMU_AUTO_GATING_MMU_CFG_MODE (0x1 << 1) -#define m_RGA3_MMU_AUTO_GATING_MMU_BUG_FIXED_DISABLE (0x1 << 31) +#define m_RGA3_MMU_AUTO_GATING_MMU_AUTO_GATING (0x1 << 1) +#define m_RGA3_MMU_AUTO_GATING_MMU_CFG_MODE (0x1 << 1) +#define m_RGA3_MMU_AUTO_GATING_MMU_BUG_FIXED_DISABLE (0x1 << 31) -#define s_RGA3_MMU_AUTO_GATING_MMU_AUTO_GATING(x) ((x & 0x1) << 1) -#define s_RGA3_MMU_AUTO_GATING_MMU_BUG_FIXED_DISABLE(x) ((x & 0x1) << 31) +#define s_RGA3_MMU_AUTO_GATING_MMU_AUTO_GATING(x) ((x & 0x1) << 1) +#define s_RGA3_MMU_AUTO_GATING_MMU_BUG_FIXED_DISABLE(x) ((x & 0x1) << 31) -/* sys_reg */ -#define RGA3_SYS_CTRL_OFFSET 0x000 -#define RGA3_CMD_CTRL_OFFSET 0x004 -#define RGA3_CMD_ADDR_OFFSET 0x008 -#define RGA3_MI_GROUP_CTRL_OFFSET 0x00c -#define RGA3_ARQOS_CTRL_OFFSET 0x010 -#define RGA3_VERSION_NUM_OFFSET 0x018 -#define RGA3_VERSION_TIM_OFFSET 0x01c -#define RGA3_INT_EN_OFFSET 0x020 -#define RGA3_INT_RAW_OFFSET 0x024 -#define RGA3_INT_MSK_OFFSET 0x028 -#define RGA3_INT_CLR_OFFSET 0x02c -#define RGA3_RO_SRST_OFFSET 0x030 -#define RGA3_STATUS0_OFFSET 0x034 -#define RGA3_SCAN_CNT_OFFSET 0x038 -#define RGA3_STATUS1_OFFSET 0x03c -#define RGA3_CMD_STATE_OFFSET 0x040 - -/* op_reg */ -#define RGA3_WIN0_RD_CTRL_OFFSET 0x000 -#define RGA3_WIN0_Y_BASE_OFFSET 0x010 -#define RGA3_WIN0_U_BASE_OFFSET 0x014 -#define RGA3_WIN0_V_BASE_OFFSET 0x018 -#define RGA3_WIN0_VIR_STRIDE_OFFSET 0x01c -#define RGA3_WIN0_FBC_OFF_OFFSET 0x020 -#define RGA3_WIN0_SRC_SIZE_OFFSET 0x024 -#define RGA3_WIN0_ACT_OFF_OFFSET 0x028 -#define RGA3_WIN0_ACT_SIZE_OFFSET 0x02c -#define RGA3_WIN0_DST_SIZE_OFFSET 0x030 -#define RGA3_WIN0_SCL_FAC_OFFSET 0x034 -#define RGA3_WIN0_UV_VIR_STRIDE_OFFSET 0x038 -#define RGA3_WIN1_RD_CTRL_OFFSET 0x040 -#define RGA3_WIN1_Y_BASE_OFFSET 0x050 -#define RGA3_WIN1_U_BASE_OFFSET 0x054 -#define RGA3_WIN1_V_BASE_OFFSET 0x058 -#define RGA3_WIN1_VIR_STRIDE_OFFSET 0x05c -#define RGA3_WIN1_FBC_OFF_OFFSET 0x060 -#define RGA3_WIN1_SRC_SIZE_OFFSET 0x064 -#define RGA3_WIN1_ACT_OFF_OFFSET 0x068 -#define RGA3_WIN1_ACT_SIZE_OFFSET 0x06c -#define RGA3_WIN1_DST_SIZE_OFFSET 0x070 -#define RGA3_WIN1_SCL_FAC_OFFSET 0x074 -#define RGA3_WIN1_UV_VIR_STRIDE_OFFSET 0x078 -#define RGA3_OVLP_CTRL_OFFSET 0x080 -#define RGA3_OVLP_OFF_OFFSET 0x084 -#define RGA3_OVLP_TOP_KEY_MIN_OFFSET 0x088 -#define RGA3_OVLP_TOP_KEY_MAX_OFFSET 0x08c -#define RGA3_OVLP_TOP_CTRL_OFFSET 0x090 -#define RGA3_OVLP_BOT_CTRL_OFFSET 0x094 -#define RGA3_OVLP_TOP_ALPHA_OFFSET 0x098 -#define RGA3_OVLP_BOT_ALPHA_OFFSET 0x09c -#define RGA3_WR_CTRL_OFFSET 0x0a0 -#define RGA3_WR_FBCE_CTRL_OFFSET 0x0a4 -#define RGA3_WR_VIR_STRIDE_OFFSET 0x0a8 -#define RGA3_WR_PL_VIR_STRIDE_OFFSET 0x0ac -#define RGA3_WR_Y_BASE_OFFSET 0x0b0 -#define RGA3_WR_U_BASE_OFFSET 0x0b4 -#define RGA3_WR_V_BASE_OFFSET 0x0b8 -#define RGA3_MMU_DTE_ADDR_OFFSET 0x0f00 -#define RGA3_MMU_STATUS_OFFSET 0x0f04 -#define RGA3_MMU_COMMAND_OFFSET 0x0f08 -#define RGA3_MMU_PAGE_FAULT_ADDR_OFFSET 0x0f0c -#define RGA3_MMU_ZAP_ONE_LINE_OFFSET 0x0f10 -#define RGA3_MMU_INT_RAWSTAT_OFFSET 0x0f14 -#define RGA3_MMU_INT_CLEAR_OFFSET 0x0f18 -#define RGA3_MMU_INT_MASK_OFFSET 0x0f1c -#define RGA3_MMU_INT_STATUS_OFFSET 0x0f20 -#define RGA3_MMU_AUTO_GATING_OFFSET 0x0f24 -#define RGA3_MMU_REG_LOAD_EN_OFFSET 0x0f28 - -#define RGA3_ROT_BIT_ROT_90 BIT(0) -#define RGA3_ROT_BIT_X_MIRROR BIT(1) -#define RGA3_ROT_BIT_Y_MIRROR BIT(2) +#define RGA3_ROT_BIT_ROT_90 BIT(0) +#define RGA3_ROT_BIT_X_MIRROR BIT(1) +#define RGA3_ROT_BIT_Y_MIRROR BIT(2) int rga3_gen_reg_info(unsigned char *base, struct rga3_req *msg); void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req); diff --git a/drivers/video/rockchip/rga3/rga2_reg_info.c b/drivers/video/rockchip/rga3/rga2_reg_info.c index 923c1f30625d..363549b6baa6 100644 --- a/drivers/video/rockchip/rga3/rga2_reg_info.c +++ b/drivers/video/rockchip/rga3/rga2_reg_info.c @@ -2351,28 +2351,28 @@ static void rga2_set_pre_intr_reg(struct rga_job *job, struct rga_scheduler_t *s if (job->pre_intr_info.read_intr_en) { reg = s_RGA2_READ_LINE_SW_INTR_LINE_RD_TH(job->pre_intr_info.read_threshold); - rga_write(reg, RGA2_READ_LINE_CNT_OFFSET, scheduler); + rga_write(reg, RGA2_READ_LINE_CNT, scheduler); } if (job->pre_intr_info.write_intr_en) { reg = s_RGA2_WRITE_LINE_SW_INTR_LINE_WR_START(job->pre_intr_info.write_start); reg = ((reg & (~m_RGA2_WRITE_LINE_SW_INTR_LINE_WR_STEP)) | (s_RGA2_WRITE_LINE_SW_INTR_LINE_WR_STEP(job->pre_intr_info.write_step))); - rga_write(reg, RGA2_WRITE_LINE_CNT_OFFSET, scheduler); + rga_write(reg, RGA2_WRITE_LINE_CNT, scheduler); } - reg = rga_read(RGA2_SYS_CTRL_OFFSET, scheduler); + reg = rga_read(RGA2_SYS_CTRL, scheduler); reg = ((reg & (~m_RGA2_SYS_HOLD_MODE_EN)) | (s_RGA2_SYS_HOLD_MODE_EN(job->pre_intr_info.read_hold_en))); - rga_write(reg, RGA2_SYS_CTRL_OFFSET, scheduler); + rga_write(reg, RGA2_SYS_CTRL, scheduler); - reg = rga_read(RGA2_INT_OFFSET, scheduler); + reg = rga_read(RGA2_INT, scheduler); reg = (reg | s_RGA2_INT_LINE_RD_CLEAR(0x1) | s_RGA2_INT_LINE_WR_CLEAR(0x1)); reg = ((reg & (~m_RGA2_INT_LINE_RD_EN)) | (s_RGA2_INT_LINE_RD_EN(job->pre_intr_info.read_intr_en))); reg = ((reg & (~m_RGA2_INT_LINE_WR_EN)) | (s_RGA2_INT_LINE_WR_EN(job->pre_intr_info.write_intr_en))); - rga_write(reg, RGA2_INT_OFFSET, scheduler); + rga_write(reg, RGA2_INT, scheduler); } static void rga2_set_reg_full_csc(struct rga_job *job, struct rga_scheduler_t *scheduler) @@ -2388,23 +2388,23 @@ static void rga2_set_reg_full_csc(struct rga_job *job, struct rga_scheduler_t *s /* full csc coefficient */ /* Y coefficient */ rga_write(job->full_csc.coe_y.r_v | (clip_y_max << 16) | (clip_y_min << 24), - RGA2_DST_CSC_00_OFFSET, scheduler); + RGA2_DST_CSC_00, scheduler); rga_write(job->full_csc.coe_y.g_y | (clip_uv_max << 16) | (clip_uv_min << 24), - RGA2_DST_CSC_01_OFFSET, scheduler); - rga_write(job->full_csc.coe_y.b_u, RGA2_DST_CSC_02_OFFSET, scheduler); - rga_write(job->full_csc.coe_y.off, RGA2_DST_CSC_OFF0_OFFSET, scheduler); + RGA2_DST_CSC_01, scheduler); + rga_write(job->full_csc.coe_y.b_u, RGA2_DST_CSC_02, scheduler); + rga_write(job->full_csc.coe_y.off, RGA2_DST_CSC_OFF0, scheduler); /* U coefficient */ - rga_write(job->full_csc.coe_u.r_v, RGA2_DST_CSC_10_OFFSET, scheduler); - rga_write(job->full_csc.coe_u.g_y, RGA2_DST_CSC_11_OFFSET, scheduler); - rga_write(job->full_csc.coe_u.b_u, RGA2_DST_CSC_12_OFFSET, scheduler); - rga_write(job->full_csc.coe_u.off, RGA2_DST_CSC_OFF1_OFFSET, scheduler); + rga_write(job->full_csc.coe_u.r_v, RGA2_DST_CSC_10, scheduler); + rga_write(job->full_csc.coe_u.g_y, RGA2_DST_CSC_11, scheduler); + rga_write(job->full_csc.coe_u.b_u, RGA2_DST_CSC_12, scheduler); + rga_write(job->full_csc.coe_u.off, RGA2_DST_CSC_OFF1, scheduler); /* V coefficient */ - rga_write(job->full_csc.coe_v.r_v, RGA2_DST_CSC_20_OFFSET, scheduler); - rga_write(job->full_csc.coe_v.g_y, RGA2_DST_CSC_21_OFFSET, scheduler); - rga_write(job->full_csc.coe_v.b_u, RGA2_DST_CSC_22_OFFSET, scheduler); - rga_write(job->full_csc.coe_v.off, RGA2_DST_CSC_OFF2_OFFSET, scheduler); + rga_write(job->full_csc.coe_v.r_v, RGA2_DST_CSC_20, scheduler); + rga_write(job->full_csc.coe_v.g_y, RGA2_DST_CSC_21, scheduler); + rga_write(job->full_csc.coe_v.b_u, RGA2_DST_CSC_22, scheduler); + rga_write(job->full_csc.coe_v.off, RGA2_DST_CSC_OFF2, scheduler); } int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler) diff --git a/drivers/video/rockchip/rga3/rga3_reg_info.c b/drivers/video/rockchip/rga3/rga3_reg_info.c index e065b820ca92..63904a0ef933 100644 --- a/drivers/video/rockchip/rga3/rga3_reg_info.c +++ b/drivers/video/rockchip/rga3/rga3_reg_info.c @@ -1621,10 +1621,10 @@ void rga3_soft_reset(struct rga_scheduler_t *scheduler) rga_write(0, 0xf08, scheduler); if (DEBUGGER_EN(INT_FLAG)) - pr_info("irq INT[%x], STATS0[%x], STATS1[%x]\n", + pr_info("soft reset, INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n", rga_read(RGA3_INT_RAW, scheduler), rga_read(RGA3_STATUS0, scheduler), - rga_read(RGA3_STATUS1, scheduler)); + rga_read(RGA3_CMD_STATE, scheduler)); for (i = 0; i < RGA_RESET_TIMEOUT; i++) { reg = rga_read(RGA3_SYS_CTRL, scheduler) & 1; @@ -1938,14 +1938,14 @@ int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler) rga_write(1, RGA3_INT_EN, scheduler); if (DEBUGGER_EN(MSG)) { - pr_info("sys_ctrl = %x, int_en = %x, int_raw = %x\n", + pr_info("sys_ctrl = 0x%x, int_en = 0x%x, int_raw = 0x%x\n", rga_read(RGA3_SYS_CTRL, scheduler), rga_read(RGA3_INT_EN, scheduler), rga_read(RGA3_INT_RAW, scheduler)); - pr_info("status0 = %x, status1 = %x\n", + pr_info("hw_status = 0x%x, cmd_status = 0x%x\n", rga_read(RGA3_STATUS0, scheduler), - rga_read(RGA3_STATUS1, scheduler)); + rga_read(RGA3_CMD_STATE, scheduler)); } if (DEBUGGER_EN(TIME)) diff --git a/drivers/video/rockchip/rga3/rga_drv.c b/drivers/video/rockchip/rga3/rga_drv.c index 0ab49ed76a05..0c1f7ccd3390 100644 --- a/drivers/video/rockchip/rga3/rga_drv.c +++ b/drivers/video/rockchip/rga3/rga_drv.c @@ -1156,10 +1156,10 @@ static irqreturn_t rga3_irq_handler(int irq, void *data) struct rga_scheduler_t *scheduler = data; if (DEBUGGER_EN(INT_FLAG)) - pr_info("irqthread INT[%x],STATS0[%x], STATS1[%x]\n", + pr_info("irq handler, INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n", rga_read(RGA3_INT_RAW, scheduler), rga_read(RGA3_STATUS0, scheduler), - rga_read(RGA3_STATUS1, scheduler)); + rga_read(RGA3_CMD_STATE, scheduler)); /* TODO: if error interrupt then soft reset hardware */ //scheduler->ops->soft_reset(job->core); @@ -1183,10 +1183,10 @@ static irqreturn_t rga3_irq_thread(int irq, void *data) } if (DEBUGGER_EN(INT_FLAG)) - pr_info("irq INT[%x], STATS0[%x], STATS1[%x]\n", + pr_info("irq thread, INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n", rga_read(RGA3_INT_RAW, scheduler), rga_read(RGA3_STATUS0, scheduler), - rga_read(RGA3_STATUS1, scheduler)); + rga_read(RGA3_CMD_STATE, scheduler)); rga_job_done(scheduler, 0); @@ -1198,16 +1198,18 @@ static irqreturn_t rga2_irq_handler(int irq, void *data) struct rga_scheduler_t *scheduler = data; if (DEBUGGER_EN(INT_FLAG)) - pr_info("irqthread INT[%x],STATS0[%x]\n", - rga_read(RGA2_INT, scheduler), rga_read(RGA2_STATUS, - scheduler)); + pr_info("irq handler, INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n", + rga_read(RGA2_INT, scheduler), + rga_read(RGA2_STATUS2, scheduler), + rga_read(RGA2_STATUS1, scheduler)); /*if error interrupt then soft reset hardware */ //warning if (rga_read(RGA2_INT, scheduler) & 0x01) { - pr_err("err irq! INT[%x],STATS0[%x]\n", - rga_read(RGA2_INT, scheduler), - rga_read(RGA2_STATUS, scheduler)); + pr_err("irq handler err! INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n", + rga_read(RGA2_INT, scheduler), + rga_read(RGA2_STATUS2, scheduler), + rga_read(RGA2_STATUS1, scheduler)); scheduler->ops->soft_reset(scheduler); } @@ -1230,14 +1232,13 @@ static irqreturn_t rga2_irq_thread(int irq, void *data) return IRQ_HANDLED; if (DEBUGGER_EN(INT_FLAG)) - pr_info("irq INT[%x], STATS0[%x]\n", - rga_read(RGA2_INT, scheduler), rga_read(RGA2_STATUS, - scheduler)); + pr_info("irq thread, INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n", + rga_read(RGA2_INT, scheduler), + rga_read(RGA2_STATUS2, scheduler), + rga_read(RGA2_STATUS1, scheduler)); - job->rga_command_base.osd_info.cur_flags0 = rga_read(RGA2_OSD_CUR_FLAGS0_OFFSET, - scheduler); - job->rga_command_base.osd_info.cur_flags1 = rga_read(RGA2_OSD_CUR_FLAGS1_OFFSET, - scheduler); + job->rga_command_base.osd_info.cur_flags0 = rga_read(RGA2_OSD_CUR_FLAGS0, scheduler); + job->rga_command_base.osd_info.cur_flags1 = rga_read(RGA2_OSD_CUR_FLAGS1, scheduler); rga_job_done(scheduler, 0);