diff --git a/drivers/video/rockchip/dp/Kconfig b/drivers/video/rockchip/dp/Kconfig
deleted file mode 100644
index 1dd5cf2ed802..000000000000
--- a/drivers/video/rockchip/dp/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "DP"
-
-config ROCKCHIP_DP
-	tristate "ROCKCHIP fb cdn dp driver"
-	depends on RK_HDMI
-	select SND_SOC_HDMI_CODEC if SND_SOC
-	help
-	  This selects support for Rockchip SoC specific extensions
-	  for the cdn DP driver. If you want to enable Dp on
-	  RK3399 based SoC with rkfb, you should select this
-	  option.
-endmenu
diff --git a/drivers/video/rockchip/dp/Makefile b/drivers/video/rockchip/dp/Makefile
deleted file mode 100644
index bb86dd5ec24c..000000000000
--- a/drivers/video/rockchip/dp/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_ROCKCHIP_DP) += rockchip_dp_core.o rockchip_dp.o cdn-dp-fb-reg.o
diff --git a/drivers/video/rockchip/dp/cdn-dp-fb-reg.c b/drivers/video/rockchip/dp/cdn-dp-fb-reg.c
deleted file mode 100644
index 8e603e019f57..000000000000
--- a/drivers/video/rockchip/dp/cdn-dp-fb-reg.c
+++ /dev/null
@@ -1,960 +0,0 @@
-/*
- * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
- * Author: Chris Zhong <zyw@rock-chips.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/clk.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/reset.h>
-
-#include "cdn-dp-fb-reg.h"
-
-#define CDN_DP_SPDIF_CLK		200000000
-#define FW_ALIVE_TIMEOUT_US		1000000
-#define MAILBOX_RETRY_US		1000
-#define MAILBOX_TIMEOUT_US		5000000
-#define LINK_TRAINING_RETRY_MS		20
-#define LINK_TRAINING_TIMEOUT_MS	500
-
-void cdn_dp_fb_set_fw_clk(struct cdn_dp_device *dp, u32 clk)
-{
-	writel(clk / 1000000, dp->regs + SW_CLK_H);
-}
-
-void cdn_dp_fb_clock_reset(struct cdn_dp_device *dp)
-{
-	u32 val;
-
-	val = DPTX_FRMR_DATA_CLK_RSTN_EN |
-	      DPTX_FRMR_DATA_CLK_EN |
-	      DPTX_PHY_DATA_RSTN_EN |
-	      DPTX_PHY_DATA_CLK_EN |
-	      DPTX_PHY_CHAR_RSTN_EN |
-	      DPTX_PHY_CHAR_CLK_EN |
-	      SOURCE_AUX_SYS_CLK_RSTN_EN |
-	      SOURCE_AUX_SYS_CLK_EN |
-	      DPTX_SYS_CLK_RSTN_EN |
-	      DPTX_SYS_CLK_EN |
-	      CFG_DPTX_VIF_CLK_RSTN_EN |
-	      CFG_DPTX_VIF_CLK_EN;
-	writel(val, dp->regs + SOURCE_DPTX_CAR);
-
-	val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN;
-	writel(val, dp->regs + SOURCE_PHY_CAR);
-
-	val = SOURCE_PKT_SYS_RSTN_EN |
-	      SOURCE_PKT_SYS_CLK_EN |
-	      SOURCE_PKT_DATA_RSTN_EN |
-	      SOURCE_PKT_DATA_CLK_EN;
-	writel(val, dp->regs + SOURCE_PKT_CAR);
-
-	val = SPDIF_CDR_CLK_RSTN_EN |
-	      SPDIF_CDR_CLK_EN |
-	      SOURCE_AIF_SYS_RSTN_EN |
-	      SOURCE_AIF_SYS_CLK_EN |
-	      SOURCE_AIF_CLK_RSTN_EN |
-	      SOURCE_AIF_CLK_EN;
-	writel(val, dp->regs + SOURCE_AIF_CAR);
-
-	val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN |
-	      SOURCE_CIPHER_SYS_CLK_EN |
-	      SOURCE_CIPHER_CHAR_CLK_RSTN_EN |
-	      SOURCE_CIPHER_CHAR_CLK_EN;
-	writel(val, dp->regs + SOURCE_CIPHER_CAR);
-
-	val = SOURCE_CRYPTO_SYS_CLK_RSTN_EN |
-	      SOURCE_CRYPTO_SYS_CLK_EN;
-	writel(val, dp->regs + SOURCE_CRYPTO_CAR);
-
-	val = ~(MAILBOX_INT_MASK_BIT | PIF_INT_MASK_BIT) & ALL_INT_MASK;
-	writel(val, dp->regs + APB_INT_MASK);
-}
-
-static int cdn_dp_fb_mailbox_read(struct cdn_dp_device *dp, bool force)
-{
-	int val, ret;
-
-	if (!dp->fw_actived && !force)
-		return -EPERM;
-
-	ret = readx_poll_timeout(readl, dp->regs + MAILBOX_EMPTY_ADDR,
-				 val, !val, MAILBOX_RETRY_US,
-				 MAILBOX_TIMEOUT_US);
-	if (ret < 0)
-		return ret;
-
-	return readl(dp->regs + MAILBOX0_RD_DATA) & 0xff;
-}
-
-static int cdn_dp_fb_mailbox_write(struct cdn_dp_device *dp, u8 val, bool force)
-{
-	int ret, full;
-
-	if (!dp->fw_actived && !force)
-		return -EPERM;
-
-	ret = readx_poll_timeout(readl, dp->regs + MAILBOX_FULL_ADDR,
-				 full, !full, MAILBOX_RETRY_US,
-				 MAILBOX_TIMEOUT_US);
-	if (ret < 0)
-		return ret;
-
-	writel(val, dp->regs + MAILBOX0_WR_DATA);
-
-	return 0;
-}
-
-static int cdn_dp_fb_mailbox_validate_receive(struct cdn_dp_device *dp,
-					   u8 module_id, u8 opcode,
-					   u8 req_size)
-{
-	u32 mbox_size, i;
-	u8 header[4];
-	int ret;
-
-	/* read the header of the message */
-	for (i = 0; i < 4; i++) {
-		ret = cdn_dp_fb_mailbox_read(dp, 0);
-		if (ret < 0)
-			return ret;
-
-		header[i] = ret;
-	}
-
-	mbox_size = (header[2] << 8) | header[3];
-
-	if (opcode != header[0] || module_id != header[1] ||
-	    req_size != mbox_size) {
-		/*
-		 * If the message in mailbox is not what we want, we need to
-		 * clear the mailbox by reading its contents.
-		 */
-		for (i = 0; i < mbox_size; i++)
-			if (cdn_dp_fb_mailbox_read(dp, 0) < 0)
-				break;
-
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int cdn_dp_fb_mailbox_read_receive(struct cdn_dp_device *dp,
-				       u8 *buff, u8 buff_size)
-{
-	u32 i;
-	int ret;
-
-	for (i = 0; i < buff_size; i++) {
-		ret = cdn_dp_fb_mailbox_read(dp, 0);
-		if (ret < 0)
-			return ret;
-
-		buff[i] = ret;
-	}
-
-	return 0;
-}
-
-static int cdn_dp_fb_mailbox_send(struct cdn_dp_device *dp, u8 module_id,
-			       u8 opcode, u16 size, u8 *message)
-{
-	u8 header[4];
-	int ret, i;
-
-	header[0] = opcode;
-	header[1] = module_id;
-	header[2] = (size >> 8) & 0xff;
-	header[3] = size & 0xff;
-
-	for (i = 0; i < 4; i++) {
-		ret = cdn_dp_fb_mailbox_write(dp, header[i], 0);
-		if (ret)
-			return ret;
-	}
-
-	for (i = 0; i < size; i++) {
-		ret = cdn_dp_fb_mailbox_write(dp, message[i], 0);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static int cdn_dp_fb_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val)
-{
-	u8 msg[6];
-
-	msg[0] = (addr >> 8) & 0xff;
-	msg[1] = addr & 0xff;
-	msg[2] = (val >> 24) & 0xff;
-	msg[3] = (val >> 16) & 0xff;
-	msg[4] = (val >> 8) & 0xff;
-	msg[5] = val & 0xff;
-	return cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_WRITE_REGISTER,
-				   sizeof(msg), msg);
-}
-
-static int cdn_dp_fb_reg_write_bit(struct cdn_dp_device *dp, u16 addr,
-				u8 start_bit, u8 bits_no, u32 val)
-{
-	u8 field[8];
-
-	field[0] = (addr >> 8) & 0xff;
-	field[1] = addr & 0xff;
-	field[2] = start_bit;
-	field[3] = bits_no;
-	field[4] = (val >> 24) & 0xff;
-	field[5] = (val >> 16) & 0xff;
-	field[6] = (val >> 8) & 0xff;
-	field[7] = val & 0xff;
-
-	return cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_WRITE_FIELD,
-				   sizeof(field), field);
-}
-
-int cdn_dp_fb_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len)
-{
-	u8 msg[5], reg[5];
-	int ret;
-
-	msg[0] = (len >> 8) & 0xff;
-	msg[1] = len & 0xff;
-	msg[2] = (addr >> 16) & 0xff;
-	msg[3] = (addr >> 8) & 0xff;
-	msg[4] = addr & 0xff;
-	ret = cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_READ_DPCD,
-				  sizeof(msg), msg);
-	if (ret)
-		goto err_dpcd_read;
-
-	ret = cdn_dp_fb_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
-					      DPTX_READ_DPCD,
-					      sizeof(reg) + len);
-	if (ret)
-		goto err_dpcd_read;
-
-	ret = cdn_dp_fb_mailbox_read_receive(dp, reg, sizeof(reg));
-	if (ret)
-		goto err_dpcd_read;
-
-	ret = cdn_dp_fb_mailbox_read_receive(dp, data, len);
-
-err_dpcd_read:
-	return ret;
-}
-
-int cdn_dp_fb_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value)
-{
-	u8 msg[6], reg[5];
-	int ret;
-
-	msg[0] = 0;
-	msg[1] = 1;
-	msg[2] = (addr >> 16) & 0xff;
-	msg[3] = (addr >> 8) & 0xff;
-	msg[4] = addr & 0xff;
-	msg[5] = value;
-	ret = cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_WRITE_DPCD,
-				  sizeof(msg), msg);
-	if (ret)
-		goto err_dpcd_write;
-
-	ret = cdn_dp_fb_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
-					      DPTX_WRITE_DPCD, sizeof(reg));
-	if (ret)
-		goto err_dpcd_write;
-
-	ret = cdn_dp_fb_mailbox_read_receive(dp, reg, sizeof(reg));
-	if (ret)
-		goto err_dpcd_write;
-
-	if (addr != (reg[2] << 16 | reg[3] << 8 | reg[4]))
-		ret = -EINVAL;
-
-err_dpcd_write:
-	if (ret)
-		dev_err(dp->dev, "dpcd write failed: %d\n", ret);
-	return ret;
-}
-
-int cdn_dp_fb_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem,
-			 u32 i_size, const u32 *d_mem, u32 d_size)
-{
-	u32 reg;
-	int i, ret;
-
-	/* reset ucpu before load firmware*/
-	writel(APB_IRAM_PATH | APB_DRAM_PATH | APB_XT_RESET,
-	       dp->regs + APB_CTRL);
-
-	for (i = 0; i < i_size; i += 4)
-		writel(*i_mem++, dp->regs + ADDR_IMEM + i);
-
-	for (i = 0; i < d_size; i += 4)
-		writel(*d_mem++, dp->regs + ADDR_DMEM + i);
-
-	/* un-reset ucpu */
-	writel(0, dp->regs + APB_CTRL);
-
-	/* check the keep alive register to make sure fw working */
-	ret = readx_poll_timeout(readl, dp->regs + KEEP_ALIVE,
-				 reg, reg, 2000, FW_ALIVE_TIMEOUT_US);
-	if (ret < 0) {
-		dev_err(dp->dev, "failed to loaded the FW reg = %x\n", reg);
-		return -EINVAL;
-	}
-
-	reg = readl(dp->regs + VER_L) & 0xff;
-	dp->fw_version = reg;
-	reg = readl(dp->regs + VER_H) & 0xff;
-	dp->fw_version |= reg << 8;
-	reg = readl(dp->regs + VER_LIB_L_ADDR) & 0xff;
-	dp->fw_version |= reg << 16;
-	reg = readl(dp->regs + VER_LIB_H_ADDR) & 0xff;
-	dp->fw_version |= reg << 24;
-
-	dev_dbg(dp->dev, "firmware version: %x\n", dp->fw_version);
-
-	return 0;
-}
-
-int cdn_dp_fb_set_firmware_active(struct cdn_dp_device *dp, bool enable)
-{
-	u8 msg[5];
-	int ret, i;
-
-	msg[0] = GENERAL_MAIN_CONTROL;
-	msg[1] = MB_MODULE_ID_GENERAL;
-	msg[2] = 0;
-	msg[3] = 1;
-	msg[4] = enable ? FW_ACTIVE : FW_STANDBY;
-
-	for (i = 0; i < sizeof(msg); i++) {
-		ret = cdn_dp_fb_mailbox_write(dp, msg[i], 1);
-		if (ret)
-			goto err_set_firmware_active;
-	}
-
-	/* read the firmware state */
-	for (i = 0; i < sizeof(msg); i++)  {
-		ret = cdn_dp_fb_mailbox_read(dp, 1);
-		if (ret < 0)
-			goto err_set_firmware_active;
-
-		msg[i] = ret;
-	}
-
-	dp->fw_actived = (msg[4] == FW_ACTIVE);
-	ret = 0;
-
-err_set_firmware_active:
-	if (ret < 0)
-		dev_err(dp->dev, "set firmware active failed\n");
-	return ret;
-}
-
-int cdn_dp_fb_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip)
-{
-	u8 msg[8];
-	int ret;
-
-	msg[0] = CDN_DP_MAX_LINK_RATE;
-	msg[1] = lanes | (0x1 << 4);
-	msg[2] = VOLTAGE_LEVEL_2;
-	msg[3] = PRE_EMPHASIS_LEVEL_3;
-	msg[4] = PTS1 | PTS2 | PTS3 | PTS4;
-	msg[5] = FAST_LT_NOT_SUPPORT;
-	msg[6] = flip ? LANE_MAPPING_FLIPPED : LANE_MAPPING_NORMAL;
-	msg[7] = ENHANCED;
-
-	ret = cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX,
-				  DPTX_SET_HOST_CAPABILITIES,
-				  sizeof(msg), msg);
-	if (ret)
-		goto err_set_host_cap;
-
-	ret = cdn_dp_fb_reg_write(dp, DP_AUX_SWAP_INVERSION_CONTROL,
-			       AUX_HOST_INVERT);
-
-err_set_host_cap:
-	if (ret)
-		dev_err(dp->dev, "set host cap failed: %d\n", ret);
-	return ret;
-}
-
-int cdn_dp_fb_event_config(struct cdn_dp_device *dp)
-{
-	u8 msg[5];
-	int ret;
-
-	memset(msg, 0, sizeof(msg));
-
-	msg[0] = DPTX_EVENT_ENABLE_HPD | DPTX_EVENT_ENABLE_TRAINING;
-
-	ret = cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_ENABLE_EVENT,
-				  sizeof(msg), msg);
-	if (ret)
-		dev_err(dp->dev, "set event config failed: %d\n", ret);
-
-	return ret;
-}
-
-u32 cdn_dp_fb_get_event(struct cdn_dp_device *dp)
-{
-	return readl(dp->regs + SW_EVENTS0);
-}
-
-int cdn_dp_fb_get_hpd_status(struct cdn_dp_device *dp)
-{
-	u8 status;
-	int ret;
-
-	ret = cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_HPD_STATE,
-				  0, NULL);
-	if (ret)
-		goto err_get_hpd;
-
-	ret = cdn_dp_fb_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
-					      DPTX_HPD_STATE, sizeof(status));
-	if (ret)
-		goto err_get_hpd;
-
-	ret = cdn_dp_fb_mailbox_read_receive(dp, &status, sizeof(status));
-	if (ret)
-		goto err_get_hpd;
-
-	return status;
-
-err_get_hpd:
-	dev_err(dp->dev, "get hpd status failed: %d\n", ret);
-	return ret;
-}
-
-int cdn_dp_fb_get_edid_block(void *data, u8 *edid,
-			  unsigned int block, size_t length)
-{
-	struct cdn_dp_device *dp = data;
-	u8 msg[2], reg[2], i;
-	int ret;
-
-	for (i = 0; i < 4; i++) {
-		msg[0] = block / 2;
-		msg[1] = block % 2;
-
-		ret = cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_GET_EDID,
-					  sizeof(msg), msg);
-		if (ret)
-			continue;
-
-		ret = cdn_dp_fb_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
-						      DPTX_GET_EDID,
-						      sizeof(reg) + length);
-		if (ret)
-			continue;
-
-		ret = cdn_dp_fb_mailbox_read_receive(dp, reg, sizeof(reg));
-		if (ret)
-			continue;
-
-		ret = cdn_dp_fb_mailbox_read_receive(dp, edid, length);
-		if (ret)
-			continue;
-
-		if (reg[0] == length && reg[1] == block / 2)
-			break;
-	}
-
-	if (ret)
-		dev_err(dp->dev, "get block[%d] edid failed: %d\n", block, ret);
-
-	return ret;
-}
-
-int cdn_dp_fb_training_start(struct cdn_dp_device *dp)
-{
-	unsigned long timeout;
-	u8 msg, event[2];
-	int ret;
-
-	msg = LINK_TRAINING_RUN;
-
-	/* start training */
-	ret = cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_TRAINING_CONTROL,
-				  sizeof(msg), &msg);
-	if (ret)
-		goto err_training_start;
-
-	timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS);
-	while (time_before(jiffies, timeout)) {
-		msleep(LINK_TRAINING_RETRY_MS);
-		ret = cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX,
-					  DPTX_READ_EVENT, 0, NULL);
-		if (ret)
-			goto err_training_start;
-
-		ret = cdn_dp_fb_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
-						      DPTX_READ_EVENT,
-						      sizeof(event));
-		if (ret)
-			goto err_training_start;
-
-		ret = cdn_dp_fb_mailbox_read_receive(dp, event, sizeof(event));
-		if (ret)
-			goto err_training_start;
-
-		if (event[1] & EQ_PHASE_FINISHED)
-			return 0;
-	}
-
-	ret = -ETIMEDOUT;
-
-err_training_start:
-	dev_err(dp->dev, "training failed: %d\n", ret);
-	return ret;
-}
-
-int cdn_dp_fb_get_training_status(struct cdn_dp_device *dp)
-{
-	u8 status[10];
-	int ret;
-
-	ret = cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_READ_LINK_STAT,
-				  0, NULL);
-	if (ret)
-		goto err_get_training_status;
-
-	ret = cdn_dp_fb_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
-					      DPTX_READ_LINK_STAT,
-					      sizeof(status));
-	if (ret)
-		goto err_get_training_status;
-
-	ret = cdn_dp_fb_mailbox_read_receive(dp, status, sizeof(status));
-	if (ret)
-		goto err_get_training_status;
-
-	dp->link.rate = status[0];
-	dp->link.num_lanes = status[1];
-
-err_get_training_status:
-	if (ret)
-		dev_err(dp->dev, "get training status failed: %d\n", ret);
-	return ret;
-}
-
-int cdn_dp_fb_set_video_status(struct cdn_dp_device *dp, int active)
-{
-	u8 msg;
-	int ret;
-
-	msg = !!active;
-
-	ret = cdn_dp_fb_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_SET_VIDEO,
-				  sizeof(msg), &msg);
-	if (ret)
-		dev_err(dp->dev, "set video status failed: %d\n", ret);
-
-	return ret;
-}
-
-static int cdn_dp_fb_get_msa_misc(struct video_info *video,
-			       struct drm_display_mode *mode)
-{
-	u32 msa_misc;
-	u8 val[2];
-
-	switch (video->color_fmt) {
-	case PXL_RGB:
-	case Y_ONLY:
-		val[0] = 0;
-		break;
-	/* set YUV default color space conversion to BT601 */
-	case YCBCR_4_4_4:
-		val[0] = 6 + BT_601 * 8;
-		break;
-	case YCBCR_4_2_2:
-		val[0] = 5 + BT_601 * 8;
-		break;
-	case YCBCR_4_2_0:
-		val[0] = 5;
-		break;
-	};
-
-	switch (video->color_depth) {
-	case 6:
-		val[1] = 0;
-		break;
-	case 8:
-		val[1] = 1;
-		break;
-	case 10:
-		val[1] = 2;
-		break;
-	case 12:
-		val[1] = 3;
-		break;
-	case 16:
-		val[1] = 4;
-		break;
-	};
-
-	msa_misc = 2 * val[0] + 32 * val[1] +
-		   ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0);
-
-	return msa_misc;
-}
-
-int cdn_dp_fb_config_video(struct cdn_dp_device *dp)
-{
-	struct video_info *video = &dp->video_info;
-	struct drm_display_mode *mode = &dp->mode;
-	u64 symbol, tmp;
-	u32 val, link_rate;
-	u8 bit_per_pix, tu_size_reg = TU_SIZE;
-	int ret;
-
-	bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ?
-		      (video->color_depth * 2) : (video->color_depth * 3);
-
-	link_rate = drm_dp_bw_code_to_link_rate(dp->link.rate) / 1000;
-
-	val = VIF_BYPASS_INTERLACE;
-	ret = cdn_dp_fb_reg_write(dp, BND_HSYNC2VSYNC, val);
-	if (ret)
-		goto err_config_video;
-
-	ret = cdn_dp_fb_reg_write(dp, HSYNC2VSYNC_POL_CTRL, 0);
-	if (ret)
-		goto err_config_video;
-
-	/*
-	 * get a best tu_size and valid symbol:
-	 * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32
-	 * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes)
-	 * 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set
-	 *    TU += 2 and repeat 2nd step.
-	 */
-	do {
-		tu_size_reg += 2;
-		tmp = tu_size_reg * mode->clock * bit_per_pix;
-		tmp /= dp->link.num_lanes * link_rate * 8;
-		symbol = tmp / 1000;
-	} while ((symbol <= 1) || (tu_size_reg - symbol < 4) ||
-		 (tmp % 1000 > 850) || (tmp % 1000 < 100));
-
-	val = symbol + (tu_size_reg << 8);
-	ret = cdn_dp_fb_reg_write(dp, DP_FRAMER_TU, val);
-	if (ret)
-		goto err_config_video;
-
-	/* set the FIFO Buffer size */
-	val = ((mode->clock * (symbol + 1) / 1000) + link_rate);
-	val /= (dp->link.num_lanes * link_rate);
-	val = 8 * (symbol + 1) / bit_per_pix - val;
-	val += 2;
-	ret = cdn_dp_fb_reg_write(dp, DP_VC_TABLE(15), val);
-
-	switch (video->color_depth) {
-	case 6:
-		val = BCS_6;
-		break;
-	case 8:
-		val = BCS_8;
-		break;
-	case 10:
-		val = BCS_10;
-		break;
-	case 12:
-		val = BCS_12;
-		break;
-	case 16:
-		val = BCS_16;
-		break;
-	};
-
-	val += video->color_fmt << 8;
-	ret = cdn_dp_fb_reg_write(dp, DP_FRAMER_PXL_REPR, val);
-	if (ret)
-		goto err_config_video;
-
-	val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0;
-	val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0;
-	ret = cdn_dp_fb_reg_write(dp, DP_FRAMER_SP, val);
-	if (ret)
-		goto err_config_video;
-
-	val = (mode->hsync_start - mode->hdisplay) << 16;
-	val |= mode->htotal - mode->hsync_end;
-	ret = cdn_dp_fb_reg_write(dp, DP_FRONT_BACK_PORCH, val);
-	if (ret)
-		goto err_config_video;
-
-	val = mode->hdisplay * bit_per_pix / 8;
-	ret = cdn_dp_fb_reg_write(dp, DP_BYTE_COUNT, val);
-	if (ret)
-		goto err_config_video;
-
-	val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16);
-	ret = cdn_dp_fb_reg_write(dp, MSA_HORIZONTAL_0, val);
-	if (ret)
-		goto err_config_video;
-
-	val = mode->hsync_end - mode->hsync_start;
-	val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15);
-	ret = cdn_dp_fb_reg_write(dp, MSA_HORIZONTAL_1, val);
-	if (ret)
-		goto err_config_video;
-
-	val = mode->vtotal;
-	val |= ((mode->vtotal - mode->vsync_start) << 16);
-	ret = cdn_dp_fb_reg_write(dp, MSA_VERTICAL_0, val);
-	if (ret)
-		goto err_config_video;
-
-	val = mode->vsync_end - mode->vsync_start;
-	val |= mode->vdisplay << 16 | (video->v_sync_polarity << 15);
-	ret = cdn_dp_fb_reg_write(dp, MSA_VERTICAL_1, val);
-	if (ret)
-		goto err_config_video;
-
-	val = cdn_dp_fb_get_msa_misc(video, mode);
-	ret = cdn_dp_fb_reg_write(dp, MSA_MISC, val);
-	if (ret)
-		goto err_config_video;
-
-	ret = cdn_dp_fb_reg_write(dp, STREAM_CONFIG, 1);
-	if (ret)
-		goto err_config_video;
-
-	val = mode->hsync_end - mode->hsync_start;
-	val |= (mode->hdisplay << 16);
-	ret = cdn_dp_fb_reg_write(dp, DP_HORIZONTAL, val);
-	if (ret)
-		goto err_config_video;
-
-	val = mode->vtotal;
-	val -= (mode->vtotal - mode->vdisplay);
-	val |= (mode->vtotal - mode->vsync_start) << 16;
-	ret = cdn_dp_fb_reg_write(dp, DP_VERTICAL_0, val);
-	if (ret)
-		goto err_config_video;
-
-	val = mode->vtotal;
-	ret = cdn_dp_fb_reg_write(dp, DP_VERTICAL_1, val);
-	if (ret)
-		goto err_config_video;
-
-	val =  0;
-	ret = cdn_dp_fb_reg_write_bit(dp, DP_VB_ID, 2, 1, val);
-
-err_config_video:
-	if (ret)
-		dev_err(dp->dev, "config video failed: %d\n", ret);
-	return ret;
-}
-
-int cdn_dp_fb_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio)
-{
-	u32 val;
-	int ret;
-
-	ret = cdn_dp_fb_reg_write(dp, AUDIO_PACK_CONTROL, 0);
-	if (ret) {
-		dev_err(dp->dev, "audio stop failed: %d\n", ret);
-		return ret;
-	}
-
-	val = SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS;
-	val |= SPDIF_FIFO_MID_RANGE(0xe0);
-	val |= SPDIF_JITTER_THRSH(0xe0);
-	val |= SPDIF_JITTER_AVG_WIN(7);
-	writel(val, dp->regs + SPDIF_CTRL_ADDR);
-
-	/* clearn the audio config and reset */
-	writel(0, dp->regs + AUDIO_SRC_CNTL);
-	writel(0, dp->regs + AUDIO_SRC_CNFG);
-	writel(AUDIO_SW_RST, dp->regs + AUDIO_SRC_CNTL);
-	writel(0, dp->regs + AUDIO_SRC_CNTL);
-
-	/* reset smpl2pckt component  */
-	writel(0, dp->regs + SMPL2PKT_CNTL);
-	writel(AUDIO_SW_RST, dp->regs + SMPL2PKT_CNTL);
-	writel(0, dp->regs + SMPL2PKT_CNTL);
-
-	/* reset FIFO */
-	writel(AUDIO_SW_RST, dp->regs + FIFO_CNTL);
-	writel(0, dp->regs + FIFO_CNTL);
-
-	if (audio->format == AFMT_SPDIF)
-		clk_disable_unprepare(dp->spdif_clk);
-
-	return 0;
-}
-
-int cdn_dp_fb_audio_mute(struct cdn_dp_device *dp, bool enable)
-{
-	int ret;
-
-	ret = cdn_dp_fb_reg_write_bit(dp, DP_VB_ID, 4, 1, enable);
-	if (ret)
-		dev_err(dp->dev, "audio mute failed: %d\n", ret);
-
-	return ret;
-}
-
-static void cdn_dp_fb_audio_config_i2s(struct cdn_dp_device *dp,
-				    struct audio_info *audio)
-{
-	int sub_pckt_num = 1, i2s_port_en_val = 0xf, i;
-	u32 val;
-
-	if (audio->channels == 2) {
-		if (dp->link.num_lanes == 1)
-			sub_pckt_num = 2;
-		else
-			sub_pckt_num = 4;
-
-		i2s_port_en_val = 1;
-	} else if (audio->channels == 4) {
-		i2s_port_en_val = 3;
-	}
-
-	writel(0x0, dp->regs + SPDIF_CTRL_ADDR);
-
-	writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL);
-
-	val = MAX_NUM_CH(audio->channels);
-	val |= NUM_OF_I2S_PORTS(audio->channels);
-	val |= AUDIO_TYPE_LPCM;
-	val |= CFG_SUB_PCKT_NUM(sub_pckt_num);
-	writel(val, dp->regs + SMPL2PKT_CNFG);
-
-	if (audio->sample_width == 16)
-		val = 0;
-	else if (audio->sample_width == 24)
-		val = 1 << 9;
-	else
-		val = 2 << 9;
-
-	val |= AUDIO_CH_NUM(audio->channels);
-	val |= I2S_DEC_PORT_EN(i2s_port_en_val);
-	val |= TRANS_SMPL_WIDTH_32;
-	writel(val, dp->regs + AUDIO_SRC_CNFG);
-
-	for (i = 0; i < (audio->channels + 1) / 2; i++) {
-		if (audio->sample_width == 16)
-			val = (0x08 << 8) | (0x08 << 20);
-		else if (audio->sample_width == 24)
-			val = (0x0b << 8) | (0x0b << 20);
-
-		val |= ((2 * i) << 4) | ((2 * i + 1) << 16);
-		writel(val, dp->regs + STTS_BIT_CH(i));
-	}
-
-	switch (audio->sample_rate) {
-	case 32000:
-		val = SAMPLING_FREQ(3) |
-		      ORIGINAL_SAMP_FREQ(0xc);
-		break;
-	case 44100:
-		val = SAMPLING_FREQ(0) |
-		      ORIGINAL_SAMP_FREQ(0xf);
-		break;
-	case 48000:
-		val = SAMPLING_FREQ(2) |
-		      ORIGINAL_SAMP_FREQ(0xd);
-		break;
-	case 88200:
-		val = SAMPLING_FREQ(8) |
-		      ORIGINAL_SAMP_FREQ(0x7);
-		break;
-	case 96000:
-		val = SAMPLING_FREQ(0xa) |
-		      ORIGINAL_SAMP_FREQ(5);
-		break;
-	case 176400:
-		val = SAMPLING_FREQ(0xc) |
-		      ORIGINAL_SAMP_FREQ(3);
-		break;
-	case 192000:
-		val = SAMPLING_FREQ(0xe) |
-		      ORIGINAL_SAMP_FREQ(1);
-		break;
-	}
-	val |= 4;
-	writel(val, dp->regs + COM_CH_STTS_BITS);
-
-	writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL);
-	writel(I2S_DEC_START, dp->regs + AUDIO_SRC_CNTL);
-}
-
-static void cdn_dp_fb_audio_config_spdif(struct cdn_dp_device *dp)
-{
-	u32 val;
-
-	val = SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS;
-	val |= SPDIF_FIFO_MID_RANGE(0xe0);
-	val |= SPDIF_JITTER_THRSH(0xe0);
-	val |= SPDIF_JITTER_AVG_WIN(7);
-	writel(val, dp->regs + SPDIF_CTRL_ADDR);
-
-	writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL);
-
-	val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4);
-	writel(val, dp->regs + SMPL2PKT_CNFG);
-	writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL);
-
-	val = SPDIF_ENABLE | SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS;
-	val |= SPDIF_FIFO_MID_RANGE(0xe0);
-	val |= SPDIF_JITTER_THRSH(0xe0);
-	val |= SPDIF_JITTER_AVG_WIN(7);
-	writel(val, dp->regs + SPDIF_CTRL_ADDR);
-
-	clk_prepare_enable(dp->spdif_clk);
-	clk_set_rate(dp->spdif_clk, CDN_DP_SPDIF_CLK);
-}
-
-int cdn_dp_fb_audio_config(struct cdn_dp_device *dp, struct audio_info *audio)
-{
-	int ret;
-
-	/* reset the spdif clk before config */
-	if (audio->format == AFMT_SPDIF) {
-		reset_control_assert(dp->spdif_rst);
-		reset_control_deassert(dp->spdif_rst);
-	}
-
-	ret = cdn_dp_fb_reg_write(dp, CM_LANE_CTRL, LANE_REF_CYC);
-	if (ret)
-		goto err_audio_config;
-
-	ret = cdn_dp_fb_reg_write(dp, CM_CTRL, 0);
-	if (ret)
-		goto err_audio_config;
-
-	if (audio->format == AFMT_I2S)
-		cdn_dp_fb_audio_config_i2s(dp, audio);
-	else
-		cdn_dp_fb_audio_config_spdif(dp);
-
-	ret = cdn_dp_fb_reg_write(dp, AUDIO_PACK_CONTROL, AUDIO_PACK_EN);
-
-err_audio_config:
-	if (ret)
-		dev_err(dp->dev, "audio config failed: %d\n", ret);
-	return ret;
-}
diff --git a/drivers/video/rockchip/dp/cdn-dp-fb-reg.h b/drivers/video/rockchip/dp/cdn-dp-fb-reg.h
deleted file mode 100644
index cbedf5cf4c7e..000000000000
--- a/drivers/video/rockchip/dp/cdn-dp-fb-reg.h
+++ /dev/null
@@ -1,577 +0,0 @@
-/*
- * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
- * Author: Chris Zhong <zyw@rock-chips.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _CDN_DP_REG_H
-#define _CDN_DP_REG_H
-
-#include <linux/wakelock.h>
-#include <linux/mutex.h>
-#include <linux/bitops.h>
-#include <drm/drmP.h>
-#include <drm/drm_crtc_helper.h>
-#include <drm/drm_dp_helper.h>
-#include <drm/drm_panel.h>
-
-#define MAX_PHY		2
-
-#define ADDR_IMEM		0x10000
-#define ADDR_DMEM		0x20000
-
-/* APB CFG addr */
-#define APB_CTRL			0
-#define XT_INT_CTRL			0x04
-#define MAILBOX_FULL_ADDR		0x08
-#define MAILBOX_EMPTY_ADDR		0x0c
-#define MAILBOX0_WR_DATA		0x10
-#define MAILBOX0_RD_DATA		0x14
-#define KEEP_ALIVE			0x18
-#define VER_L				0x1c
-#define VER_H				0x20
-#define VER_LIB_L_ADDR			0x24
-#define VER_LIB_H_ADDR			0x28
-#define SW_DEBUG_L			0x2c
-#define SW_DEBUG_H			0x30
-#define MAILBOX_INT_MASK		0x34
-#define MAILBOX_INT_STATUS		0x38
-#define SW_CLK_L			0x3c
-#define SW_CLK_H			0x40
-#define SW_EVENTS0			0x44
-#define SW_EVENTS1			0x48
-#define SW_EVENTS2			0x4c
-#define SW_EVENTS3			0x50
-#define XT_OCD_CTRL			0x60
-#define APB_INT_MASK			0x6c
-#define APB_STATUS_MASK			0x70
-
-/* audio decoder addr */
-#define AUDIO_SRC_CNTL			0x30000
-#define AUDIO_SRC_CNFG			0x30004
-#define COM_CH_STTS_BITS		0x30008
-#define STTS_BIT_CH(x)			(0x3000c + ((x) << 2))
-#define SPDIF_CTRL_ADDR			0x3004c
-#define SPDIF_CH1_CS_3100_ADDR		0x30050
-#define SPDIF_CH1_CS_6332_ADDR		0x30054
-#define SPDIF_CH1_CS_9564_ADDR		0x30058
-#define SPDIF_CH1_CS_12796_ADDR		0x3005c
-#define SPDIF_CH1_CS_159128_ADDR	0x30060
-#define SPDIF_CH1_CS_191160_ADDR	0x30064
-#define SPDIF_CH2_CS_3100_ADDR		0x30068
-#define SPDIF_CH2_CS_6332_ADDR		0x3006c
-#define SPDIF_CH2_CS_9564_ADDR		0x30070
-#define SPDIF_CH2_CS_12796_ADDR		0x30074
-#define SPDIF_CH2_CS_159128_ADDR	0x30078
-#define SPDIF_CH2_CS_191160_ADDR	0x3007c
-#define SMPL2PKT_CNTL			0x30080
-#define SMPL2PKT_CNFG			0x30084
-#define FIFO_CNTL			0x30088
-#define FIFO_STTS			0x3008c
-
-/* source pif addr */
-#define SOURCE_PIF_WR_ADDR		0x30800
-#define SOURCE_PIF_WR_REQ		0x30804
-#define SOURCE_PIF_RD_ADDR		0x30808
-#define SOURCE_PIF_RD_REQ		0x3080c
-#define SOURCE_PIF_DATA_WR		0x30810
-#define SOURCE_PIF_DATA_RD		0x30814
-#define SOURCE_PIF_FIFO1_FLUSH		0x30818
-#define SOURCE_PIF_FIFO2_FLUSH		0x3081c
-#define SOURCE_PIF_STATUS		0x30820
-#define SOURCE_PIF_INTERRUPT_SOURCE	0x30824
-#define SOURCE_PIF_INTERRUPT_MASK	0x30828
-#define SOURCE_PIF_PKT_ALLOC_REG	0x3082c
-#define SOURCE_PIF_PKT_ALLOC_WR_EN	0x30830
-#define SOURCE_PIF_SW_RESET		0x30834
-
-/* bellow registers need access by mailbox */
-/* source car addr */
-#define SOURCE_HDTX_CAR			0x0900
-#define SOURCE_DPTX_CAR			0x0904
-#define SOURCE_PHY_CAR			0x0908
-#define SOURCE_CEC_CAR			0x090c
-#define SOURCE_CBUS_CAR			0x0910
-#define SOURCE_PKT_CAR			0x0918
-#define SOURCE_AIF_CAR			0x091c
-#define SOURCE_CIPHER_CAR		0x0920
-#define SOURCE_CRYPTO_CAR		0x0924
-
-/* clock meters addr */
-#define CM_CTRL				0x0a00
-#define CM_I2S_CTRL			0x0a04
-#define CM_SPDIF_CTRL			0x0a08
-#define CM_VID_CTRL			0x0a0c
-#define CM_LANE_CTRL			0x0a10
-#define I2S_NM_STABLE			0x0a14
-#define I2S_NCTS_STABLE			0x0a18
-#define SPDIF_NM_STABLE			0x0a1c
-#define SPDIF_NCTS_STABLE		0x0a20
-#define NMVID_MEAS_STABLE		0x0a24
-#define I2S_MEAS			0x0a40
-#define SPDIF_MEAS			0x0a80
-#define NMVID_MEAS			0x0ac0
-
-/* source vif addr */
-#define BND_HSYNC2VSYNC			0x0b00
-#define HSYNC2VSYNC_F1_L1		0x0b04
-#define HSYNC2VSYNC_F2_L1		0x0b08
-#define HSYNC2VSYNC_STATUS		0x0b0c
-#define HSYNC2VSYNC_POL_CTRL		0x0b10
-
-/* dptx phy addr */
-#define DP_TX_PHY_CONFIG_REG		0x2000
-#define DP_TX_PHY_STATUS_REG		0x2004
-#define DP_TX_PHY_SW_RESET		0x2008
-#define DP_TX_PHY_SCRAMBLER_SEED	0x200c
-#define DP_TX_PHY_TRAINING_01_04	0x2010
-#define DP_TX_PHY_TRAINING_05_08	0x2014
-#define DP_TX_PHY_TRAINING_09_10	0x2018
-#define TEST_COR			0x23fc
-
-/* dptx hpd addr */
-#define HPD_IRQ_DET_MIN_TIMER		0x2100
-#define HPD_IRQ_DET_MAX_TIMER		0x2104
-#define HPD_UNPLGED_DET_MIN_TIMER	0x2108
-#define HPD_STABLE_TIMER		0x210c
-#define HPD_FILTER_TIMER		0x2110
-#define HPD_EVENT_MASK			0x211c
-#define HPD_EVENT_DET			0x2120
-
-/* dpyx framer addr */
-#define DP_FRAMER_GLOBAL_CONFIG		0x2200
-#define DP_SW_RESET			0x2204
-#define DP_FRAMER_TU			0x2208
-#define DP_FRAMER_PXL_REPR		0x220c
-#define DP_FRAMER_SP			0x2210
-#define AUDIO_PACK_CONTROL		0x2214
-#define DP_VC_TABLE(x)			(0x2218 + ((x) << 2))
-#define DP_VB_ID			0x2258
-#define DP_MTPH_LVP_CONTROL		0x225c
-#define DP_MTPH_SYMBOL_VALUES		0x2260
-#define DP_MTPH_ECF_CONTROL		0x2264
-#define DP_MTPH_ACT_CONTROL		0x2268
-#define DP_MTPH_STATUS			0x226c
-#define DP_INTERRUPT_SOURCE		0x2270
-#define DP_INTERRUPT_MASK		0x2274
-#define DP_FRONT_BACK_PORCH		0x2278
-#define DP_BYTE_COUNT			0x227c
-
-/* dptx stream addr */
-#define MSA_HORIZONTAL_0		0x2280
-#define MSA_HORIZONTAL_1		0x2284
-#define MSA_VERTICAL_0			0x2288
-#define MSA_VERTICAL_1			0x228c
-#define MSA_MISC			0x2290
-#define STREAM_CONFIG			0x2294
-#define AUDIO_PACK_STATUS		0x2298
-#define VIF_STATUS			0x229c
-#define PCK_STUFF_STATUS_0		0x22a0
-#define PCK_STUFF_STATUS_1		0x22a4
-#define INFO_PACK_STATUS		0x22a8
-#define RATE_GOVERNOR_STATUS		0x22ac
-#define DP_HORIZONTAL			0x22b0
-#define DP_VERTICAL_0			0x22b4
-#define DP_VERTICAL_1			0x22b8
-#define DP_BLOCK_SDP			0x22bc
-
-/* dptx glbl addr */
-#define DPTX_LANE_EN			0x2300
-#define DPTX_ENHNCD			0x2304
-#define DPTX_INT_MASK			0x2308
-#define DPTX_INT_STATUS			0x230c
-
-/* dp aux addr */
-#define DP_AUX_HOST_CONTROL		0x2800
-#define DP_AUX_INTERRUPT_SOURCE		0x2804
-#define DP_AUX_INTERRUPT_MASK		0x2808
-#define DP_AUX_SWAP_INVERSION_CONTROL	0x280c
-#define DP_AUX_SEND_NACK_TRANSACTION	0x2810
-#define DP_AUX_CLEAR_RX			0x2814
-#define DP_AUX_CLEAR_TX			0x2818
-#define DP_AUX_TIMER_STOP		0x281c
-#define DP_AUX_TIMER_CLEAR		0x2820
-#define DP_AUX_RESET_SW			0x2824
-#define DP_AUX_DIVIDE_2M		0x2828
-#define DP_AUX_TX_PREACHARGE_LENGTH	0x282c
-#define DP_AUX_FREQUENCY_1M_MAX		0x2830
-#define DP_AUX_FREQUENCY_1M_MIN		0x2834
-#define DP_AUX_RX_PRE_MIN		0x2838
-#define DP_AUX_RX_PRE_MAX		0x283c
-#define DP_AUX_TIMER_PRESET		0x2840
-#define DP_AUX_NACK_FORMAT		0x2844
-#define DP_AUX_TX_DATA			0x2848
-#define DP_AUX_RX_DATA			0x284c
-#define DP_AUX_TX_STATUS		0x2850
-#define DP_AUX_RX_STATUS		0x2854
-#define DP_AUX_RX_CYCLE_COUNTER		0x2858
-#define DP_AUX_MAIN_STATES		0x285c
-#define DP_AUX_MAIN_TIMER		0x2860
-#define DP_AUX_AFE_OUT			0x2864
-
-/* crypto addr */
-#define CRYPTO_HDCP_REVISION		0x5800
-#define HDCP_CRYPTO_CONFIG		0x5804
-#define CRYPTO_INTERRUPT_SOURCE		0x5808
-#define CRYPTO_INTERRUPT_MASK		0x580c
-#define CRYPTO22_CONFIG			0x5818
-#define CRYPTO22_STATUS			0x581c
-#define SHA_256_DATA_IN			0x583c
-#define SHA_256_DATA_OUT_(x)		(0x5850 + ((x) << 2))
-#define AES_32_KEY_(x)			(0x5870 + ((x) << 2))
-#define AES_32_DATA_IN			0x5880
-#define AES_32_DATA_OUT_(x)		(0x5884 + ((x) << 2))
-#define CRYPTO14_CONFIG			0x58a0
-#define CRYPTO14_STATUS			0x58a4
-#define CRYPTO14_PRNM_OUT		0x58a8
-#define CRYPTO14_KM_0			0x58ac
-#define CRYPTO14_KM_1			0x58b0
-#define CRYPTO14_AN_0			0x58b4
-#define CRYPTO14_AN_1			0x58b8
-#define CRYPTO14_YOUR_KSV_0		0x58bc
-#define CRYPTO14_YOUR_KSV_1		0x58c0
-#define CRYPTO14_MI_0			0x58c4
-#define CRYPTO14_MI_1			0x58c8
-#define CRYPTO14_TI_0			0x58cc
-#define CRYPTO14_KI_0			0x58d0
-#define CRYPTO14_KI_1			0x58d4
-#define CRYPTO14_BLOCKS_NUM		0x58d8
-#define CRYPTO14_KEY_MEM_DATA_0		0x58dc
-#define CRYPTO14_KEY_MEM_DATA_1		0x58e0
-#define CRYPTO14_SHA1_MSG_DATA		0x58e4
-#define CRYPTO14_SHA1_V_VALUE_(x)	(0x58e8 + ((x) << 2))
-#define TRNG_CTRL			0x58fc
-#define TRNG_DATA_RDY			0x5900
-#define TRNG_DATA			0x5904
-
-/* cipher addr */
-#define HDCP_REVISION			0x60000
-#define INTERRUPT_SOURCE		0x60004
-#define INTERRUPT_MASK			0x60008
-#define HDCP_CIPHER_CONFIG		0x6000c
-#define AES_128_KEY_0			0x60010
-#define AES_128_KEY_1			0x60014
-#define AES_128_KEY_2			0x60018
-#define AES_128_KEY_3			0x6001c
-#define AES_128_RANDOM_0		0x60020
-#define AES_128_RANDOM_1		0x60024
-#define CIPHER14_KM_0			0x60028
-#define CIPHER14_KM_1			0x6002c
-#define CIPHER14_STATUS			0x60030
-#define CIPHER14_RI_PJ_STATUS		0x60034
-#define CIPHER_MODE			0x60038
-#define CIPHER14_AN_0			0x6003c
-#define CIPHER14_AN_1			0x60040
-#define CIPHER22_AUTH			0x60044
-#define CIPHER14_R0_DP_STATUS		0x60048
-#define CIPHER14_BOOTSTRAP		0x6004c
-
-#define DPTX_FRMR_DATA_CLK_RSTN_EN	BIT(11)
-#define DPTX_FRMR_DATA_CLK_EN		BIT(10)
-#define DPTX_PHY_DATA_RSTN_EN		BIT(9)
-#define DPTX_PHY_DATA_CLK_EN		BIT(8)
-#define DPTX_PHY_CHAR_RSTN_EN		BIT(7)
-#define DPTX_PHY_CHAR_CLK_EN		BIT(6)
-#define SOURCE_AUX_SYS_CLK_RSTN_EN	BIT(5)
-#define SOURCE_AUX_SYS_CLK_EN		BIT(4)
-#define DPTX_SYS_CLK_RSTN_EN		BIT(3)
-#define DPTX_SYS_CLK_EN			BIT(2)
-#define CFG_DPTX_VIF_CLK_RSTN_EN	BIT(1)
-#define CFG_DPTX_VIF_CLK_EN		BIT(0)
-
-#define SOURCE_PHY_RSTN_EN		BIT(1)
-#define SOURCE_PHY_CLK_EN		BIT(0)
-
-#define SOURCE_PKT_SYS_RSTN_EN		BIT(3)
-#define SOURCE_PKT_SYS_CLK_EN		BIT(2)
-#define SOURCE_PKT_DATA_RSTN_EN		BIT(1)
-#define SOURCE_PKT_DATA_CLK_EN		BIT(0)
-
-#define SPDIF_CDR_CLK_RSTN_EN		BIT(5)
-#define SPDIF_CDR_CLK_EN		BIT(4)
-#define SOURCE_AIF_SYS_RSTN_EN		BIT(3)
-#define SOURCE_AIF_SYS_CLK_EN		BIT(2)
-#define SOURCE_AIF_CLK_RSTN_EN		BIT(1)
-#define SOURCE_AIF_CLK_EN		BIT(0)
-
-#define SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN	BIT(3)
-#define SOURCE_CIPHER_SYS_CLK_EN		BIT(2)
-#define SOURCE_CIPHER_CHAR_CLK_RSTN_EN		BIT(1)
-#define SOURCE_CIPHER_CHAR_CLK_EN		BIT(0)
-
-#define SOURCE_CRYPTO_SYS_CLK_RSTN_EN	BIT(1)
-#define SOURCE_CRYPTO_SYS_CLK_EN	BIT(0)
-
-#define APB_IRAM_PATH			BIT(2)
-#define APB_DRAM_PATH			BIT(1)
-#define APB_XT_RESET			BIT(0)
-
-#define MAILBOX_INT_MASK_BIT		BIT(1)
-#define PIF_INT_MASK_BIT		BIT(0)
-#define ALL_INT_MASK			3
-
-/* mailbox */
-#define MB_OPCODE_ID			0
-#define MB_MODULE_ID			1
-#define MB_SIZE_MSB_ID			2
-#define MB_SIZE_LSB_ID			3
-#define MB_DATA_ID			4
-
-#define MB_MODULE_ID_DP_TX		0x01
-#define MB_MODULE_ID_HDCP_TX		0x07
-#define MB_MODULE_ID_HDCP_RX		0x08
-#define MB_MODULE_ID_HDCP_GENERAL	0x09
-#define MB_MODULE_ID_GENERAL		0x0a
-
-/* general opcode */
-#define GENERAL_MAIN_CONTROL            0x01
-#define GENERAL_TEST_ECHO               0x02
-#define GENERAL_BUS_SETTINGS            0x03
-#define GENERAL_TEST_ACCESS             0x04
-
-#define DPTX_SET_POWER_MNG			0x00
-#define DPTX_SET_HOST_CAPABILITIES		0x01
-#define DPTX_GET_EDID				0x02
-#define DPTX_READ_DPCD				0x03
-#define DPTX_WRITE_DPCD				0x04
-#define DPTX_ENABLE_EVENT			0x05
-#define DPTX_WRITE_REGISTER			0x06
-#define DPTX_READ_REGISTER			0x07
-#define DPTX_WRITE_FIELD			0x08
-#define DPTX_TRAINING_CONTROL			0x09
-#define DPTX_READ_EVENT				0x0a
-#define DPTX_READ_LINK_STAT			0x0b
-#define DPTX_SET_VIDEO				0x0c
-#define DPTX_SET_AUDIO				0x0d
-#define DPTX_GET_LAST_AUX_STAUS			0x0e
-#define DPTX_SET_LINK_BREAK_POINT		0x0f
-#define DPTX_FORCE_LANES			0x10
-#define DPTX_HPD_STATE				0x11
-
-#define FW_STANDBY				0
-#define FW_ACTIVE				1
-
-#define DPTX_EVENT_ENABLE_HPD			BIT(0)
-#define DPTX_EVENT_ENABLE_TRAINING		BIT(1)
-
-#define LINK_TRAINING_NOT_ACTIVE		0
-#define LINK_TRAINING_RUN			1
-#define LINK_TRAINING_RESTART			2
-
-#define CONTROL_VIDEO_IDLE			0
-#define CONTROL_VIDEO_VALID			1
-
-#define VIF_BYPASS_INTERLACE			BIT(13)
-#define INTERLACE_FMT_DET			BIT(12)
-#define INTERLACE_DTCT_WIN			0x20
-
-#define DP_FRAMER_SP_INTERLACE_EN		BIT(2)
-#define DP_FRAMER_SP_HSP			BIT(1)
-#define DP_FRAMER_SP_VSP			BIT(0)
-
-/* capability */
-#define AUX_HOST_INVERT				3
-#define	FAST_LT_SUPPORT				1
-#define FAST_LT_NOT_SUPPORT			0
-#define LANE_MAPPING_NORMAL			0x1b
-#define LANE_MAPPING_FLIPPED			0xe4
-#define ENHANCED				1
-
-#define	FULL_LT_STARTED				BIT(0)
-#define FASE_LT_STARTED				BIT(1)
-#define CLK_RECOVERY_FINISHED			BIT(2)
-#define EQ_PHASE_FINISHED			BIT(3)
-#define FASE_LT_START_FINISHED			BIT(4)
-#define CLK_RECOVERY_FAILED			BIT(5)
-#define EQ_PHASE_FAILED				BIT(6)
-#define FASE_LT_FAILED				BIT(7)
-
-#define DPTX_HPD_EVENT				BIT(0)
-#define DPTX_TRAINING_EVENT			BIT(1)
-#define HDCP_TX_STATUS_EVENT			BIT(4)
-#define HDCP2_TX_IS_KM_STORED_EVENT		BIT(5)
-#define HDCP2_TX_STORE_KM_EVENT			BIT(6)
-#define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT	BIT(7)
-
-#define TU_SIZE					30
-#define CDN_DP_MAX_LINK_RATE			DP_LINK_BW_5_4
-
-/* audio */
-#define AUDIO_PACK_EN				BIT(8)
-#define SAMPLING_FREQ(x)			(((x) & 0xf) << 16)
-#define ORIGINAL_SAMP_FREQ(x)			(((x) & 0xf) << 24)
-#define SYNC_WR_TO_CH_ZERO			BIT(1)
-#define I2S_DEC_START				BIT(1)
-#define AUDIO_SW_RST				BIT(0)
-#define SMPL2PKT_EN				BIT(1)
-#define MAX_NUM_CH(x)				(((x) & 0x1f) - 1)
-#define NUM_OF_I2S_PORTS(x)			((((x) / 2 - 1) & 0x3) << 5)
-#define AUDIO_TYPE_LPCM				(2 << 7)
-#define CFG_SUB_PCKT_NUM(x)			((((x) - 1) & 0x7) << 11)
-#define AUDIO_CH_NUM(x)				((((x) - 1) & 0x1f) << 2)
-#define TRANS_SMPL_WIDTH_16			0
-#define TRANS_SMPL_WIDTH_24			BIT(11)
-#define TRANS_SMPL_WIDTH_32			(2 << 11)
-#define I2S_DEC_PORT_EN(x)			(((x) & 0xf) << 17)
-#define SPDIF_ENABLE				BIT(21)
-#define SPDIF_AVG_SEL				BIT(20)
-#define SPDIF_JITTER_BYPASS			BIT(19)
-#define SPDIF_FIFO_MID_RANGE(x)			(((x) & 0xff) << 11)
-#define SPDIF_JITTER_THRSH(x)			(((x) & 0xff) << 3)
-#define SPDIF_JITTER_AVG_WIN(x)			((x) & 0x7)
-
-/* Refernce cycles when using lane clock as refernce */
-#define LANE_REF_CYC				0x8000
-
-enum voltage_swing_level {
-	VOLTAGE_LEVEL_0,
-	VOLTAGE_LEVEL_1,
-	VOLTAGE_LEVEL_2,
-	VOLTAGE_LEVEL_3,
-};
-
-enum pre_emphasis_level {
-	PRE_EMPHASIS_LEVEL_0,
-	PRE_EMPHASIS_LEVEL_1,
-	PRE_EMPHASIS_LEVEL_2,
-	PRE_EMPHASIS_LEVEL_3,
-};
-
-enum pattern_set {
-	PTS1		= BIT(0),
-	PTS2		= BIT(1),
-	PTS3		= BIT(2),
-	PTS4		= BIT(3),
-	DP_NONE		= BIT(4)
-};
-
-enum vic_color_depth {
-	BCS_6 = 0x1,
-	BCS_8 = 0x2,
-	BCS_10 = 0x4,
-	BCS_12 = 0x8,
-	BCS_16 = 0x10,
-};
-
-enum vic_bt_type {
-	BT_601 = 0x0,
-	BT_709 = 0x1,
-};
-
-enum audio_format {
-	AFMT_I2S = 0,
-	AFMT_SPDIF = 1,
-	AFMT_UNUSED,
-};
-
-struct audio_info {
-	enum audio_format format;
-	int sample_rate;
-	int channels;
-	int sample_width;
-};
-
-enum vic_pxl_encoding_format {
-	PXL_RGB = 0x1,
-	YCBCR_4_4_4 = 0x2,
-	YCBCR_4_2_2 = 0x4,
-	YCBCR_4_2_0 = 0x8,
-	Y_ONLY = 0x10,
-};
-
-struct video_info {
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
-	int color_depth;
-	enum vic_pxl_encoding_format color_fmt;
-};
-
-struct cdn_firmware_header {
-	u32 size_bytes; /* size of the entire header+image(s) in bytes */
-	u32 header_size; /* size of just the header in bytes */
-	u32 iram_size; /* size of iram */
-	u32 dram_size; /* size of dram */
-};
-
-struct cdn_dp_port {
-	struct cdn_dp_device *dp;
-	struct notifier_block event_nb;
-	struct delayed_work event_wq;
-	struct extcon_dev *extcon;
-	struct phy *phy;
-	u8 cap_lanes;
-	bool phy_status;
-	u8 id;
-};
-
-struct cdn_dp_device {
-	struct device *dev;
-	struct drm_device *drm_dev;
-	struct drm_connector connector;
-	struct drm_encoder encoder;
-	struct drm_display_mode mode;
-	struct platform_device *audio_pdev;
-
-	const struct firmware *fw;	/* cdn dp firmware */
-	unsigned int fw_version;	/* cdn fw version */
-	u32 fw_wait;
-	bool fw_loaded;
-	bool fw_actived;
-	bool fw_clk_enabled;
-	void __iomem *regs;
-	struct regmap *grf;
-	struct clk *grf_clk;
-	struct clk *core_clk;
-	struct clk *pclk;
-	struct clk *spdif_clk;
-	struct reset_control *spdif_rst;
-	struct reset_control *dptx_rst;
-	struct reset_control *apb_rst;
-	struct reset_control *core_rst;
-	struct audio_info audio_info;
-	struct video_info video_info;
-	struct drm_dp_link link;
-	struct cdn_dp_port *port[MAX_PHY];
-	u8 ports;
-
-	u8 dpcd[DP_RECEIVER_CAP_SIZE];
-	enum drm_connector_status hpd_status;
-	int dpms_mode;
-	bool suspend;
-	bool sink_has_audio;
-
-	struct mutex lock;
-	struct wake_lock	wake_lock;
-};
-
-void cdn_dp_fb_clock_reset(struct cdn_dp_device *dp);
-
-void cdn_dp_fb_set_fw_clk(struct cdn_dp_device *dp, u32 clk);
-int cdn_dp_fb_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem,
-			 u32 i_size, const u32 *d_mem, u32 d_size);
-int cdn_dp_fb_set_firmware_active(struct cdn_dp_device *dp, bool enable);
-int cdn_dp_fb_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip);
-int cdn_dp_fb_event_config(struct cdn_dp_device *dp);
-u32 cdn_dp_fb_get_event(struct cdn_dp_device *dp);
-int cdn_dp_fb_get_hpd_status(struct cdn_dp_device *dp);
-int cdn_dp_fb_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value);
-int cdn_dp_fb_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len);
-int cdn_dp_fb_get_edid_block(void *dp, u8 *edid,
-			  unsigned int block, size_t length);
-int cdn_dp_fb_training_start(struct cdn_dp_device *dp);
-int cdn_dp_fb_get_training_status(struct cdn_dp_device *dp);
-int cdn_dp_fb_set_video_status(struct cdn_dp_device *dp, int active);
-int cdn_dp_fb_config_video(struct cdn_dp_device *dp);
-int cdn_dp_fb_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);
-int cdn_dp_fb_audio_mute(struct cdn_dp_device *dp, bool enable);
-int cdn_dp_fb_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);
-#endif /* _CDN_DP_REG_H */
diff --git a/drivers/video/rockchip/dp/rockchip_dp.c b/drivers/video/rockchip/dp/rockchip_dp.c
deleted file mode 100644
index 4dc803d7988c..000000000000
--- a/drivers/video/rockchip/dp/rockchip_dp.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include "rockchip_dp.h"
-#include <linux/delay.h>
-#include <linux/of_gpio.h>
-
-static int rockchip_dp_removed(struct hdmi *hdmi_drv)
-{
-	struct dp_dev *dp_dev = hdmi_drv->property->priv;
-	int ret;
-
-	ret = cdn_dp_encoder_disable(dp_dev->dp);
-	if (ret)
-		dev_warn(hdmi_drv->dev, "dp has been removed twice:%d\n", ret);
-	return HDMI_ERROR_SUCCESS;
-}
-
-static int rockchip_dp_enable(struct hdmi *hdmi_drv)
-{
-	return 0;
-}
-
-static int rockchip_dp_disable(struct hdmi *hdmi_drv)
-{
-	return 0;
-}
-
-static int rockchip_dp_control_output(struct hdmi *hdmi_drv, int enable)
-{
-	struct dp_dev *dp_dev = hdmi_drv->property->priv;
-	int ret;
-
-	if (enable == HDMI_AV_UNMUTE) {
-		if (!dp_dev->early_suspended) {
-			ret = cdn_dp_encoder_enable(dp_dev->dp);
-			if (ret) {
-				dev_err(hdmi_drv->dev,
-					"dp enable video and audio output error:%d\n", ret);
-				return HDMI_ERROR_FALSE;
-			}
-		} else
-			dev_warn(hdmi_drv->dev,
-				"don't output video and audio after dp has been suspended!\n");
-	} else if (enable & HDMI_VIDEO_MUTE)
-		dev_dbg(hdmi_drv->dev, "dp disable video and audio output !\n");
-
-	return 0;
-}
-
-static int rockchip_dp_config_audio(struct hdmi *hdmi_drv,
-				    struct hdmi_audio *audio)
-{
-	return 0;
-}
-
-static int rockchip_dp_config_video(struct hdmi *hdmi_drv,
-				    struct hdmi_video *vpara)
-{
-	struct hdmi_video_timing *timing = NULL;
-	struct dp_dev *dp_dev = hdmi_drv->property->priv;
-	struct dp_disp_info *disp_info = &dp_dev->disp_info;
-	int ret;
-
-	if (dp_dev->early_suspended) {
-		dev_warn(hdmi_drv->dev,
-			"don't config video after dp has been suspended!\n");
-		return 0;
-	}
-
-	timing = (struct hdmi_video_timing *)hdmi_vic2timing(vpara->vic);
-	if (!timing) {
-		dev_err(hdmi_drv->dev,
-			"[%s] not found vic %d\n", __func__, vpara->vic);
-		return -ENOENT;
-	}
-	disp_info->mode = &timing->mode;
-
-	disp_info->color_depth = vpara->color_output_depth;
-	disp_info->vsync_polarity = 1;
-	disp_info->hsync_polarity = 1;
-
-	ret = cdn_dp_encoder_mode_set(dp_dev->dp, disp_info);
-	if (ret) {
-		dev_err(hdmi_drv->dev, "dp config video mode error:%d\n", ret);
-		return HDMI_ERROR_FALSE;
-	}
-
-	return 0;
-}
-
-static int rockchip_dp_detect_hotplug(struct hdmi *hdmi_drv)
-{
-	struct dp_dev *dp_dev = hdmi_drv->property->priv;
-
-	if (cdn_dp_connector_detect(dp_dev->dp))
-		return HDMI_HPD_ACTIVATED;
-	return HDMI_HPD_REMOVED;
-}
-
-static int rockchip_dp_read_edid(struct hdmi *hdmi_drv, int block, u8 *buf)
-{
-	int ret = 0;
-	struct dp_dev *dp_dev = hdmi_drv->property->priv;
-
-	if (dp_dev->lanes == 4)
-		dp_dev->hdmi->property->feature |= SUPPORT_TMDS_600M;
-	else
-		dp_dev->hdmi->property->feature &= ~SUPPORT_TMDS_600M;
-
-	ret = cdn_dp_get_edid(dp_dev->dp, buf, block);
-	if (ret)
-		dev_err(hdmi_drv->dev, "dp config video mode error:%d\n", ret);
-
-	return ret;
-}
-
-static int rockchip_dp_insert(struct hdmi *hdmi_drv)
-{
-	return 0;
-}
-
-static int rockchip_dp_config_vsi(struct hdmi *hdmi,
-				  unsigned char vic_3d,
-				  unsigned char format)
-{
-	return 0;
-}
-
-static void rockchip_dp_dev_init_ops(struct hdmi_ops *ops)
-{
-	if (ops) {
-		ops->disable = rockchip_dp_disable;
-		ops->enable = rockchip_dp_enable;
-		ops->remove = rockchip_dp_removed;
-		ops->setmute = rockchip_dp_control_output;
-		ops->setvideo = rockchip_dp_config_video;
-		ops->setaudio = rockchip_dp_config_audio;
-		ops->getstatus = rockchip_dp_detect_hotplug;
-		ops->getedid = rockchip_dp_read_edid;
-		ops->insert     = rockchip_dp_insert;
-		ops->setvsi = rockchip_dp_config_vsi;
-	}
-}
-
-void hpd_change(struct device *dev, int lanes)
-{
-	struct dp_dev *dp_dev = dev_get_drvdata(dev);
-
-	if (lanes)
-		dp_dev->lanes = lanes;
-
-	if (dp_dev->hdmi->enable) {
-		if (dp_dev->early_suspended)
-			dev_warn(dp_dev->hdmi->dev,
-				"hpd triggered after early suspend, so don't send hpd change event !\n");
-		else
-			hdmi_submit_work(dp_dev->hdmi, HDMI_HPD_CHANGE, 10, 0);
-	}
-}
-
-static void rockchip_dp_early_suspend(struct dp_dev *dp_dev)
-{
-	hdmi_submit_work(dp_dev->hdmi, HDMI_SUSPEND_CTL, 0, 1);
-	cdn_dp_fb_suspend(dp_dev->dp);
-}
-
-static void rockchip_dp_early_resume(struct dp_dev *dp_dev)
-{
-	cdn_dp_fb_resume(dp_dev->dp);
-	hdmi_submit_work(dp_dev->hdmi, HDMI_RESUME_CTL, 0, 0);
-}
-
-static int rockchip_dp_fb_event_notify(struct notifier_block *self,
-				       unsigned long action,
-					   void *data)
-{
-	struct fb_event *event = data;
-	struct dp_dev *dp_dev = container_of(self, struct dp_dev, fb_notif);
-
-	if (action == FB_EARLY_EVENT_BLANK) {
-		switch (*((int *)event->data)) {
-		case FB_BLANK_UNBLANK:
-			break;
-		default:
-			if (!dp_dev->hdmi->sleep) {
-				rockchip_dp_early_suspend(dp_dev);
-				dp_dev->early_suspended = true;
-			}
-			break;
-		}
-	} else if (action == FB_EVENT_BLANK) {
-		switch (*((int *)event->data)) {
-		case FB_BLANK_UNBLANK:
-			if (dp_dev->hdmi->sleep) {
-				dp_dev->early_suspended = false;
-				rockchip_dp_early_resume(dp_dev);
-			}
-			break;
-		default:
-			break;
-		}
-	}
-
-	return NOTIFY_OK;
-}
-
-static int cdn_dp_get_prop_dts(struct hdmi *hdmi, struct device_node *np)
-{
-	const struct property *prop;
-	int i = 0, nstates = 0;
-	const __be32 *val;
-	int value;
-	struct edid_prop_value *pval = NULL;
-
-	if (!hdmi || !np)
-		return -EINVAL;
-
-	if (!of_property_read_u32(np, "dp_edid_auto_support", &value))
-		hdmi->edid_auto_support = value;
-
-	prop = of_find_property(np, "dp_edid_prop_value", NULL);
-	if (!prop || !prop->value) {
-		pr_info("%s:No edid-prop-value, %d\n", __func__, !prop);
-		return -EINVAL;
-	}
-
-	nstates = (prop->length / sizeof(struct edid_prop_value));
-	pval = kcalloc(nstates, sizeof(struct edid_prop_value), GFP_NOWAIT);
-	if (!pval)
-		return -ENOMEM;
-
-	for (i = 0, val = prop->value; i < nstates; i++) {
-		pval[i].vid = be32_to_cpup(val++);
-		pval[i].pid = be32_to_cpup(val++);
-		pval[i].sn = be32_to_cpup(val++);
-		pval[i].xres = be32_to_cpup(val++);
-		pval[i].yres = be32_to_cpup(val++);
-		pval[i].vic = be32_to_cpup(val++);
-		pval[i].width = be32_to_cpup(val++);
-		pval[i].height = be32_to_cpup(val++);
-		pval[i].x_w = be32_to_cpup(val++);
-		pval[i].x_h = be32_to_cpup(val++);
-		pval[i].hwrotation = be32_to_cpup(val++);
-		pval[i].einit = be32_to_cpup(val++);
-		pval[i].vsync = be32_to_cpup(val++);
-		pval[i].panel = be32_to_cpup(val++);
-		pval[i].scan = be32_to_cpup(val++);
-
-		pr_info("%s: 0x%x 0x%x 0x%x %d %d %d %d %d %d %d %d %d %d %d %d\n",
-			__func__, pval[i].vid, pval[i].pid, pval[i].sn,
-			pval[i].width, pval[i].height, pval[i].xres,
-			pval[i].yres, pval[i].vic, pval[i].x_w,
-			pval[i].x_h, pval[i].hwrotation, pval[i].einit,
-			pval[i].vsync, pval[i].panel, pval[i].scan);
-	}
-
-	hdmi->pvalue = pval;
-	hdmi->nstates = nstates;
-
-	return 0;
-}
-
-int cdn_dp_fb_register(struct platform_device *pdev, void *dp)
-{
-	struct hdmi_ops *rk_dp_ops;
-	struct hdmi_property *rk_cdn_dp_prop;
-	struct device *dev = &pdev->dev;
-	struct dp_dev *dp_dev;
-	struct device_node *np = dev->of_node;
-	int val = 0;
-
-	rk_dp_ops = devm_kzalloc(dev, sizeof(struct hdmi_ops), GFP_KERNEL);
-	if (!rk_dp_ops)
-		return -ENOMEM;
-
-	rk_cdn_dp_prop = devm_kzalloc(dev, sizeof(struct hdmi_property),
-				      GFP_KERNEL);
-	if (!rk_cdn_dp_prop)
-		return -ENOMEM;
-
-	dp_dev = devm_kzalloc(dev, sizeof(struct dp_dev), GFP_KERNEL);
-	if (!dp_dev)
-		return -ENOMEM;
-
-	if (!of_property_read_u32(np, "dp_vop_sel", &val))
-		dp_dev->disp_info.vop_sel = val;
-
-	rockchip_dp_dev_init_ops(rk_dp_ops);
-	rk_cdn_dp_prop->videosrc = dp_dev->disp_info.vop_sel;
-	rk_cdn_dp_prop->display = DISPLAY_MAIN;
-	if (!of_property_read_u32(np, "dp_defaultmode", &val))
-		rk_cdn_dp_prop->defaultmode = val;
-	else
-		rk_cdn_dp_prop->defaultmode = HDMI_VIDEO_DEFAULT_MODE;
-	rk_cdn_dp_prop->name = (char *)pdev->name;
-	rk_cdn_dp_prop->priv = dp_dev;
-	rk_cdn_dp_prop->feature |=
-				SUPPORT_DEEP_10BIT |
-				SUPPORT_YCBCR_INPUT |
-				SUPPORT_1080I |
-				SUPPORT_480I_576I |
-				SUPPORT_RK_DISCRETE_VR;
-
-	if (!rk_cdn_dp_prop->videosrc) {
-		rk_cdn_dp_prop->feature |=
-					SUPPORT_4K |
-					SUPPORT_4K_4096 |
-					SUPPORT_YUV420 |
-					SUPPORT_YCBCR_INPUT |
-					SUPPORT_TMDS_600M;
-	}
-
-	dp_dev->hdmi = rockchip_hdmi_register(rk_cdn_dp_prop,
-						rk_dp_ops);
-	dp_dev->hdmi->dev = dev;
-	dp_dev->hdmi->enable = 1;
-	dp_dev->early_suspended = 0;
-	dp_dev->hdmi->sleep = 0;
-	dp_dev->hdmi->colormode = HDMI_COLOR_RGB_0_255;
-	dp_dev->dp = dp;
-
-	cdn_dp_get_prop_dts(dp_dev->hdmi, np);
-	dp_dev->fb_notif.notifier_call = rockchip_dp_fb_event_notify;
-	fb_register_client(&dp_dev->fb_notif);
-	dev_set_drvdata(dev, dp_dev);
-
-	hdmi_submit_work(dp_dev->hdmi, HDMI_HPD_CHANGE, 20, 0);
-	return 0;
-}
diff --git a/drivers/video/rockchip/dp/rockchip_dp.h b/drivers/video/rockchip/dp/rockchip_dp.h
deleted file mode 100644
index d098e7a1a072..000000000000
--- a/drivers/video/rockchip/dp/rockchip_dp.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ROCKCHIP_DP_H__
-#define __ROCKCHIP_DP_H__
-
-#include "../hdmi/rockchip-hdmi.h"
-#include "rockchip_dp_core.h"
-
-int cdn_dp_get_edid(void *dp, u8 *edid, unsigned int block);
-int cdn_dp_encoder_mode_set(void *dp, struct dp_disp_info *disp_info);
-int cdn_dp_encoder_enable(void *dp);
-int cdn_dp_connector_detect(void *dp);
-int cdn_dp_encoder_disable(void *dp);
-int cdn_dp_audio_hw_params(void *dp);
-int cdn_dp_audio_digital_mute(void *dp, bool enable);
-int cdn_dp_fb_resume(void *dp_dev);
-int cdn_dp_fb_suspend(void *dp_dev);
-
-#endif
diff --git a/drivers/video/rockchip/dp/rockchip_dp_core.c b/drivers/video/rockchip/dp/rockchip_dp_core.c
deleted file mode 100644
index dad42f26bafb..000000000000
--- a/drivers/video/rockchip/dp/rockchip_dp_core.c
+++ /dev/null
@@ -1,950 +0,0 @@
-/*
- * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
- * Author: Chris Zhong <zyw@rock-chips.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/clk.h>
-#include <linux/component.h>
-#include <linux/extcon.h>
-#include <linux/firmware.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-#include <linux/mfd/syscon.h>
-#include <linux/phy/phy.h>
-#include <sound/hdmi-codec.h>
-#include <video/of_videomode.h>
-#include <video/videomode.h>
-
-#include <linux/fb.h>
-#include <linux/platform_device.h>
-#include "rockchip_dp_core.h"
-#include "cdn-dp-fb-reg.h"
-
-static struct cdn_dp_data rk3399_cdn_dp = {
-	.max_phy = 2,
-};
-
-static const struct of_device_id cdn_dp_dt_ids[] = {
-	{ .compatible = "rockchip,rk3399-cdn-dp-fb",
-		.data = (void *)&rk3399_cdn_dp },
-	{}
-};
-
-MODULE_DEVICE_TABLE(of, cdn_dp_dt_ids);
-
-static int cdn_dp_grf_write(struct cdn_dp_device *dp,
-			    unsigned int reg, unsigned int val)
-{
-	int ret;
-
-	ret = clk_prepare_enable(dp->grf_clk);
-	if (ret) {
-		dev_err(dp->dev, "Failed to prepare_enable grf clock\n");
-		return ret;
-	}
-
-	ret = regmap_write(dp->grf, reg, val);
-	if (ret) {
-		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
-		return ret;
-	}
-
-	clk_disable_unprepare(dp->grf_clk);
-
-	return 0;
-}
-
-static int cdn_dp_set_fw_rate(struct cdn_dp_device *dp)
-{
-	u32 rate;
-
-	if (!dp->fw_clk_enabled) {
-		rate = clk_get_rate(dp->core_clk);
-		if (rate == 0) {
-			dev_err(dp->dev, "get clk rate failed: %d\n", rate);
-			return rate;
-		}
-		cdn_dp_fb_set_fw_clk(dp, rate);
-		cdn_dp_fb_clock_reset(dp);
-		dp->fw_clk_enabled = true;
-	}
-
-	return 0;
-}
-
-static int cdn_dp_clk_enable(struct cdn_dp_device *dp)
-{
-	int ret;
-
-	ret = clk_prepare_enable(dp->pclk);
-	if (ret < 0) {
-		dev_err(dp->dev, "cannot enable dp pclk %d\n", ret);
-		goto runtime_get_pm;
-	}
-
-	ret = clk_prepare_enable(dp->core_clk);
-	if (ret < 0) {
-		dev_err(dp->dev, "cannot enable core_clk %d\n", ret);
-		goto err_core_clk;
-	}
-
-	ret = pm_runtime_get_sync(dp->dev);
-	if (ret < 0) {
-		dev_err(dp->dev, "cannot get pm runtime %d\n", ret);
-		return ret;
-	}
-
-	reset_control_assert(dp->apb_rst);
-	reset_control_assert(dp->core_rst);
-	reset_control_assert(dp->dptx_rst);
-	udelay(1);
-	reset_control_deassert(dp->dptx_rst);
-	reset_control_deassert(dp->core_rst);
-	reset_control_deassert(dp->apb_rst);
-
-	ret = cdn_dp_set_fw_rate(dp);
-	if (ret < 0) {
-		dev_err(dp->dev, "cannot get set fw rate %d\n", ret);
-		goto err_set_rate;
-	}
-
-	return 0;
-
-err_set_rate:
-	clk_disable_unprepare(dp->core_clk);
-err_core_clk:
-	clk_disable_unprepare(dp->pclk);
-runtime_get_pm:
-	pm_runtime_put_sync(dp->dev);
-	return ret;
-}
-
-static void cdn_dp_clk_disable(struct cdn_dp_device *dp)
-{
-	pm_runtime_put_sync(dp->dev);
-	clk_disable_unprepare(dp->pclk);
-	clk_disable_unprepare(dp->core_clk);
-}
-
-int cdn_dp_get_edid(void *dp, u8 *buf, int block)
-{
-	int ret;
-	struct cdn_dp_device *dp_dev = dp;
-
-	mutex_lock(&dp_dev->lock);
-	ret = cdn_dp_fb_get_edid_block(dp_dev, buf, block, EDID_BLOCK_SIZE);
-	mutex_unlock(&dp_dev->lock);
-
-	return ret;
-}
-
-int cdn_dp_connector_detect(void *dp)
-{
-	struct cdn_dp_device *dp_dev = dp;
-	bool ret = false;
-
-	mutex_lock(&dp_dev->lock);
-	if (dp_dev->hpd_status == connector_status_connected)
-		ret = true;
-	mutex_unlock(&dp_dev->lock);
-
-	return ret;
-}
-
-int cdn_dp_encoder_disable(void *dp)
-{
-	struct cdn_dp_device *dp_dev = dp;
-	int ret = 0;
-
-	mutex_lock(&dp_dev->lock);
-	memset(&dp_dev->mode, 0, sizeof(dp_dev->mode));
-	if (dp_dev->hpd_status == connector_status_disconnected) {
-		dp_dev->dpms_mode = DRM_MODE_DPMS_OFF;
-		mutex_unlock(&dp_dev->lock);
-		return ret;
-	}
-
-	if (dp_dev->dpms_mode == DRM_MODE_DPMS_ON) {
-		dp_dev->dpms_mode = DRM_MODE_DPMS_OFF;
-	} else{
-		dev_warn(dp_dev->dev, "wrong dpms status,dp encoder has already been disabled\n");
-		ret = -1;
-	}
-	mutex_unlock(&dp_dev->lock);
-
-	return ret;
-}
-
-static void cdn_dp_commit(struct cdn_dp_device *dp)
-{
-	char guid[16];
-	int ret = cdn_dp_fb_training_start(dp);
-
-	if (ret) {
-		dev_err(dp->dev, "link training failed: %d\n", ret);
-		return;
-	}
-
-	ret = cdn_dp_fb_get_training_status(dp);
-	if (ret) {
-		dev_err(dp->dev, "get link training status failed: %d\n", ret);
-		return;
-	}
-
-	dev_info(dp->dev, "rate:%d, lanes:%d\n",
-			dp->link.rate, dp->link.num_lanes);
-
-	/**
-	* Use dpcd@0x0030~0x003f(which is GUID registers) to sync with NanoC
-	* to make sure training is ok. Nanoc will write "nanoc" in GUID registers
-	* when booting, and then we will use these registers to decide whether
-	* need to sync with device which plugged in.
-	* The sync register is 0x0035, firstly we write 0xaa to sync register,
-	* nanoc will read this register and then start the part2 code of DP.
-	*/
-	ret = cdn_dp_fb_dpcd_read(dp, 0x0030, guid, 8);
-	if (ret == 0 && guid[0] == 'n' && guid[1] == 'a' && guid[2] == 'n' &&
-			guid[3] == 'o' && guid[4] == 'c') {
-		u8 sync_number = 0xaa;
-
-		cdn_dp_fb_dpcd_write(dp, 0x0035, sync_number);
-	}
-
-	if (cdn_dp_fb_set_video_status(dp, CONTROL_VIDEO_IDLE))
-		return;
-
-	if (cdn_dp_fb_config_video(dp)) {
-		dev_err(dp->dev, "unable to config video\n");
-		return;
-	}
-
-	if (cdn_dp_fb_set_video_status(dp, CONTROL_VIDEO_VALID))
-		return;
-
-	dp->dpms_mode = DRM_MODE_DPMS_ON;
-}
-
-int cdn_dp_encoder_mode_set(void *dp, struct dp_disp_info *disp_info)
-{
-	int ret, val;
-	struct cdn_dp_device *dp_dev = dp;
-	struct video_info *video = &dp_dev->video_info;
-	struct drm_display_mode disp_mode;
-	struct fb_videomode *mode = disp_info->mode;
-
-	mutex_lock(&dp_dev->lock);
-	disp_mode.clock = mode->pixclock / 1000;
-	disp_mode.hdisplay = mode->xres;
-	disp_mode.hsync_start = disp_mode.hdisplay + mode->right_margin;
-	disp_mode.hsync_end = disp_mode.hsync_start + mode->hsync_len;
-	disp_mode.htotal = disp_mode.hsync_end + mode->left_margin;
-	disp_mode.vdisplay = mode->yres;
-	disp_mode.vsync_start = disp_mode.vdisplay + mode->lower_margin;
-	disp_mode.vsync_end = disp_mode.vsync_start + mode->vsync_len;
-	disp_mode.vtotal = disp_mode.vsync_end + mode->upper_margin;
-
-	switch (disp_info->color_depth) {
-	case 16:
-	case 12:
-	case 10:
-		video->color_depth = 10;
-		break;
-	case 6:
-		video->color_depth = 6;
-		break;
-	default:
-		video->color_depth = 8;
-		break;
-	}
-
-	video->color_fmt = PXL_RGB;
-
-	video->v_sync_polarity = disp_info->vsync_polarity;
-	video->h_sync_polarity = disp_info->hsync_polarity;
-
-	if (disp_info->vop_sel)
-		val = DP_SEL_VOP_LIT | (DP_SEL_VOP_LIT << 16);
-	else
-		val = DP_SEL_VOP_LIT << 16;
-
-	ret = cdn_dp_grf_write(dp, GRF_SOC_CON9, val);
-	if (ret != 0) {
-		dev_err(dp_dev->dev, "Could not write to GRF: %d\n", ret);
-		mutex_unlock(&dp_dev->lock);
-		return ret;
-	}
-	memcpy(&dp_dev->mode, &disp_mode, sizeof(disp_mode));
-
-	mutex_unlock(&dp_dev->lock);
-
-	return 0;
-}
-
-int cdn_dp_encoder_enable(void *dp)
-{
-	struct cdn_dp_device *dp_dev = dp;
-	int ret = 0;
-
-	mutex_lock(&dp_dev->lock);
-
-	if (dp_dev->dpms_mode == DRM_MODE_DPMS_OFF) {
-		/**
-		* the mode info of dp device will be cleared when dp encoder is disabled
-		* so if clock value of mode is 0, means rockchip_dp_config_video is not
-		* return success, so we don't do cdn_dp_commit.
-		*/
-		if (dp_dev->mode.clock == 0) {
-			dev_err(dp_dev->dev, "Error !Please make sure function cdn_dp_encoder_mode_set return success!\n");
-			mutex_unlock(&dp_dev->lock);
-			return -1;
-		}
-		cdn_dp_commit(dp_dev);
-	} else {
-		dev_warn(dp_dev->dev, "wrong dpms status,dp encoder has already been enabled\n");
-		ret = -1;
-	}
-	mutex_unlock(&dp_dev->lock);
-
-	return ret;
-}
-
-static int cdn_dp_firmware_init(struct cdn_dp_device *dp)
-{
-	int ret;
-	const u32 *iram_data, *dram_data;
-	const struct firmware *fw = dp->fw;
-	const struct cdn_firmware_header *hdr;
-
-	hdr = (struct cdn_firmware_header *)fw->data;
-	if (fw->size != le32_to_cpu(hdr->size_bytes)) {
-		dev_err(dp->dev, "firmware is invalid\n");
-		return -EINVAL;
-	}
-
-	iram_data = (const u32 *)(fw->data + hdr->header_size);
-	dram_data = (const u32 *)(fw->data + hdr->header_size + hdr->iram_size);
-
-	ret = cdn_dp_fb_load_firmware(dp, iram_data, hdr->iram_size,
-				   dram_data, hdr->dram_size);
-	if (ret)
-		return ret;
-
-	ret = cdn_dp_fb_set_firmware_active(dp, true);
-	if (ret) {
-		dev_err(dp->dev, "active ucpu failed: %d\n", ret);
-		return ret;
-	}
-
-	dp->fw_loaded = 1;
-	return cdn_dp_fb_event_config(dp);
-}
-
-static int cdn_dp_init(struct cdn_dp_device *dp)
-{
-	struct device *dev = dp->dev;
-	struct device_node *np = dev->of_node;
-	struct platform_device *pdev = to_platform_device(dev);
-	struct resource *res;
-
-	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
-	if (IS_ERR(dp->grf)) {
-		dev_err(dev, "cdn-dp needs rockchip,grf property\n");
-		return PTR_ERR(dp->grf);
-	}
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	dp->regs = devm_ioremap_resource(dev, res);
-	if (IS_ERR(dp->regs)) {
-		dev_err(dev, "ioremap reg failed\n");
-		return PTR_ERR(dp->regs);
-	}
-
-	dp->core_clk = devm_clk_get(dev, "core-clk");
-	if (IS_ERR(dp->core_clk)) {
-		dev_err(dev, "cannot get core_clk_dp\n");
-		return PTR_ERR(dp->core_clk);
-	}
-
-	dp->pclk = devm_clk_get(dev, "pclk");
-	if (IS_ERR(dp->pclk)) {
-		dev_err(dev, "cannot get pclk\n");
-		return PTR_ERR(dp->pclk);
-	}
-
-	dp->spdif_clk = devm_clk_get(dev, "spdif");
-	if (IS_ERR(dp->spdif_clk)) {
-		dev_err(dev, "cannot get spdif_clk\n");
-		return PTR_ERR(dp->spdif_clk);
-	}
-
-	dp->grf_clk = devm_clk_get(dev, "grf");
-	if (IS_ERR(dp->grf_clk)) {
-		dev_err(dev, "cannot get grf clk\n");
-		return PTR_ERR(dp->grf_clk);
-	}
-
-	dp->spdif_rst = devm_reset_control_get(dev, "spdif");
-	if (IS_ERR(dp->spdif_rst)) {
-		dev_err(dev, "no spdif reset control found\n");
-		return PTR_ERR(dp->spdif_rst);
-	}
-
-	dp->dptx_rst = devm_reset_control_get(dev, "dptx");
-	if (IS_ERR(dp->dptx_rst)) {
-		dev_err(dev, "no uphy reset control found\n");
-		return PTR_ERR(dp->dptx_rst);
-	}
-
-	dp->apb_rst = devm_reset_control_get(dev, "apb");
-	if (IS_ERR(dp->apb_rst)) {
-		dev_err(dev, "no apb reset control found\n");
-		return PTR_ERR(dp->apb_rst);
-	}
-
-	dp->core_rst = devm_reset_control_get(dev, "core");
-	if (IS_ERR(dp->core_rst)) {
-		DRM_DEV_ERROR(dev, "no core reset control found\n");
-		return PTR_ERR(dp->core_rst);
-	}
-
-	dp->dpms_mode = DRM_MODE_DPMS_OFF;
-	dp->fw_clk_enabled = false;
-
-	pm_runtime_enable(dev);
-
-	mutex_init(&dp->lock);
-	wake_lock_init(&dp->wake_lock, WAKE_LOCK_SUSPEND, "cdn_dp_fb");
-	return 0;
-}
-
-struct cdn_dp_device *g_dp;
-static int cdn_dp_audio_hw_params(struct device *dev,  void *data,
-				  struct hdmi_codec_daifmt *daifmt,
-				  struct hdmi_codec_params *params)
-{
-	struct dp_dev *dp_dev = dev_get_drvdata(dev);
-	struct cdn_dp_device *dp = dp_dev->dp;
-	int ret;
-	struct audio_info audio = {
-		.sample_width = 16,
-		.sample_rate = 44100,
-		.channels = 8,
-	};
-
-	if (!cdn_dp_connector_detect(dp))
-		return 0;
-
-	switch (HDMI_I2S) {
-	case HDMI_I2S:
-		audio.format = AFMT_I2S;
-		break;
-	case HDMI_SPDIF:
-		audio.format = AFMT_SPDIF;
-		break;
-	default:
-		dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
-		return -EINVAL;
-	}
-
-	ret = cdn_dp_fb_audio_config(dp, &audio);
-	if (!ret)
-		dp->audio_info = audio;
-
-	return ret;
-}
-
-static void cdn_dp_audio_shutdown(struct device *dev, void *data)
-{
-	struct dp_dev *dp_dev = dev_get_drvdata(dev);
-	struct cdn_dp_device *dp = dp_dev->dp;
-	int ret;
-
-	if (cdn_dp_connector_detect(dp)) {
-		ret = cdn_dp_fb_audio_stop(dp, &dp->audio_info);
-		if (!ret)
-			dp->audio_info.format = AFMT_UNUSED;
-	}
-}
-
-static int cdn_dp_audio_digital_mute(struct device *dev, void *data,
-				     bool enable)
-{
-	struct dp_dev *dp_dev = dev_get_drvdata(dev);
-	struct cdn_dp_device *dp = dp_dev->dp;
-
-	if (!cdn_dp_connector_detect(dp))
-		return 0;
-	return cdn_dp_fb_audio_mute(dp, enable);
-}
-
-static const struct hdmi_codec_ops audio_codec_ops = {
-	.hw_params = cdn_dp_audio_hw_params,
-	.audio_shutdown = cdn_dp_audio_shutdown,
-	.digital_mute = cdn_dp_audio_digital_mute,
-};
-
-static int cdn_dp_audio_codec_init(struct cdn_dp_device *dp,
-				   struct device *dev)
-{
-	struct hdmi_codec_pdata codec_data = {
-		.i2s = 1,
-		.spdif = 1,
-		.ops = &audio_codec_ops,
-		.max_i2s_channels = 8,
-	};
-
-	dp->audio_pdev = platform_device_register_data(
-			 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
-			 &codec_data, sizeof(codec_data));
-
-	return PTR_ERR_OR_ZERO(dp->audio_pdev);
-}
-
-static int cdn_dp_get_cap_lanes(struct cdn_dp_device *dp,
-				struct extcon_dev *edev)
-{
-	union extcon_property_value property;
-	u8 lanes = 0;
-	int dptx;
-
-	if (dp->suspend)
-		return 0;
-
-	dptx = extcon_get_state(edev, EXTCON_DISP_DP);
-	if (dptx > 0) {
-		extcon_get_property(edev, EXTCON_DISP_DP,
-				    EXTCON_PROP_USB_SS, &property);
-		if (property.intval)
-			lanes = 2;
-		else
-			lanes = 4;
-	}
-
-	return lanes;
-}
-
-static int cdn_dp_get_dpcd(struct cdn_dp_device *dp, struct cdn_dp_port *port)
-{
-	u8 sink_count;
-	int i, ret;
-	int retry = 60;
-
-	/*
-	 * Native read with retry for link status and receiver capability reads
-	 * for cases where the sink may still not be ready.
-	 *
-	 * Sinks are *supposed* to come up within 1ms from an off state, but
-	 * some DOCKs need about 5 seconds to power up, so read the dpcd every
-	 * 100ms, if can not get a good dpcd in 10 seconds, give up.
-	 */
-	for (i = 0; i < 100; i++) {
-		ret = cdn_dp_fb_dpcd_read(dp, DP_SINK_COUNT,
-				       &sink_count, 1);
-		if (!ret) {
-			dev_dbg(dp->dev, "get dpcd success!\n");
-
-			sink_count = DP_GET_SINK_COUNT(sink_count);
-			if (!sink_count) {
-				if (retry-- <= 0) {
-					dev_err(dp->dev, "sink cout is 0, no sink device!\n");
-					return -ENODEV;
-				}
-				msleep(50);
-				continue;
-			}
-
-			ret = cdn_dp_fb_dpcd_read(dp, 0x000, dp->dpcd,
-					       DP_RECEIVER_CAP_SIZE);
-			if (ret)
-				continue;
-
-			return ret;
-		} else if (!extcon_get_state(port->extcon, EXTCON_DISP_DP)) {
-			break;
-		}
-
-		msleep(100);
-	}
-
-	dev_err(dp->dev, "get dpcd failed!\n");
-
-	return -ETIMEDOUT;
-}
-
-static void cdn_dp_enter_standy(struct cdn_dp_device *dp,
-				struct cdn_dp_port *port)
-{
-	int i, ret;
-
-	if (port->phy_status) {
-		ret = phy_power_off(port->phy);
-		if (ret) {
-			dev_err(dp->dev, "phy power off failed: %d", ret);
-			return;
-		}
-	}
-
-	port->phy_status = false;
-	port->cap_lanes = 0;
-	for (i = 0; i < dp->ports; i++)
-		if (dp->port[i]->phy_status)
-			return;
-
-	memset(dp->dpcd, 0, DP_RECEIVER_CAP_SIZE);
-	if (dp->fw_actived)
-		cdn_dp_fb_set_firmware_active(dp, false);
-	if (dp->fw_clk_enabled) {
-		cdn_dp_clk_disable(dp);
-		dp->fw_clk_enabled = false;
-	}
-	dp->hpd_status = connector_status_disconnected;
-
-	hpd_change(dp->dev, 0);
-}
-
-static int cdn_dp_start_work(struct cdn_dp_device *dp,
-			     struct cdn_dp_port *port,
-			     u8 cap_lanes)
-{
-	union extcon_property_value property;
-	int ret;
-
-	if (!dp->fw_loaded) {
-		ret = request_firmware(&dp->fw, CDN_DP_FIRMWARE, dp->dev);
-		if (ret) {
-			if (ret == -ENOENT && dp->fw_wait <= MAX_FW_WAIT_SECS) {
-				unsigned long time = msecs_to_jiffies(dp->fw_wait * HZ);
-
-				/*
-				 * Keep trying to load the firmware for up to 1 minute,
-				 * if can not find the file.
-				 */
-				schedule_delayed_work(&port->event_wq, time);
-				dp->fw_wait *= 2;
-			} else {
-				dev_err(dp->dev, "failed to request firmware: %d\n",
-					ret);
-			}
-
-			return ret;
-		} else
-			dp->fw_loaded = true;
-	}
-
-	ret = cdn_dp_clk_enable(dp);
-	if (ret < 0) {
-		dev_err(dp->dev, "failed to enable clock for dp: %d\n", ret);
-		return ret;
-	}
-
-	ret = phy_power_on(port->phy);
-	if (ret) {
-		dev_err(dp->dev, "phy power on failed: %d\n", ret);
-		goto err_phy;
-	}
-
-	port->phy_status = true;
-
-	ret = cdn_dp_firmware_init(dp);
-	if (ret) {
-		dev_err(dp->dev, "firmware init failed: %d", ret);
-		goto err_firmware;
-	}
-
-	ret = cdn_dp_grf_write(dp, GRF_SOC_CON26,
-			       DPTX_HPD_SEL_MASK | DPTX_HPD_SEL);
-	if (ret)
-		goto err_grf;
-
-	ret = cdn_dp_fb_get_hpd_status(dp);
-	if (ret <= 0) {
-		if (!ret)
-			dev_err(dp->dev, "hpd does not exist\n");
-		goto err_hpd;
-	}
-
-	ret = extcon_get_property(port->extcon, EXTCON_DISP_DP,
-				  EXTCON_PROP_USB_TYPEC_POLARITY, &property);
-	if (ret) {
-		dev_err(dp->dev, "get property failed\n");
-		goto err_hpd;
-	}
-
-	ret = cdn_dp_fb_set_host_cap(dp, cap_lanes, property.intval);
-	if (ret) {
-		dev_err(dp->dev, "set host capabilities failed: %d\n", ret);
-		goto err_hpd;
-	}
-
-	ret = cdn_dp_get_dpcd(dp, port);
-	if (ret)
-		goto err_hpd;
-
-	return 0;
-
-err_hpd:
-	cdn_dp_grf_write(dp, GRF_SOC_CON26,
-			 DPTX_HPD_SEL_MASK | DPTX_HPD_DEL);
-
-err_grf:
-	if (dp->fw_actived)
-		cdn_dp_fb_set_firmware_active(dp, false);
-
-err_firmware:
-	if (phy_power_off(port->phy))
-		dev_err(dp->dev, "phy power off failed: %d", ret);
-	else
-		port->phy_status = false;
-
-err_phy:
-	cdn_dp_clk_disable(dp);
-	dp->fw_clk_enabled = false;
-	return ret;
-}
-
-static int cdn_dp_pd_event(struct notifier_block *nb,
-			   unsigned long event, void *priv)
-{
-	struct cdn_dp_port *port;
-
-	port = container_of(nb, struct cdn_dp_port, event_nb);
-	schedule_delayed_work(&port->event_wq, 0);
-	return 0;
-}
-
-static void cdn_dp_pd_event_wq(struct work_struct *work)
-{
-	struct cdn_dp_port *port = container_of(work, struct cdn_dp_port,
-						event_wq.work);
-	struct cdn_dp_device *dp = port->dp;
-	u8 new_cap_lanes, sink_count, i;
-	int ret;
-
-	mutex_lock(&dp->lock);
-	wake_lock_timeout(&dp->wake_lock, msecs_to_jiffies(1000));
-
-	new_cap_lanes = cdn_dp_get_cap_lanes(dp, port->extcon);
-
-	if (new_cap_lanes == port->cap_lanes) {
-		if (!new_cap_lanes) {
-			dev_err(dp->dev, "dp lanes is 0, and same with last time\n");
-			goto out;
-		}
-
-		/*
-		 * If HPD interrupt is triggered, and cable states is still
-		 * attached, that means something on the Type-C Dock/Dongle
-		 * changed, check the sink count by DPCD. If sink count became
-		 * 0, this port phy can be powered off; if the sink count does
-		 * not change and dp is connected, don't do anything, because
-		 * dp video output maybe ongoing. if dp is not connected, that
-		 * means something is wrong, we don't do anything here, just
-		 * output error log.
-		 */
-		cdn_dp_fb_dpcd_read(dp, DP_SINK_COUNT, &sink_count, 1);
-		if (sink_count) {
-			if (dp->hpd_status == connector_status_connected)
-				dev_info(dp->dev,
-					 "hpd interrupt is triggered when dp has been already connected\n");
-			else
-				dev_err(dp->dev,
-					"something is wrong, hpd is triggered before dp is connected\n");
-
-			goto out;
-		} else {
-			new_cap_lanes = 0;
-		}
-	}
-
-	if (dp->hpd_status == connector_status_connected && new_cap_lanes) {
-		dev_err(dp->dev, "error, dp connector has already been connected\n");
-		goto out;
-	}
-
-	if (!new_cap_lanes) {
-		dev_info(dp->dev, "dp lanes is 0, enter standby\n");
-		cdn_dp_enter_standy(dp, port);
-		goto out;
-	}
-
-	/* if other phy is running, do not do anything, just return */
-	for (i = 0; i < dp->ports; i++) {
-		if (dp->port[i]->phy_status) {
-			dev_warn(dp->dev, "busy, phy[%d] is running",
-				 dp->port[i]->id);
-			goto out;
-		}
-	}
-
-	ret = cdn_dp_start_work(dp, port, new_cap_lanes);
-	if (ret) {
-		dev_err(dp->dev, "dp failed to connect ,error = %d\n", ret);
-		goto out;
-	}
-	port->cap_lanes = new_cap_lanes;
-	dp->hpd_status = connector_status_connected;
-	wake_unlock(&dp->wake_lock);
-	mutex_unlock(&dp->lock);
-	hpd_change(dp->dev, new_cap_lanes);
-
-	return;
-out:
-	wake_unlock(&dp->wake_lock);
-	mutex_unlock(&dp->lock);
-}
-
-static int cdn_dp_bind(struct cdn_dp_device *dp)
-{
-	struct cdn_dp_port *port;
-	int ret, i;
-
-	ret = cdn_dp_init(dp);
-	if (ret < 0)
-		return ret;
-
-	dp->hpd_status = connector_status_disconnected;
-	dp->fw_wait = 1;
-	cdn_dp_audio_codec_init(dp, dp->dev);
-
-	for (i = 0; i < dp->ports; i++) {
-		port = dp->port[i];
-
-		port->event_nb.notifier_call = cdn_dp_pd_event;
-		INIT_DELAYED_WORK(&port->event_wq, cdn_dp_pd_event_wq);
-		ret = extcon_register_notifier(port->extcon, EXTCON_DISP_DP,
-					       &port->event_nb);
-		if (ret) {
-			dev_err(dp->dev, "regitster EXTCON_DISP_DP notifier err\n");
-			return ret;
-		}
-
-		if (extcon_get_state(port->extcon, EXTCON_DISP_DP))
-			schedule_delayed_work(&port->event_wq,
-							msecs_to_jiffies(2000));
-	}
-
-	return 0;
-}
-
-int cdn_dp_fb_suspend(void *dp_dev)
-{
-	struct cdn_dp_device *dp = dp_dev;
-	struct cdn_dp_port *port;
-	int i;
-
-	for (i = 0; i < dp->ports; i++) {
-		port = dp->port[i];
-		if (port->phy_status) {
-			cdn_dp_fb_dpcd_write(dp, DP_SET_POWER, DP_SET_POWER_D3);
-			cdn_dp_enter_standy(dp, port);
-		}
-	}
-
-	/*
-	 * if dp has been suspended, need to download firmware
-	 * and set fw clk again.
-	 */
-	dp->fw_clk_enabled = false;
-	dp->fw_loaded = false;
-	dp->suspend = true;
-	return 0;
-}
-
-int cdn_dp_fb_resume(void *dp_dev)
-{
-	struct cdn_dp_device *dp = dp_dev;
-	struct cdn_dp_port *port;
-	int i;
-	if (dp->suspend) {
-		dp->suspend = false;
-		for (i = 0; i < dp->ports; i++) {
-			port = dp->port[i];
-			schedule_delayed_work(&port->event_wq, 0);
-			flush_delayed_work(&port->event_wq);
-		}
-	}
-
-	return 0;
-}
-
-static int cdn_dp_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	const struct of_device_id *match;
-	struct cdn_dp_data *dp_data;
-	struct cdn_dp_port *port;
-	struct cdn_dp_device *dp;
-	struct extcon_dev *extcon;
-	struct phy *phy;
-	int i, ret;
-
-	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
-	if (!dp)
-		return -ENOMEM;
-	dp->dev = dev;
-	g_dp = dp;
-
-	match = of_match_node(cdn_dp_dt_ids, pdev->dev.of_node);
-	dp_data = (struct cdn_dp_data *)match->data;
-
-	for (i = 0; i < dp_data->max_phy; i++) {
-		extcon = extcon_get_edev_by_phandle(dev, i);
-		phy = devm_of_phy_get_by_index(dev, dev->of_node, i);
-
-		if (PTR_ERR(extcon) == -EPROBE_DEFER ||
-		    PTR_ERR(phy) == -EPROBE_DEFER){
-			/* don't exit if there already has one port */
-			if(dp->ports)
-				continue;
-			return -EPROBE_DEFER;
-
-		}
-
-		if (IS_ERR(extcon) || IS_ERR(phy))
-			continue;
-
-		port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
-		if (!port)
-			return -ENOMEM;
-
-		port->extcon = extcon;
-		port->phy = phy;
-		port->dp = dp;
-		port->id = i;
-		dp->port[dp->ports++] = port;
-	}
-
-	if (!dp->ports) {
-		dev_err(dev, "missing extcon or phy\n");
-		return -EINVAL;
-	}
-
-	cdn_dp_bind(dp);
-	ret = cdn_dp_fb_register(pdev, dp);
-
-	return ret;
-}
-
-static struct platform_driver cdn_dp_driver = {
-	.probe = cdn_dp_probe,
-	.driver = {
-		   .name = "cdn-dp-fb",
-		   .owner = THIS_MODULE,
-		   .of_match_table = of_match_ptr(cdn_dp_dt_ids),
-	},
-};
-
-module_platform_driver(cdn_dp_driver);
-
-MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
-MODULE_DESCRIPTION("cdn DP Driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/rockchip/dp/rockchip_dp_core.h b/drivers/video/rockchip/dp/rockchip_dp_core.h
deleted file mode 100644
index 05dd66541851..000000000000
--- a/drivers/video/rockchip/dp/rockchip_dp_core.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ROCKCHIP_DP_CORE_H__
-#define __ROCKCHIP_DP_CORE_H__
-
-/* dp grf register offset */
-#define GRF_SOC_CON9		0x6224
-#define GRF_SOC_CON26		0x6268
-
-#define DPTX_HPD_SEL		(3 << 12)
-#define DPTX_HPD_DEL		(2 << 12)
-#define DPTX_HPD_SEL_MASK	(3 << 28)
-
-#define DP_SEL_VOP_LIT		BIT(12)
-#define MAX_FW_WAIT_SECS	64
-#define EDID_BLOCK_SIZE		128
-#define CDN_DP_FIRMWARE	"cdn/dptx.bin"
-
-struct dp_disp_info {
-	struct fb_videomode *mode;
-	int color_depth;
-	int vsync_polarity;
-	int hsync_polarity;
-	int vop_sel;
-};
-
-struct cdn_dp_data {
-	u8 max_phy;
-};
-
-struct dp_dev {
-	struct dp_disp_info disp_info;
-	struct hdmi *hdmi;
-	void *dp;
-	struct notifier_block fb_notif;
-	int lanes;
-	bool early_suspended;
-};
-
-int cdn_dp_fb_register(struct platform_device *pdev, void *dp);
-void hpd_change(struct device *dev, int lanes);
-
-#endif