Merge tag 'reset-for-v5.12' of git://git.pengutronix.de/pza/linux into arm/drivers

Reset controller updates for v5.12

This tag adds support for Broadcom BCM4908 PCIe resets, corrects
the Hisilicon vendor prefix, adds a missing API function
devm_reset_control_get_optional_exclusive_released(), and fixes
the kernel-doc markup for the __device_reset() function.

* tag 'reset-for-v5.12' of git://git.pengutronix.de/pza/linux:
  reset: Add devm_reset_control_get_optional_exclusive_released()
  reset: core: fix a kernel-doc markup
  dt-bindings: reset: convert Hisilicon reset controller bindings to json-schema
  dt-bindings: reset: correct vendor prefix hisi to hisilicon
  reset: hisilicon: correct vendor prefix
  reset: simple: add BCM4908 MISC PCIe reset controller support
  dt-bindings: reset: document Broadcom's BCM4908 PCIe reset binding

Link: https://lore.kernel.org/r/20210129153108.GA26994@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2021-01-30 11:56:29 +01:00
8 changed files with 147 additions and 49 deletions

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@@ -0,0 +1,39 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/brcm,bcm4908-misc-pcie-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom MISC block PCIe reset controller
description: This document describes reset controller handling PCIe PERST#
signals. On BCM4908 it's a part of the MISC block.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
const: brcm,bcm4908-misc-pcie-reset
reg:
maxItems: 1
"#reset-cells":
description: PCIe core id
const: 1
required:
- compatible
- reg
- "#reset-cells"
additionalProperties: false
examples:
- |
reset-controller@ff802644 {
compatible = "brcm,bcm4908-misc-pcie-reset";
reg = <0xff802644 0x04>;
#reset-cells = <1>;
};

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@@ -1,44 +0,0 @@
Hisilicon System Reset Controller
======================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
The reset controller registers are part of the system-ctl block on
hi3660 and hi3670 SoCs.
Required properties:
- compatible: should be one of the following:
"hisilicon,hi3660-reset" for HI3660
"hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670
- hisi,rst-syscon: phandle of the reset's syscon.
- #reset-cells : Specifies the number of cells needed to encode a
reset source. The type shall be a <u32> and the value shall be 2.
Cell #1 : offset of the reset assert control
register from the syscon register base
offset + 4: deassert control register
offset + 8: status control register
Cell #2 : bit position of the reset in the reset control register
Example:
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3660-iomcu", "syscon";
reg = <0x0 0xffd7e000 0x0 0x1000>;
};
iomcu_rst: iomcu_rst_controller {
compatible = "hisilicon,hi3660-reset";
hisi,rst-syscon = <&iomcu>;
#reset-cells = <2>;
};
Specifying reset lines connected to IP modules
==============================================
example:
i2c0: i2c@..... {
...
resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */
...
};

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@@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon System Reset Controller
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: |
Please also refer to reset.txt in this directory for common reset
controller binding usage.
The reset controller registers are part of the system-ctl block on
hi3660 and hi3670 SoCs.
properties:
compatible:
oneOf:
- items:
- const: hisilicon,hi3660-reset
- items:
- const: hisilicon,hi3670-reset
- const: hisilicon,hi3660-reset
hisilicon,rst-syscon:
description: phandle of the reset's syscon.
$ref: /schemas/types.yaml#/definitions/phandle
'#reset-cells':
description: |
Specifies the number of cells needed to encode a reset source.
Cell #1 : offset of the reset assert control register from the syscon
register base
offset + 4: deassert control register
offset + 8: status control register
Cell #2 : bit position of the reset in the reset control register
const: 2
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3660-clock.h>
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3660-iomcu", "syscon";
reg = <0xffd7e000 0x1000>;
};
iomcu_rst: iomcu_rst_controller {
compatible = "hisilicon,hi3660-reset";
hisilicon,rst-syscon = <&iomcu>;
#reset-cells = <2>;
};
/* Specifying reset lines connected to IP modules */
i2c@ffd71000 {
compatible = "snps,designware-i2c";
reg = <0xffd71000 0x1000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
resets = <&iomcu_rst 0x20 3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
status = "disabled";
};
...

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@@ -173,7 +173,7 @@ config RESET_SCMI
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
default ARCH_AGILEX || ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
help
This enables a simple reset controller driver for reset lines that
that can be asserted and deasserted by toggling bits in a contiguous,

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@@ -875,8 +875,8 @@ struct reset_control *__devm_reset_control_get(struct device *dev,
EXPORT_SYMBOL_GPL(__devm_reset_control_get);
/**
* device_reset - find reset controller associated with the device
* and perform reset
* __device_reset - find reset controller associated with the device
* and perform reset
* @dev: device to be reset by the controller
* @optional: whether it is optional to reset the device
*

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@@ -83,9 +83,14 @@ static int hi3660_reset_probe(struct platform_device *pdev)
if (!rc)
return -ENOMEM;
rc->map = syscon_regmap_lookup_by_phandle(np, "hisi,rst-syscon");
rc->map = syscon_regmap_lookup_by_phandle(np, "hisilicon,rst-syscon");
if (rc->map == ERR_PTR(-ENODEV)) {
/* fall back to the deprecated compatible */
rc->map = syscon_regmap_lookup_by_phandle(np,
"hisi,rst-syscon");
}
if (IS_ERR(rc->map)) {
dev_err(dev, "failed to get hi3660,rst-syscon\n");
dev_err(dev, "failed to get hisilicon,rst-syscon\n");
return PTR_ERR(rc->map);
}

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@@ -146,6 +146,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
{ .compatible = "aspeed,ast2500-lpc-reset" },
{ .compatible = "bitmain,bm1880-reset",
.data = &reset_simple_active_low },
{ .compatible = "brcm,bcm4908-misc-pcie-reset",
.data = &reset_simple_active_low },
{ .compatible = "snps,dw-high-reset" },
{ .compatible = "snps,dw-low-reset",
.data = &reset_simple_active_low },

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@@ -362,6 +362,25 @@ __must_check devm_reset_control_get_exclusive_released(struct device *dev,
return __devm_reset_control_get(dev, id, 0, false, false, false);
}
/**
* devm_reset_control_get_optional_exclusive_released - resource managed
* reset_control_get_optional_exclusive_released()
* @dev: device to be reset by the controller
* @id: reset line name
*
* Managed-and-optional variant of reset_control_get_exclusive_released(). For
* reset controllers returned from this function, reset_control_put() is called
* automatically on driver detach.
*
* See reset_control_get_exclusive_released() for more information.
*/
static inline struct reset_control *
__must_check devm_reset_control_get_optional_exclusive_released(struct device *dev,
const char *id)
{
return __devm_reset_control_get(dev, id, 0, false, true, false);
}
/**
* devm_reset_control_get_shared - resource managed reset_control_get_shared()
* @dev: device to be reset by the controller