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MALI: bifrost: rockchip: make sure pvtpll work fine when pd on/off

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1. switch to normal pll(200M) before disable pd.
2. call pm_runtime_get() to enable pd before change freq(pvtpll).

Change-Id: I8749025c42ec40604361db4d4de2c2b819e0b2a3
Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
2021-12-25 20:18:01 +08:00
committed by Tao Huang
parent 72fefcc13b
commit 7ccbdc84a9
2 changed files with 19 additions and 0 deletions
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5
drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c
View File

@@ -34,6 +34,7 @@
#include <linux/version.h>
#include <linux/pm_opp.h>
#include <linux/pm_runtime.h>
#include <soc/rockchip/rockchip_ipa.h>
#include <soc/rockchip/rockchip_opp_select.h>
@@ -227,6 +228,8 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags)
}
#endif
/* enable pd for pvtpll clk for px30s/rk3326s */
pm_runtime_get_sync(dev);
for (i = 0; i < kbdev->nr_clocks; i++) {
if (kbdev->clocks[i]) {
int err;
@@ -237,10 +240,12 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags)
} else {
dev_err(dev, "Failed to set clock %lu (target %lu)\n",
freqs[i], *target_freq);
pm_runtime_put_sync(dev);
return err;
}
}
}
pm_runtime_put_sync(dev);
#if IS_ENABLED(CONFIG_REGULATOR)
for (i = 0; i < kbdev->nr_clocks; i++) {

14
drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c
View File

@@ -169,11 +169,25 @@ struct kbase_platform_funcs_conf platform_funcs = {
static int rk_pm_callback_runtime_on(struct kbase_device *kbdev)
{
int i;
for (i = 0; i < kbdev->nr_clocks; i++) {
if (kbdev->clocks[i])
clk_set_rate(kbdev->clocks[i], kbdev->current_freqs[i]);
}
return 0;
}
static void rk_pm_callback_runtime_off(struct kbase_device *kbdev)
{
int i;
for (i = 0; i < kbdev->nr_clocks; i++) {
/* switch to normal pll(200M) before disable pd */
if (kbdev->clocks[i])
clk_set_rate(kbdev->clocks[i], 200000000);
}
}
static int rk_pm_callback_power_on(struct kbase_device *kbdev)