From 7cd68dc9116ac0dc5e1b67f0aa5f82a96a2a53f8 Mon Sep 17 00:00:00 2001 From: Leo Sun Date: Wed, 4 Jun 2025 14:01:37 +0800 Subject: [PATCH] media: rockchip: sc850sl: Support for 40 frame rates Change-Id: Idbaef7b7b9a1286b08733dc20e3200ae9266265f Signed-off-by: Leo Sun --- drivers/media/i2c/sc850sl.c | 240 +++++++++++++++++++++++++++++++++++- 1 file changed, 234 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/sc850sl.c b/drivers/media/i2c/sc850sl.c index 4404866b6c91..2abad1b2d37b 100644 --- a/drivers/media/i2c/sc850sl.c +++ b/drivers/media/i2c/sc850sl.c @@ -41,8 +41,10 @@ #endif #define MIPI_FREQ_540M 540000000 +#define MIPI_FREQ_972M 486000000 +#define SC850AI_MAX_LINK_FREQ MIPI_FREQ_540M -#define SC850SL_MAX_PIXEL_RATE (MIPI_FREQ_540M / 10 * 2 * SC850SL_4LANES) +#define SC850SL_MAX_PIXEL_RATE (SC850AI_MAX_LINK_FREQ / 10 * 2 * SC850SL_4LANES) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode" #define SC850SL_XVCLK_FREQ_24M 24000000 @@ -144,6 +146,7 @@ struct sc850sl_mode { u32 vts_def; u32 exp_def; u32 mipi_freq_idx; + u32 xvclk_freq; u32 bpp; const struct regval *reg_list; u32 hdr_mode; @@ -195,7 +198,7 @@ struct sc850sl { #define to_sc850sl(sd) container_of(sd, struct sc850sl, subdev) //cleaned_0x20_SC850SL_MIPI_24Minput_1C4D_1080Mbps_10bit_3840x2160_30fps_one_expo.ini -static __maybe_unused const struct regval sc850sl_linear10bit_3840x2160_regs[] = { +static __maybe_unused const struct regval sc850sl_linear10bit_3840x2160_30fps_regs[] = { {0x0103, 0x01}, {0x0100, 0x00}, {0x36e9, 0x80}, @@ -394,6 +397,208 @@ static __maybe_unused const struct regval sc850sl_linear10bit_3840x2160_regs[] = {REG_NULL, 0x00}, }; +static __maybe_unused const struct regval sc850sl_linear10bit_3840x2160_40fps_regs[] = { + {0x0103, 0x01}, + {0x0100, 0x00}, + {0x36e9, 0x80}, + {0x36f9, 0x80}, + {0x36ea, 0x09}, + {0x36eb, 0x0c}, + {0x36ec, 0x4b}, + {0x36ed, 0x34}, + {0x36fa, 0xcb}, + {0x36fb, 0x13}, + {0x36fc, 0x00}, + {0x36fd, 0x07}, + {0x36e9, 0x53}, + {0x36f9, 0x53}, + {0x3000, 0x01}, + {0x3018, 0x7a}, + {0x3019, 0xf0}, + {0x301a, 0x30}, + {0x301e, 0x3c}, + {0x301f, 0x0d}, + {0x302a, 0x00}, + {0x3031, 0x0a}, + {0x3032, 0x20}, + {0x3033, 0x22}, + {0x3037, 0x60}, + {0x303e, 0xb4}, + {0x3201, 0x98}, + {0x3203, 0x0c}, + {0x3205, 0xa7}, + {0x3207, 0x83}, + {0x320c, 0x03}, + {0x320d, 0x39}, + {0x3211, 0x08}, + {0x3213, 0x2c}, + {0x3223, 0xc0}, + {0x3226, 0x00}, + {0x3227, 0x03}, + {0x3230, 0x11}, + {0x3231, 0x93}, + {0x3250, 0x40}, + {0x3253, 0x08}, + {0x327e, 0x00}, + {0x3280, 0x00}, + {0x3281, 0x00}, + {0x3301, 0x24}, + {0x3304, 0x30}, + {0x3306, 0x54}, + {0x3308, 0x10}, + {0x3309, 0x60}, + {0x330a, 0x00}, + {0x330b, 0xa0}, + {0x330d, 0x10}, + {0x3314, 0x92}, + {0x331e, 0x29}, + {0x331f, 0x59}, + {0x3333, 0x10}, + {0x3347, 0x05}, + {0x3348, 0xd0}, + {0x3352, 0x01}, + {0x3356, 0x38}, + {0x335d, 0x60}, + {0x3362, 0x70}, + {0x338f, 0x80}, + {0x33af, 0x48}, + {0x33fe, 0x00}, + {0x3400, 0x12}, + {0x3406, 0x04}, + {0x3410, 0x12}, + {0x3416, 0x06}, + {0x3433, 0x01}, + {0x3440, 0x12}, + {0x3446, 0x08}, + {0x3478, 0x01}, + {0x3479, 0x01}, + {0x347a, 0x02}, + {0x347b, 0x01}, + {0x347c, 0x04}, + {0x347d, 0x01}, + {0x3616, 0x0c}, + {0x3620, 0x94}, + {0x3622, 0x74}, + {0x3629, 0x74}, + {0x362a, 0xf0}, + {0x362b, 0x0f}, + {0x362d, 0x00}, + {0x3630, 0x68}, + {0x3633, 0x24}, + {0x3634, 0x22}, + {0x3635, 0x20}, + {0x3637, 0x18}, + {0x3638, 0x26}, + {0x363b, 0x06}, + {0x363c, 0x07}, + {0x363d, 0x05}, + {0x363e, 0x8f}, + {0x3648, 0xe0}, + {0x3649, 0x0a}, + {0x364a, 0x06}, + {0x364c, 0x6a}, + {0x3650, 0x3d}, + {0x3654, 0x70}, + {0x3656, 0x68}, + {0x3657, 0x0f}, + {0x3658, 0x3d}, + {0x365c, 0x40}, + {0x365e, 0x68}, + {0x3901, 0x04}, + {0x3902, 0xf1}, + {0x3904, 0x20}, + {0x3905, 0x91}, + {0x391e, 0x03}, + {0x3928, 0x04}, + {0x3933, 0xa0}, + {0x3934, 0x0a}, + {0x3935, 0x68}, + {0x3936, 0x00}, + {0x3937, 0x20}, + {0x3938, 0x0a}, + {0x3946, 0x20}, + {0x3961, 0x40}, + {0x3962, 0x40}, + {0x3963, 0xc8}, + {0x3964, 0xc8}, + {0x3965, 0x40}, + {0x3966, 0x40}, + {0x3967, 0x00}, + {0x39cd, 0xc8}, + {0x39ce, 0xc8}, + {0x3e01, 0x82}, + {0x3e02, 0x00}, + {0x3e0e, 0x02}, + {0x3e0f, 0x00}, + {0x3e1c, 0x0f}, + {0x3e23, 0x00}, + {0x3e24, 0x00}, + {0x3e53, 0x00}, + {0x3e54, 0x00}, + {0x3e68, 0x00}, + {0x3e69, 0x80}, + {0x3e73, 0x00}, + {0x3e74, 0x00}, + {0x3e86, 0x03}, + {0x3e87, 0x40}, + {0x3f02, 0x24}, + {0x4424, 0x02}, + {0x4501, 0xb4}, + {0x4503, 0x20}, + {0x4509, 0x20}, + {0x4561, 0x12}, + {0x4800, 0x24}, + {0x4837, 0x20}, + {0x4900, 0x24}, + {0x4937, 0x16}, + {0x5000, 0x0e}, + {0x500f, 0x35}, + {0x5020, 0x00}, + {0x5787, 0x10}, + {0x5788, 0x06}, + {0x5789, 0x00}, + {0x578a, 0x18}, + {0x578b, 0x0c}, + {0x578c, 0x00}, + {0x5790, 0x10}, + {0x5791, 0x06}, + {0x5792, 0x01}, + {0x5793, 0x18}, + {0x5794, 0x0c}, + {0x5795, 0x01}, + {0x5799, 0x06}, + {0x57a2, 0x60}, + {0x59e0, 0xfe}, + {0x59e1, 0x40}, + {0x59e2, 0x38}, + {0x59e3, 0x30}, + {0x59e4, 0x20}, + {0x59e5, 0x38}, + {0x59e6, 0x30}, + {0x59e7, 0x20}, + {0x59e8, 0x3f}, + {0x59e9, 0x38}, + {0x59ea, 0x30}, + {0x59eb, 0x3f}, + {0x59ec, 0x38}, + {0x59ed, 0x30}, + {0x59ee, 0xfe}, + {0x59ef, 0x40}, + {0x59f4, 0x38}, + {0x59f5, 0x30}, + {0x59f6, 0x20}, + {0x59f7, 0x38}, + {0x59f8, 0x30}, + {0x59f9, 0x20}, + {0x59fa, 0x3f}, + {0x59fb, 0x38}, + {0x59fc, 0x30}, + {0x59fd, 0x3f}, + {0x59fe, 0x38}, + {0x59ff, 0x30}, + {REG_NULL, 0x00}, +}; + /* * The width and height must be configured to be * the same as the current output resolution of the sensor. @@ -407,6 +612,26 @@ static __maybe_unused const struct regval sc850sl_linear10bit_3840x2160_regs[] = * } */ static const struct sc850sl_mode supported_modes[] = { +#if defined CONFIG_VIDEO_CAM_SLEEP_WAKEUP + { + .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, + .width = 3840, + .height = 2160, + .max_fps = { + .numerator = 10000, + .denominator = 400000, + }, + .exp_def = 0x08c0, + .hts_def = 0x10e0, + .vts_def = 0x08ca, + .reg_list = sc850sl_linear10bit_3840x2160_40fps_regs, + .hdr_mode = NO_HDR, + .xvclk_freq = 24000000, + .mipi_freq_idx = 1, + .bpp = 10, + .vc[PAD0] = 0, + }, +#endif { .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, .width = 3840, @@ -419,8 +644,9 @@ static const struct sc850sl_mode supported_modes[] = { .hts_def = 0x0226 * 5 - 0x180, .vts_def = 0x08ca, .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, - .reg_list = sc850sl_linear10bit_3840x2160_regs, + .reg_list = sc850sl_linear10bit_3840x2160_30fps_regs, .hdr_mode = NO_HDR, + .xvclk_freq = 24000000, .mipi_freq_idx = 0, .bpp = 10, .vc[PAD0] = 0, @@ -441,6 +667,7 @@ static const char *const sc850sl_test_pattern_menu[] = { static const s64 link_freq_items[] = { MIPI_FREQ_540M, + MIPI_FREQ_972M, }; /* Write registers up to 4 at a time */ @@ -1025,6 +1252,7 @@ static long sc850sl_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) case RKMODULE_SET_QUICK_STREAM: stream = *((u32 *)arg); + dev_info(&sc850sl->client->dev, "stream: %d\n", stream); if (stream) { ret |= sc850sl_write_reg(sc850sl->client, 0x3019, @@ -1354,10 +1582,10 @@ static int __sc850sl_power_on(struct sc850sl *sc850sl) if (ret < 0) dev_err(dev, "could not set pins\n"); } - ret = clk_set_rate(sc850sl->xvclk, SC850SL_XVCLK_FREQ_24M); + ret = clk_set_rate(sc850sl->xvclk, sc850sl->cur_mode->xvclk_freq); if (ret < 0) dev_warn(dev, "Failed to set xvclk rate 24MHz\n"); - if (clk_get_rate(sc850sl->xvclk) != SC850SL_XVCLK_FREQ_24M) + if (clk_get_rate(sc850sl->xvclk) != sc850sl->cur_mode->xvclk_freq) dev_warn(dev, "xvclk mismatched\n"); ret = clk_prepare_enable(sc850sl->xvclk); if (ret < 0) { @@ -1973,7 +2201,7 @@ static int sc850sl_probe(struct i2c_client *client, #endif if (!sc850sl->cam_sw_info) { sc850sl->cam_sw_info = cam_sw_init(); - cam_sw_clk_init(sc850sl->cam_sw_info, sc850sl->xvclk, SC850SL_XVCLK_FREQ_24M); + cam_sw_clk_init(sc850sl->cam_sw_info, sc850sl->xvclk, sc850sl->cur_mode->xvclk_freq); cam_sw_reset_pin_init(sc850sl->cam_sw_info, sc850sl->reset_gpio, 0); cam_sw_pwdn_pin_init(sc850sl->cam_sw_info, sc850sl->pwdn_gpio, 1); }