From 7dd2a1642cde77b11f72c67b227f5a860ebdd047 Mon Sep 17 00:00:00 2001 From: YoungSoo Shin Date: Fri, 26 Jul 2024 16:03:29 +0900 Subject: [PATCH] ODROID-M2: can: Add overlays for mcp2515 and mcp2517fd mcp2515 - MISO: 21 - MOSI: 19 - SCLK: 23 - CS1 : 26 - INT : 11 mcp2517 (CAN-FD Add-on board) - MISO: 21 - MOSI: 19 - SCLK: 23 - CS0 : 24 - INT : 11 Signed-off-by: YoungSoo Shin Change-Id: I9af389e9538c22a2863218bc03569854dc38bad6 --- .../dts/rockchip/overlays/odroidm2/Makefile | 4 ++ .../dts/rockchip/overlays/odroidm2/canfd0.dts | 51 +++++++++++++++++++ .../rockchip/overlays/odroidm2/mcp2515.dts | 14 +++++ .../rockchip/overlays/odroidm2/mcp2515.dtsi | 51 +++++++++++++++++++ .../overlays/odroidm2/mcp2515_12mhz.dts | 14 +++++ .../overlays/odroidm2/mcp2515_16mhz.dts | 14 +++++ .../boot/dts/rockchip/rk3588s-odroid-m2.dtsi | 8 +++ 7 files changed, 156 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/overlays/odroidm2/canfd0.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515_12mhz.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515_16mhz.dts diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm2/Makefile b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/Makefile index 589711743e38..dc61473373da 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/odroidm2/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/Makefile @@ -3,12 +3,16 @@ dtbo-y += \ blueled_off.dtbo \ can0.dtbo \ + canfd0.dtbo \ dht11.dtbo \ display_vu8s.dtbo \ gpio_shortcut.dtbo \ i2c0.dtbo \ i2c1.dtbo \ i2c2.dtbo \ + mcp2515.dtbo \ + mcp2515_12mhz.dtbo \ + mcp2515_16mhz.dtbo \ onewire.dtbo \ pwm15.dtbo \ pwm3.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm2/canfd0.dts b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/canfd0.dts new file mode 100644 index 000000000000..be176b6fb577 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/canfd0.dts @@ -0,0 +1,51 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + fragment@0 { + target = <&spi0>; + + __overlay__ { + num_chipselect = <1>; + cs-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + }; + }; + + fragment@1 { + target-path = "/"; + + __overlay__ { + can0_clk: can0_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + }; + }; + + fragment@2 { + target = <&spi0>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp2517fd: canfd@0 { + compatible = "microchip,mcp2517fd"; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251x_int_pins>; + reg = <0>; + clocks = <&can0_clk>; + interrupt-parent = <&gpio3>; + interrupts = ; + spi-max-frequency = <10000000>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515.dts b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515.dts new file mode 100644 index 000000000000..f0cc4bd6e54f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include "mcp2515.dtsi" + +/ { + fragment@1 { + __overlay__ { + can0_clk: can0_clk { + clock-frequency = <8000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515.dtsi b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515.dtsi new file mode 100644 index 000000000000..49bbca5fad38 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515.dtsi @@ -0,0 +1,51 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + fragment@0 { + target = <&spi0>; + + __overlay__ { + num_chipselect = <1>; + cs-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + }; + }; + + fragment@1 { + target-path = "/"; + + __overlay__ { + can0_clk: can0_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8000000>; + }; + }; + }; + + fragment@2 { + target = <&spi0>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + mcp2515: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&mcp251x_int_pins>; + reg = <0>; + clocks = <&can0_clk>; + interrupt-parent = <&gpio3>; + interrupts = ; + spi-max-frequency = <10000000>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515_12mhz.dts b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515_12mhz.dts new file mode 100644 index 000000000000..adbf3c1c2c2c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515_12mhz.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include "mcp2515.dtsi" + +/ { + fragment@1 { + __overlay__ { + can0_clk: can0_clk { + clock-frequency = <12000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515_16mhz.dts b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515_16mhz.dts new file mode 100644 index 000000000000..dfaf880f05d8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/odroidm2/mcp2515_16mhz.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include "mcp2515.dtsi" + +/ { + fragment@1 { + __overlay__ { + can0_clk: can0_clk { + clock-frequency = <16000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dtsi index 2eba721dffb4..2f9db6b2220a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dtsi @@ -1093,3 +1093,11 @@ rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; rockchip,primary-plane = ; }; + +&pinctrl { + can_pins { + mcp251x_int_pins: mcp251x_int_pins { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; \ No newline at end of file