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USB: Modify RK3188 && RK3288 clk.

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This commit is contained in:
wlf
2014-03-18 20:58:58 +08:00
parent 98e837e8cf
commit 7ddafb0945
4 changed files with 77 additions and 75 deletions
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28
arch/arm/boot/dts/rk3188.dtsi
View File

@@ -714,10 +714,10 @@
<0x2000812c 0x8>,
<0x20008138 0x8>;
reg-names = "GRF_SOC_STATUS0",
"GRF_UOC0_BASE",
"GRF_UOC1_BASE",
"GRF_UOC2_BASE",
"GRF_UOC3_BASE";
"GRF_UOC0_BASE",
"GRF_UOC1_BASE",
"GRF_UOC2_BASE",
"GRF_UOC3_BASE";
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg_bvalid";
gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
@@ -736,30 +736,30 @@
};
usb@10180000 {
usb0: usb@10180000 {
compatible = "rockchip,rk3188_usb20_otg";
reg = <0x10180000 0x40000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;
clock-names = "otgphy0", "hclk_otg0";
clocks = <&clk_gates1 5>, <&clk_gates5 13>;
clock-names = "clk_usbphy0", "hclk_usb0";
};
usb@101c0000 {
usb1: usb@101c0000 {
compatible = "rockchip,rk3188_usb20_host";
reg = <0x101c0000 0x40000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;
clock-names = "otgphy1", "hclk_otg1";
clocks = <&clk_gates1 6>, <&clk_gates7 3>;
clock-names = "clk_usbphy1", "hclk_usb1";
};
hsic@10240000 {
hsic: hsic@10240000 {
compatible = "rockchip,rk3188_rk_hsic_host";
reg = <0x10240000 0x40000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
<&clk_hsicphy12m>, <&clk_otgphy1_480m>;
clock-names = "hsicphy480m", "hclk_hsic",
"hsicphy12m", "hsic_otgphy1";
<&clk_hsicphy12m>, <&clk_otgphy1_480m>;
clock-names = "hsicphy_480m", "hclk_hsic",
"hsicphy_12m", "hsic_usbphy1";
};
vmac@10204000 {

56
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -645,19 +645,19 @@
<0xff770348 0x10>, <0xff770358 0x08>,
<0xff770360 0x08>;
reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
"GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
"GRF_UOC0_BASE", "GRF_UOC1_BASE",
"GRF_UOC2_BASE", "GRF_UOC3_BASE",
"GRF_UOC4_BASE";
"GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
"GRF_UOC0_BASE", "GRF_UOC1_BASE",
"GRF_UOC2_BASE", "GRF_UOC3_BASE",
"GRF_UOC4_BASE";
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg_id", "otg_bvalid",
"otg_linestate", "host0_linestate",
"host1_linestate";
"otg_linestate", "host0_linestate",
"host1_linestate";
/*gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,*//*HOST_VBUS_DRV*/
/* <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;*//*OTG_VBUS_DRV*/
/*clocks = <&clk_gates4 5>;*/
/* <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;*//*OTG_VBUS_DRV*/
/*clocks = <&clk_gates7 9>;*/
/*clock-names = "hclk_usb_peri";*/
usb_bc{
@@ -674,46 +674,48 @@
};
};
usb1: usb@ff580000 {
usb0: usb@ff580000 {
compatible = "rockchip,rk3288_usb20_otg";
reg = <0xff580000 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
/*clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;*/
/*clock-names = "otgphy0", "hclk_otg0";*/
/*clocks = <&clk_gates13 4>, <&clk_gates7 4>;*/
/*clock-names = "clk_usbphy0", "hclk_usb0";*/
};
usb2: usb@ff540000 {
usb1: usb@ff540000 {
compatible = "rockchip,rk3288_usb20_host";
reg = <0xff540000 0x40000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
/*clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;*/
/*clock-names = "otgphy1", "hclk_otg1";*/
/*clocks = <&clk_gates13 5>, <&clk_gates7 6>;*/
/*clock-names = "clk_usbphy1", "hclk_usb1";*/
};
usb3: usb@ff520000 {
usb2: usb@ff520000 {
compatible = "rockchip,rk3288_rk_ohci_host";
reg = <0xff520000 0x20000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
/*clocks = ;*/
/*clock-names = ;*/
/*clocks = <&clk_gates13 6>, <&clk_gates7 7>;*/
/*clock-names = "clk_usbphy2", "hclk_usb2";*/
};
usb4: usb@ff500000 {
usb3: usb@ff500000 {
compatible = "rockchip,rk3288_rk_ehci_host";
reg = <0xff500000 0x20000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/*clocks = ;*/
/*clock-names = ;*/
/*clocks = <&clk_gates13 6>, <&clk_gates7 7>;*/
/*clock-names = "clk_usbphy3", "hclk_usb3";*/
};
usb5: hsic@ff5c0000 {
hsic: hsic@ff5c0000 {
compatible = "rockchip,rk3288_rk_hsic_host";
reg = <0xff5c0000 0x40000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
/*clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,*/
/* <&clk_hsicphy12m>, <&clk_otgphy1_480m>;*/
/*clock-names = "hsicphy480m", "hclk_hsic",*/
/* "hsicphy12m", "hsic_otgphy1";*/
/*clocks = <&hsicphy_480m>, <&clk_gates7 8>,*/
/* <&hsicphy_12m>, <&clk_otgphy1_480m>,*/
/* <&clk_otgphy2_480m>;*/
/*clock-names = "hsicphy_480m", "hclk_hsic",*/
/* "hsicphy_12m", "hsic_usbphy1",*/
/* "hsic_usbphy2";*/
};
gmac: eth@ff290000 {

34
drivers/usb/dwc_otg_310/usbdev_rk30.c
View File

@@ -55,15 +55,15 @@ static void usb20otg_clock_init(void* pdata)
struct dwc_otg_platform_data *usbpdata=pdata;
struct clk* ahbclk,*phyclk;
ahbclk = devm_clk_get(usbpdata->dev, "hclk_otg0");
ahbclk = devm_clk_get(usbpdata->dev, "hclk_usb0");
if (IS_ERR(ahbclk)) {
dev_err(usbpdata->dev, "Failed to get hclk_otg0\n");
dev_err(usbpdata->dev, "Failed to get hclk_usb0\n");
return;
}
phyclk = devm_clk_get(usbpdata->dev, "otgphy0");
phyclk = devm_clk_get(usbpdata->dev, "clk_usbphy0");
if (IS_ERR(phyclk)) {
dev_err(usbpdata->dev, "Failed to get otgphy0\n");
dev_err(usbpdata->dev, "Failed to get clk_usbphy0\n");
return;
}
@@ -193,15 +193,15 @@ static void usb20host_clock_init(void* pdata)
struct dwc_otg_platform_data *usbpdata=pdata;
struct clk* ahbclk,*phyclk;
ahbclk = devm_clk_get(usbpdata->dev, "hclk_otg1");
ahbclk = devm_clk_get(usbpdata->dev, "hclk_usb1");
if (IS_ERR(ahbclk)) {
dev_err(usbpdata->dev, "Failed to get hclk_otg1\n");
dev_err(usbpdata->dev, "Failed to get hclk_usb1\n");
return;
}
phyclk = devm_clk_get(usbpdata->dev, "otgphy1");
phyclk = devm_clk_get(usbpdata->dev, "clk_usbphy1");
if (IS_ERR(phyclk)) {
dev_err(usbpdata->dev, "Failed to get otgphy1\n");
dev_err(usbpdata->dev, "Failed to get clk_usbphy1\n");
return;
}
@@ -298,23 +298,23 @@ static void rk_hsic_clock_init(void* pdata)
* to uart mode, otg phy 480MHz clk will be closed automatically
*/
struct rkehci_platform_data *usbpdata=pdata;
struct clk *ahbclk, *phyclk480m_hsic, *phyclk12m_hsic, *phyclk_otgphy1;
struct clk *ahbclk, *phyclk480m_hsic, *phyclk12m_hsic, *phyclk_usbphy1;
phyclk480m_hsic = devm_clk_get(usbpdata->dev, "hsicphy480m");
phyclk480m_hsic = devm_clk_get(usbpdata->dev, "hsicphy_480m");
if (IS_ERR(phyclk480m_hsic)) {
dev_err(usbpdata->dev, "Failed to get hsicphy480m\n");
dev_err(usbpdata->dev, "Failed to get hsicphy_480m\n");
return;
}
phyclk12m_hsic = devm_clk_get(usbpdata->dev, "hsicphy12m");
phyclk12m_hsic = devm_clk_get(usbpdata->dev, "hsicphy_12m");
if (IS_ERR(phyclk12m_hsic)) {
dev_err(usbpdata->dev, "Failed to get hsicphy12m\n");
dev_err(usbpdata->dev, "Failed to get hsicphy_12m\n");
return;
}
phyclk_otgphy1 = devm_clk_get(usbpdata->dev, "hsic_otgphy1");
if (IS_ERR(phyclk_otgphy1)) {
dev_err(usbpdata->dev, "Failed to get hsic_otgphy1\n");
phyclk_usbphy1 = devm_clk_get(usbpdata->dev, "hsic_usbphy1");
if (IS_ERR(phyclk_usbphy1)) {
dev_err(usbpdata->dev, "Failed to get hsic_usbphy1\n");
return;
}
@@ -324,7 +324,7 @@ static void rk_hsic_clock_init(void* pdata)
return;
}
clk_set_parent(phyclk480m_hsic, phyclk_otgphy1);
clk_set_parent(phyclk480m_hsic, phyclk_usbphy1);
usbpdata->hclk_hsic = ahbclk;
usbpdata->hsic_phy_480m = phyclk480m_hsic;

34
drivers/usb/dwc_otg_310/usbdev_rk32.c
View File

@@ -55,15 +55,15 @@ static void usb20otg_clock_init(void* pdata)
struct dwc_otg_platform_data *usbpdata=pdata;
struct clk* ahbclk,*phyclk;
ahbclk = devm_clk_get(usbpdata->dev, "hclk_otg0");
ahbclk = devm_clk_get(usbpdata->dev, "hclk_usb0");
if (IS_ERR(ahbclk)) {
dev_err(usbpdata->dev, "Failed to get hclk_otg0\n");
dev_err(usbpdata->dev, "Failed to get hclk_usb0\n");
return;
}
phyclk = devm_clk_get(usbpdata->dev, "otgphy0");
phyclk = devm_clk_get(usbpdata->dev, "clk_usbphy0");
if (IS_ERR(phyclk)) {
dev_err(usbpdata->dev, "Failed to get otgphy0\n");
dev_err(usbpdata->dev, "Failed to get clk_usbphy0\n");
return;
}
@@ -194,15 +194,15 @@ static void usb20host_clock_init(void* pdata)
struct dwc_otg_platform_data *usbpdata=pdata;
struct clk* ahbclk,*phyclk;
ahbclk = devm_clk_get(usbpdata->dev, "hclk_otg1");
ahbclk = devm_clk_get(usbpdata->dev, "hclk_usb1");
if (IS_ERR(ahbclk)) {
dev_err(usbpdata->dev, "Failed to get hclk_otg1\n");
dev_err(usbpdata->dev, "Failed to get hclk_usb1\n");
return;
}
phyclk = devm_clk_get(usbpdata->dev, "otgphy1");
phyclk = devm_clk_get(usbpdata->dev, "clk_usbphy1");
if (IS_ERR(phyclk)) {
dev_err(usbpdata->dev, "Failed to get otgphy1\n");
dev_err(usbpdata->dev, "Failed to get clk_usbphy1\n");
return;
}
@@ -303,23 +303,23 @@ static void rk_hsic_clock_init(void* pdata)
*/
/*
struct rkehci_platform_data *usbpdata=pdata;
struct clk *ahbclk, *phyclk480m_hsic, *phyclk12m_hsic, *phyclk_otgphy1;
struct clk *ahbclk, *phyclk480m_hsic, *phyclk12m_hsic, *phyclk_usbphy1;
phyclk480m_hsic = devm_clk_get(usbpdata->dev, "hsicphy480m");
phyclk480m_hsic = devm_clk_get(usbpdata->dev, "hsicphy_480m");
if (IS_ERR(phyclk480m_hsic)) {
dev_err(usbpdata->dev, "Failed to get hsicphy480m\n");
dev_err(usbpdata->dev, "Failed to get hsicphy_480m\n");
return;
}
phyclk12m_hsic = devm_clk_get(usbpdata->dev, "hsicphy12m");
phyclk12m_hsic = devm_clk_get(usbpdata->dev, "hsicphy_12m");
if (IS_ERR(phyclk12m_hsic)) {
dev_err(usbpdata->dev, "Failed to get hsicphy12m\n");
dev_err(usbpdata->dev, "Failed to get hsicphy_12m\n");
return;
}
phyclk_otgphy1 = devm_clk_get(usbpdata->dev, "hsic_otgphy1");
if (IS_ERR(phyclk_otgphy1)) {
dev_err(usbpdata->dev, "Failed to get hsic_otgphy1\n");
phyclk_usbphy1 = devm_clk_get(usbpdata->dev, "hsic_usbphy1");
if (IS_ERR(phyclk_usbphy1)) {
dev_err(usbpdata->dev, "Failed to get hsic_usbphy1\n");
return;
}
@@ -329,7 +329,7 @@ static void rk_hsic_clock_init(void* pdata)
return;
}
clk_set_parent(phyclk480m_hsic, phyclk_otgphy1);
clk_set_parent(phyclk480m_hsic, phyclk_usbphy1);
usbpdata->hclk_hsic = ahbclk;
usbpdata->hsic_phy_480m = phyclk480m_hsic;