From 7ddb8b2d97b31f422a5f9769c583fb31b77f33d3 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Mon, 8 Mar 2021 16:56:15 +0800 Subject: [PATCH] clk: rockchip: rk3568: Allow config i2s mclk as out/in This patch exports I2Sx_IOE to allow user to config mclk direction from DT. e.g. i2s2 mclk as output: &ext_codec { clocks = <&cru I2S2_MCLKOUT>; clock-names = "mclk"; assigned-clocks = <&cru I2S2_MCLK_IOE>, <&cru I2S2_MCLKOUT>; assigned-clock-rates = <0>, <12288000>; assigned-clock-parents = <&cru I2S2_MCLKOUT>; }; clk summary: gpll 6 9 0 1188000000 clk_i2s2_2ch_src 0 0 0 594000000 clk_i2s2_2ch_frac 0 0 0 12288000 clk_i2s2_2ch 0 0 0 12288000 mclk_i2s2_2ch 0 0 0 12288000 i2s2_mclkout 0 0 0 12288000 i2s2_mclk_ioe 0 0 0 12288000 i2s2 mclk as input: &ext_codec { clocks = <&i2s2_mclkin>; clock-names = "mclk"; assigned-clocks = <&cru I2S2_MCLK_IOE>, <&cru CLK_I2S2_2CH>; assigned-clock-parents = <&i2s2_mclkin>, <&i2s2_mclkin>; }; clk summary: i2s2_mclkin 0 0 0 12288000 clk_i2s2_2ch 0 0 0 12288000 mclk_i2s2_2ch 0 0 0 12288000 i2s2_mclk_ioe 0 0 0 12288000 Change-Id: I57d10ea02b65bf14d2c2f9ff403f06ec4c33c610 Signed-off-by: Elaine Zhang Signed-off-by: Sugar Zhang --- drivers/clk/rockchip/clk-rk3568.c | 35 ++++++++++++++++++++------ include/dt-bindings/clock/rk3568-cru.h | 6 +++++ 2 files changed, 34 insertions(+), 7 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 296e8e12fd57..5f47d5ff37d7 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -13,6 +13,8 @@ #include #include "clk.h" +#define RK3568_GRF_SOC_CON1 0x504 +#define RK3568_GRF_SOC_CON2 0x508 #define RK3568_GRF_SOC_STATUS0 0x580 #define RK3568_PMU_GRF_SOC_CON0 0x100 @@ -276,13 +278,13 @@ PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" }; PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" }; -PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; -PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; -PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; -PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; -PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; -PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; -PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; +PNAME(i2s0_mclkout_tx_p) = { "mclk_i2s0_8ch_tx", "xin_osc0_half" }; +PNAME(i2s0_mclkout_rx_p) = { "mclk_i2s0_8ch_rx", "xin_osc0_half" }; +PNAME(i2s1_mclkout_tx_p) = { "mclk_i2s1_8ch_tx", "xin_osc0_half" }; +PNAME(i2s1_mclkout_rx_p) = { "mclk_i2s1_8ch_rx", "xin_osc0_half" }; +PNAME(i2s2_mclkout_p) = { "mclk_i2s2_2ch", "xin_osc0_half" }; +PNAME(i2s3_mclkout_tx_p) = { "mclk_i2s3_2ch_tx", "xin_osc0_half" }; +PNAME(i2s3_mclkout_rx_p) = { "mclk_i2s3_2ch_rx", "xin_osc0_half" }; PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" }; PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" }; PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" }; @@ -337,6 +339,12 @@ PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" }; PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" }; PNAME(clk_32k_ioe_p) = { "clk_rtc_32k", "xin32k" }; +PNAME(i2s1_mclkout_p) = { "i2s1_mclkout_rx", "i2s1_mclkout_tx" }; +PNAME(i2s3_mclkout_p) = { "i2s3_mclkout_rx", "i2s3_mclkout_tx" }; +PNAME(i2s1_mclk_rx_ioe_p) = { "i2s1_mclkin_rx", "i2s1_mclkout_rx" }; +PNAME(i2s1_mclk_tx_ioe_p) = { "i2s1_mclkin_tx", "i2s1_mclkout_tx" }; +PNAME(i2s2_mclk_ioe_p) = { "i2s2_mclkin", "i2s2_mclkout" }; +PNAME(i2s3_mclk_ioe_p) = { "i2s3_mclkin", "i2s3_mclkout" }; static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = { [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, @@ -743,6 +751,19 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { RK3568_CLKSEL_CON(83), 15, 1, MFLAGS, RK3568_CLKGATE_CON(7), 11, GFLAGS), + MUXGRF(I2S1_MCLKOUT, "i2s1_mclkout", i2s1_mclkout_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_GRF_SOC_CON1, 5, 1, MFLAGS), + MUXGRF(I2S3_MCLKOUT, "i2s3_mclkout", i2s3_mclkout_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_GRF_SOC_CON2, 15, 1, MFLAGS), + MUXGRF(I2S1_MCLK_RX_IOE, "i2s1_mclk_rx_ioe", i2s1_mclk_rx_ioe_p, 0, + RK3568_GRF_SOC_CON2, 0, 1, MFLAGS), + MUXGRF(I2S1_MCLK_TX_IOE, "i2s1_mclk_tx_ioe", i2s1_mclk_tx_ioe_p, 0, + RK3568_GRF_SOC_CON2, 1, 1, MFLAGS), + MUXGRF(I2S2_MCLK_IOE, "i2s2_mclk_ioe", i2s2_mclk_ioe_p, 0, + RK3568_GRF_SOC_CON2, 2, 1, MFLAGS), + MUXGRF(I2S3_MCLK_IOE, "i2s3_mclk_ioe", i2s3_mclk_ioe_p, 0, + RK3568_GRF_SOC_CON2, 3, 1, MFLAGS), + GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0, RK3568_CLKGATE_CON(5), 14, GFLAGS), COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0, diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h index 22b0b8739b5d..aecfdd4ce084 100644 --- a/include/dt-bindings/clock/rk3568-cru.h +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -479,6 +479,12 @@ #define CPLL_25M 416 #define CPLL_100M 417 #define SCLK_DDRCLK 418 +#define I2S1_MCLKOUT 419 +#define I2S3_MCLKOUT 420 +#define I2S1_MCLK_RX_IOE 421 +#define I2S1_MCLK_TX_IOE 422 +#define I2S2_MCLK_IOE 423 +#define I2S3_MCLK_IOE 424 #define PCLK_CORE_PVTM 450