Merge "ODROID-COMMON: hdmitx: add new hdmi resolutions" into odroidc4-4.9.y

2026-06-09 12:17:12 +09:00 · 2020-03-19 17:58:23 +09:00
parent 63542b4568 0648e30688
commit 7e13728562
9 changed files with 834 additions and 0 deletions
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c
@@ -1333,6 +1333,153 @@ static struct hdmi_format_para fmt_para_4096x2160p60_256x135_y420 = {
 	},
 };

+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+/* new display modes for odroid-n2 */
+static struct hdmi_format_para fmt_para_vesa_2560x1440p60_16x9 = {
+	.vic = HDMIV_2560x1440p60hz,
+	.name = "2560x1440p60hz",
+	.sname = "2560x1440p60hz",
+	.pixel_repetition_factor = 0,
+	.progress_mode = 1,
+	.scrambler_en = 0,
+	.tmds_clk_div40 = 0,
+	.tmds_clk =  241500,
+	.timing = {
+		.pixel_freq = 241500,
+		.frac_freq = 241500,
+		.h_freq = 98700,
+		.v_freq = 60000,
+		.vsync_polarity = 0,
+		.hsync_polarity = 1,
+		.h_active = 2560,
+		.h_total = 2720,
+		.h_blank = 160,
+		.h_front = 48,
+		.h_sync = 32,
+		.h_back = 80,
+		.v_active = 1440,
+		.v_total = 1481,
+		.v_blank = 41,
+		.v_front = 2,
+		.v_sync = 5,
+		.v_back = 34,
+		.v_sync_ln = 1,
+	},
+	.hdmitx_vinfo = {
+		.name              = "2560x1440p60hz",
+		.mode              = VMODE_HDMI,
+		.width             = 2560,
+		.height            = 1440,
+		.field_height      = 1440,
+		.aspect_ratio_num  = 16,
+		.aspect_ratio_den  = 9,
+		.sync_duration_num = 60,
+		.sync_duration_den = 1,
+		.video_clk         = 241500000,
+		.htotal            = 2720,
+		.vtotal            = 1481,
+		.viu_color_fmt     = COLOR_FMT_YUV444,
+		.viu_mux           = VIU_MUX_ENCP,
+	},
+};
+
+static struct hdmi_format_para fmt_para_480x320p60_4x3 = {
+	.vic = HDMI_480x320p60_4x3,
+	.name = "480x320p60hz",
+	.sname = "480x320p60hz",
+	.pixel_repetition_factor = 0,
+	.progress_mode = 1,
+	.scrambler_en = 0,
+	.tmds_clk_div40 = 0,
+	.tmds_clk = 25200,
+	.timing = {
+		.pixel_freq = 25200,
+		.frac_freq = 25200,
+		.h_freq = 31500,
+		.v_freq = 60000,
+		.vsync_polarity = 0, /* -VSync */
+		.hsync_polarity = 0, /* -HSync */
+		.h_active = 480,
+		.h_total = 800,
+		.h_blank = 320,
+		.h_front = 120,
+		.h_sync = 100,
+		.h_back = 100,
+		.v_active = 320,
+		.v_total = 525,
+		.v_blank = 205,
+		.v_front = 8,
+		.v_sync = 8,
+		.v_back = 189,
+		.v_sync_ln = 1,
+	},
+	.hdmitx_vinfo = {
+		.name              = "480x320p60hz",
+		.mode              = VMODE_HDMI,
+		.width             = 480,
+		.height            = 320,
+		.field_height      = 320,
+		.aspect_ratio_num  = 4,
+		.aspect_ratio_den  = 3,
+		.sync_duration_num = 60,
+		.sync_duration_den = 1,
+		.video_clk         = 25200000,
+		.htotal            = 800,
+		.vtotal            = 525,
+		.viu_color_fmt     = COLOR_FMT_YUV444,
+		.viu_mux           = VIU_MUX_ENCP,
+	},
+};
+
+static struct hdmi_format_para fmt_para_480x800p60_4x3 = {
+	.vic = HDMI_480x800p60_4x3,
+	.name = "480x800p60hz",
+	.sname = "480x800p60hz",
+	.pixel_repetition_factor = 0,
+	.progress_mode = 1,
+	.scrambler_en = 0,
+	.tmds_clk_div40 = 0,
+	.tmds_clk = 32000,
+	.timing = {
+		.pixel_freq = 32000,
+		.frac_freq = 32000,
+		.h_freq = 52600,
+		.v_freq = 62300,
+		.vsync_polarity = 0,
+		.hsync_polarity = 0,
+		.h_active = 480,
+		.h_total = 608,
+		.h_blank = 128,
+		.h_front = 40,
+		.h_sync = 48,
+		.h_back = 40,
+		.v_active = 800,
+		.v_total = 845,
+		.v_blank = 45,
+		.v_front = 13,
+		.v_sync = 3,
+		.v_back = 29,
+		.v_sync_ln = 1,
+	},
+	.hdmitx_vinfo = {
+		.name              = "480x800p60hz",
+		.mode              = VMODE_HDMI,
+		.width             = 480,
+		.height            = 800,
+		.field_height      = 800,
+		.aspect_ratio_num  = 4,
+		.aspect_ratio_den  = 3,
+		.sync_duration_num = 60,
+		.sync_duration_den = 1,
+		.video_clk         = 32000000,
+		.htotal            = 608,
+		.vtotal            = 845,
+		.viu_color_fmt     = COLOR_FMT_YUV444,
+		.viu_mux           = VIU_MUX_ENCP,
+	},
+};
+#endif
+
 static struct hdmi_format_para fmt_para_non_hdmi_fmt = {
 	.vic = HDMI_Unknown,
 	.name = "invalid",
@@ -1587,7 +1734,11 @@ static struct hdmi_format_para fmt_para_vesa_800x600p60_4x3 = {
 	.tmds_clk_div40 = 0,
 	.tmds_clk = 40000,
 	.timing = {
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		.pixel_freq = 40000,
+#else
 		.pixel_freq = 66666,
+#endif
 		.h_freq = 37879,
 		.v_freq = 60317,
 		.vsync = 60,
@@ -1617,7 +1768,11 @@ static struct hdmi_format_para fmt_para_vesa_800x600p60_4x3 = {
 		.aspect_ratio_den  = 3,
 		.sync_duration_num = 60,
 		.sync_duration_den = 1,
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		.video_clk         = 40000000,
+#else
 		.video_clk         = 66666000,
+#endif
 		.htotal            = 1056,
 		.vtotal            = 628,
 		.fr_adj_type       = VOUT_FR_ADJ_HDMI,
@@ -2637,6 +2792,11 @@ static struct hdmi_format_para *all_fmt_paras[] = {
 	&fmt_para_vesa_1920x1200p60_8x5,
 	&fmt_para_vesa_2160x1200p90_9x5,
 	&fmt_para_vesa_2560x1600p60_8x5,
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+	&fmt_para_vesa_2560x1440p60_16x9,
+	&fmt_para_480x320p60_4x3,
+	&fmt_para_480x800p60_4x3,
+#endif
 	&fmt_para_null_hdmi_fmt,
 	&fmt_para_non_hdmi_fmt,
 	NULL,
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c
@@ -2628,6 +2628,10 @@ static struct dispmode_vic dispmode_vic_tab[] = {
 	{"2560x1440p60hz", HDMIV_2560x1440p60hz},
 	{"2560x1600p60hz", HDMIV_2560x1600p60hz},
 	{"3440x1440p60hz", HDMIV_3440x1440p60hz},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+	{"480x320p60hz", HDMI_480x320p60_4x3},
+	{"480x800p60hz", HDMI_480x800p60_4x3},
+#endif
 };

 int hdmitx_edid_VIC_support(enum hdmi_vic vic)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c
@@ -2314,6 +2314,10 @@ const char *disp_mode_t[] = {
 	"2560x1440p60hz",
 	"2560x1600p60hz",
 	"3440x1440p60hz",
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+	"480x320p60hz",
+	"480x800p60hz",
+#endif
 	NULL
 };

--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c
@@ -809,6 +809,30 @@ static struct hdmitx_vidpara hdmi_tx_video_params[] = {
 		.ss			= SS_SCAN_UNDER,
 		.sc			= SC_SCALE_HORIZ_VERT,
 	},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+	{
+		.VIC            = HDMI_480x320p60_4x3,
+		.color_prefer   = COLORSPACE_RGB444,
+		.color_depth    = COLORDEPTH_24B,
+		.bar_info       = B_BAR_VERT_HORIZ,
+		.repeat_time    = NO_REPEAT,
+		.aspect_ratio   = ASPECT_RATIO_SAME_AS_SOURCE,
+		.cc             = CC_ITU709,
+		.ss             = SS_SCAN_UNDER,
+		.sc             = SC_SCALE_HORIZ_VERT,
+	},
+	{
+		.VIC            = HDMI_480x800p60_4x3,
+		.color_prefer   = COLORSPACE_RGB444,
+		.color_depth    = COLORDEPTH_24B,
+		.bar_info       = B_BAR_VERT_HORIZ,
+		.repeat_time    = NO_REPEAT,
+		.aspect_ratio   = ASPECT_RATIO_SAME_AS_SOURCE,
+		.cc             = CC_ITU709,
+		.ss             = SS_SCAN_UNDER,
+		.sc             = SC_SCALE_HORIZ_VERT,
+	},
+#endif
 };

 static struct hdmitx_vidpara *hdmi_get_video_param(
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
@@ -1386,6 +1386,87 @@ static const struct reg_s tvregs_vesa_3440x1440p60hz[] = {
 };
 #endif

+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+static const struct reg_s tvregs_vesa_2560x1440p60hz[] = {
+	{P_VENC_VDAC_SETTING, 0xff,},
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+
+	{P_ENCP_VIDEO_MAX_PXCNT, 0xA9F,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x5C8,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x50,},
+	{P_ENCP_VIDEO_HAVON_END, 0xA4F,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x22,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x5C1,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0,},
+	{P_ENCP_VIDEO_HSO_END, 0x20,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x5,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_480x320p_60hz[] = {
+	{P_VENC_VDAC_SETTING, 0xff,},
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x31F,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x20C,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x64,},
+	{P_ENCP_VIDEO_HAVON_END, 0x243,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0xBD,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x1FC,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x64,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x8,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_480x800p_60hz[] = {
+	{P_ENCP_VIDEO_EN, 0},
+	{P_ENCI_VIDEO_EN, 0},
+
+	{P_ENCP_VIDEO_MODE, 0x4040},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18},
+
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x25F},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x34C},
+
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x28},
+	{P_ENCP_VIDEO_HAVON_END, 0x207},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x1D},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x33C},
+
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0},
+	{P_ENCP_VIDEO_HSO_END, 0x30},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E},
+	{P_ENCP_VIDEO_VSO_END, 0x32},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x3},
+
+	{P_ENCP_VIDEO_EN, 1},
+	{P_ENCI_VIDEO_EN, 0},
+	{MREG_END_MARKER, 0},
+};
+#endif
+
 struct vic_tvregs_set {
 	enum hdmi_vic vic;
 	const struct reg_s *reg_setting;
@@ -1450,6 +1531,11 @@ static struct vic_tvregs_set tvregsTab[] = {
 	{HDMIV_1920x1200p60hz, tvregs_vesa_1920x1200p60hz},
 	{HDMIV_2160x1200p90hz, tvregs_vesa_2160x1200p90hz},
 	{HDMIV_2560x1600p60hz, tvregs_vesa_2560x1600p60hz},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+	{HDMIV_2560x1440p60hz, tvregs_vesa_2560x1440p60hz},
+	{HDMI_480x320p60_4x3, tvregs_480x320p_60hz},
+	{HDMI_480x800p60_4x3, tvregs_480x800p_60hz},
+#endif
 };

 /*
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
@@ -1700,7 +1700,9 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
 		TOTAL_FRAMES = 4;
 		break;
 	case HDMI_2560x1080p50_64x27:
+#if !defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
 	case HDMI_2560x1080p60_64x27:
+#endif
 		INTERLACE_MODE	= 0U;
 		PIXEL_REPEAT_VENC  = 0;
 		PIXEL_REPEAT_HDMI  = 0;
@@ -1716,6 +1718,261 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
 		SOF_LINES = hdmi_encp_timing->v_back;
 		TOTAL_FRAMES = 4;
 		break;
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+	case HDMIV_2560x1600p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1600/(1+INTERLACE_MODE));
+		LINES_F0 = 1658;
+		LINES_F1 = 1658;
+		FRONT_PORCH = 192;
+		HSYNC_PIXELS = 280;
+		BACK_PORCH = 472;
+		EOF_LINES = 3;
+		VSYNC_LINES = 6;
+		SOF_LINES = 49;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMIV_2560x1440p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1440/(1+INTERLACE_MODE));
+		LINES_F0 = 1481;
+		LINES_F1 = 1481;
+		FRONT_PORCH = 48;
+		HSYNC_PIXELS = 32;
+		BACK_PORCH = 80;
+		EOF_LINES = 2;
+		VSYNC_LINES = 5;
+		SOF_LINES = 34;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMI_2560x1080p60_64x27:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
+		LINES_F0 = 1100;
+		LINES_F1 = 1100;
+		FRONT_PORCH = 248;
+		HSYNC_PIXELS = 44;
+		BACK_PORCH = 148;
+		EOF_LINES = 4;
+		VSYNC_LINES = 5;
+		SOF_LINES = 11;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMIV_1920x1200p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1200/(1+INTERLACE_MODE));
+		LINES_F0 = 1245;
+		LINES_F1 = 1245;
+		FRONT_PORCH = 136;
+		HSYNC_PIXELS = 200;
+		BACK_PORCH = 336;
+		EOF_LINES = 3;
+		VSYNC_LINES = 6;
+		SOF_LINES = 36;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMIV_1600x1200p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1600*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1200/(1+INTERLACE_MODE));
+		LINES_F0 = 1250;
+		LINES_F1 = 1250;
+		FRONT_PORCH = 64;
+		HSYNC_PIXELS = 192;
+		BACK_PORCH = 304;
+		EOF_LINES = 1;
+		VSYNC_LINES = 3;
+		SOF_LINES = 46;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMIV_1600x900p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1600*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (900/(1+INTERLACE_MODE));
+		LINES_F0 = 1800;
+		LINES_F1 = 1800;
+		FRONT_PORCH = 24;
+		HSYNC_PIXELS = 80;
+		BACK_PORCH = 96;
+		EOF_LINES = 1;
+		VSYNC_LINES = 3;
+		SOF_LINES = 96;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMIV_1440x900p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1440*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (900/(1+INTERLACE_MODE));
+		LINES_F0 = 934;
+		LINES_F1 = 934;
+		FRONT_PORCH = 80;
+		HSYNC_PIXELS = 152;
+		BACK_PORCH = 232;
+		EOF_LINES = 3;
+		VSYNC_LINES = 6;
+		SOF_LINES = 25;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMIV_1280x1024p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1024/(1+INTERLACE_MODE));
+		LINES_F0 = 1066;
+		LINES_F1 = 1066;
+		FRONT_PORCH = 48;
+		HSYNC_PIXELS = 112;
+		BACK_PORCH = 248;
+		EOF_LINES = 1;
+		VSYNC_LINES = 3;
+		SOF_LINES = 38;
+		break;
+	case HDMIV_1280x800p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (800/(1+INTERLACE_MODE));
+		LINES_F0 = 823;
+		LINES_F1 = 823;
+		FRONT_PORCH = 48;
+		HSYNC_PIXELS = 32;
+		BACK_PORCH = 80;
+		EOF_LINES = 3;
+		VSYNC_LINES = 6;
+		SOF_LINES = 14;
+		break;
+	case HDMIV_1024x768p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1024*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (768/(1+INTERLACE_MODE));
+		LINES_F0 = 806;
+		LINES_F1 = 806;
+		FRONT_PORCH = 24;
+		HSYNC_PIXELS = 136;
+		BACK_PORCH = 160;
+		EOF_LINES = 3;
+		VSYNC_LINES = 6;
+		SOF_LINES = 29;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMIV_1024x600p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1024*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (600/(1+INTERLACE_MODE));
+		LINES_F0 = 638;
+		LINES_F1 = 638;
+		FRONT_PORCH = 24;
+		HSYNC_PIXELS = 136;
+		BACK_PORCH = 160;
+		EOF_LINES = 3;
+		VSYNC_LINES = 6;
+		SOF_LINES = 29;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMIV_800x600p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (800*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (600/(1+INTERLACE_MODE));
+		LINES_F0 = 628;
+		LINES_F1 = 628;
+		FRONT_PORCH = 40;
+		HSYNC_PIXELS = 128;
+		BACK_PORCH = 88;
+		EOF_LINES = 1;
+		VSYNC_LINES = 4;
+		SOF_LINES = 23;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMIV_800x480p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (800*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (480/(1+INTERLACE_MODE));
+		LINES_F0 = 500;
+		LINES_F1 = 500;
+		FRONT_PORCH = 24;
+		HSYNC_PIXELS = 72;
+		BACK_PORCH = 96;
+		EOF_LINES = 3;
+		VSYNC_LINES = 7;
+		SOF_LINES = 10;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMIV_640x480p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (640*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (480/(1+INTERLACE_MODE));
+		LINES_F0 = 525;
+		LINES_F1 = 525;
+		FRONT_PORCH = 16;
+		HSYNC_PIXELS = 96;
+		BACK_PORCH = 48;
+		EOF_LINES = 10;
+		VSYNC_LINES = 2;
+		SOF_LINES = 33;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMI_480x320p60_4x3:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (480*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (320/(1+INTERLACE_MODE));
+		LINES_F0 = 263;
+		LINES_F1 = 263;
+		FRONT_PORCH = 120;
+		HSYNC_PIXELS = 100;
+		BACK_PORCH = 100;
+		EOF_LINES = 8;
+		VSYNC_LINES = 4;
+		SOF_LINES = 95;
+		TOTAL_FRAMES = 4;
+		break;
+	case HDMI_480x800p60_4x3:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (480*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (800*(1+PIXEL_REPEAT_HDMI));
+		LINES_F0 = 845;
+		LINES_F1 = 845;
+		FRONT_PORCH = 40;
+		HSYNC_PIXELS = 48;
+		BACK_PORCH = 40;
+		EOF_LINES = 13;
+		VSYNC_LINES = 3;
+		SOF_LINES = 29;
+		break;
+#endif
 	default:
 		break;
 	}
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
@@ -820,54 +820,106 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
 	  HDMI_3840x2160p50_16x9_Y420,
 	  HDMI_VIC_END},
 		5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+	{{HDMIV_2560x1440p60hz,
+	  HDMI_VIC_END},
+		2415000, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+	{{HDMI_480x320p60_4x3,
+	  HDMI_VIC_END},
+		/* actual hpll : 2016000 */
+		2000000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+	{{HDMI_480x800p60_4x3,
+	  HDMI_VIC_END},
+		2560000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+#endif
 	{{HDMI_VIC_FAKE,
 	  HDMI_VIC_END},
 		3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
 	/* pll setting for VESA modes */
 	{{HDMIV_640x480p60hz, /* 4.028G / 16 = 251.75M */
 	  HDMI_VIC_END},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		2000000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+#else
 		4028000, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#endif
 	{{HDMIV_800x480p60hz,
 	  HDMI_VIC_END},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		2415000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+#else
 		4761600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#endif
 	{{HDMIV_800x600p60hz,
 	  HDMI_VIC_END},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		3243240, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+#else
 		3200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#endif
 	{{HDMIV_852x480p60hz,
 	   HDMIV_854x480p60hz,
 	  HDMI_VIC_END},
 		4838400, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
 	{{HDMIV_1024x600p60hz,
 	  HDMI_VIC_END},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		2058000, 4, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+#else
 		4115866, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#endif
 	{{HDMIV_1024x768p60hz,
 	  HDMI_VIC_END},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		2600000, 2, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#else
 		5200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#endif
 	{{HDMIV_1280x768p60hz,
 	  HDMI_VIC_END},
 		3180000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
 	{{HDMIV_1280x800p60hz,
 	  HDMI_VIC_END},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		1422000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#else
 		5680000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#endif
 	{{HDMIV_1152x864p75hz,
 	  HDMIV_1280x960p60hz,
 	  HDMIV_1280x1024p60hz,
 	  HDMIV_1600x900p60hz,
 	  HDMI_VIC_END},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		4324320, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#else
 		4320000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#endif
 	{{HDMIV_1600x1200p60hz,
 	  HDMI_VIC_END},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		3243240, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#else
 		3240000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#endif
 	{{HDMIV_1360x768p60hz,
 	  HDMIV_1366x768p60hz,
 	  HDMI_VIC_END},
 		3420000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
 	{{HDMIV_1400x1050p60hz,
 	  HDMI_VIC_END},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		2134000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#else
 		4870000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#endif
 	{{HDMIV_1440x900p60hz,
 	  HDMI_VIC_END},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		2134000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#else
 		4260000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#endif
 	{{HDMIV_1440x2560p60hz,
 	  HDMI_VIC_END},
 		4897000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
@@ -882,7 +934,11 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
 		5371100, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
 	{{HDMIV_2560x1600p60hz,
 	  HDMI_VIC_END},
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+		3450000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#else
 		3485000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+#endif
 };

 /* For colordepth 10bits */
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
@@ -323,6 +323,245 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
 		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
 		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		break;
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+	case 3960000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004a4);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000110e1);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 3865000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004a0);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000110e1);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 3420000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00048e);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 2685000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00046F);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 2600000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00046C);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 2560000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00046A);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 2415000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000464);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 2134000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00045A);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 2058000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000455);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 2000000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000453);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 1855800:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00044C);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 1560000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000440);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 1540000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00043F);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 1462500:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00043C);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 1422000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00043A);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 320000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00040D);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+#endif
 	default:
 		pr_info("error hpll clk: %d\n", clk);
 		break;
--- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h
+++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h
@@ -158,6 +158,10 @@ enum hdmi_vic {
 	HDMI_3840x1080p100hz,
 	HDMI_3840x540p240hz,
 	HDMI_3840x540p200hz,
+#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+	HDMI_480x320p60_4x3,
+	HDMI_480x800p60_4x3,
+#endif

 	/*
 	 * the following vic is for those y420 mode