From 7e4881a49ef1052abec3de1ceb12be2eee00c4df Mon Sep 17 00:00:00 2001 From: William Wu Date: Tue, 31 Aug 2021 16:12:37 +0800 Subject: [PATCH] usb: dwc3: core: use 2.0 clk for 3.0 if only support 2.0 mode If the dwc3 core is programmed to operate in usb 2.0 only mode, and no usb 3.0 phy, then it needs to set the bit DEV_FORCE_20_CLK_FOR_30_CLK of GUCTL1 to make the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe) clock. Signed-off-by: William Wu Signed-off-by: Bin Yang Change-Id: I217a380815c21903c1090bd003c1d8ba2fadbe7c --- drivers/usb/dwc3/core.c | 4 ++++ drivers/usb/dwc3/core.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 1fd8a5dc7d09..4cea590ca3f6 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1056,6 +1056,10 @@ static int dwc3_core_init(struct dwc3 *dwc) if (dwc->parkmode_disable_ss_quirk) reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; + if (dwc->maximum_speed == USB_SPEED_HIGH || + dwc->maximum_speed == USB_SPEED_FULL) + reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); } diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 07d70418b7bd..2b44bb38bb7a 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -259,6 +259,7 @@ /* Global User Control 1 Register */ #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) +#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) /* Global Status Register */