From 7e70102b91e9cecf622577420d3ece3ce304f9c5 Mon Sep 17 00:00:00 2001
From: Zhibin Huang <zhibin.huang@rock-chips.com>
Date: Fri, 17 May 2024 17:49:58 +0800
Subject: [PATCH] misc: rk628: bt1120: fix read bt1120_dec clock frequency
 error

Type: Fix
Redmine ID: N/A
Associated modifications: N/A
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: I40f80f9d6a0daee6aedbae07cadfe24e7e171e56
---
 drivers/misc/rk628/rk628_cru.c | 16 ++++++++++++++++
 drivers/misc/rk628/rk628_rgb.c |  3 ++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/rk628/rk628_cru.c b/drivers/misc/rk628/rk628_cru.c
index 87123010235b..0a15e4264df3 100644
--- a/drivers/misc/rk628/rk628_cru.c
+++ b/drivers/misc/rk628/rk628_cru.c
@@ -480,6 +480,19 @@ static unsigned long rk628_cru_clk_set_rate_bt1120_dec(struct rk628 *rk628,
 	return parent_rate / div;
 }
 
+static unsigned long rk628_cru_clk_get_rate_bt1120_dec(struct rk628 *rk628)
+{
+	unsigned long parent_rate;
+	u32 div;
+
+	parent_rate = rk628_cru_clk_get_rate_bt1120_dec_parent(rk628);
+
+	rk628_i2c_read(rk628, CRU_CLKSEL_CON02, &div);
+	div = (div & 0x1f) + 1;
+
+	return parent_rate / div;
+}
+
 int rk628_cru_clk_set_rate(struct rk628 *rk628, unsigned int id,
 			   unsigned long rate)
 {
@@ -536,6 +549,9 @@ unsigned long rk628_cru_clk_get_rate(struct rk628 *rk628, unsigned int id)
 	case CGU_CLK_HDMIRX_AUD:
 		rate = rk628_cru_clk_get_rate_sclk_hdmirx_aud(rk628);
 		break;
+	case CGU_BT1120DEC:
+		rate = rk628_cru_clk_get_rate_bt1120_dec(rk628);
+		break;
 	default:
 		return 0;
 	}
diff --git a/drivers/misc/rk628/rk628_rgb.c b/drivers/misc/rk628/rk628_rgb.c
index 28e7de14db1a..7dcf7fa0d522 100644
--- a/drivers/misc/rk628/rk628_rgb.c
+++ b/drivers/misc/rk628/rk628_rgb.c
@@ -297,7 +297,8 @@ static void rk628_bt1120_decoder_enable(struct rk628 *rk628)
 	 * so that the deviation between the actual clk and the required clk
 	 * frequency is not significant.
 	 */
-	dec_clk_rate = rk628_cru_clk_set_rate(rk628, CGU_BT1120DEC, mode->clock * 1000);
+	rk628_cru_clk_set_rate(rk628, CGU_BT1120DEC, mode->clock * 1000);
+	dec_clk_rate = rk628_cru_clk_get_rate(rk628, CGU_BT1120DEC);
 	if (dec_clk_rate < mode->clock * 1000)
 		rk628_cru_clk_set_rate(rk628, CGU_BT1120DEC, mode->clock * 1020);