From 7e8ad67e3a5ab4d0ebf21d32ea62a2ef69794d4b Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 10 Aug 2018 09:53:33 +0800 Subject: [PATCH] pinctrl: rockchip: Disable GPIO_INTEN bit while gpio irq type setting If the gpio IRQ type changes, it is possible to accidentally trigger an interrupt, such as when the input is high, changed from level to rise edge. For now, the best way to do this is to disable the INTEN bit first, then configure the type to stagger this period of time. Change-Id: I71351b9ed6f7920958c7451c2e51ab5f699875d1 Signed-off-by: David Wu --- drivers/pinctrl/pinctrl-rockchip.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 7dc006677c7e..3af7ea066273 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3466,6 +3466,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) u32 polarity; u32 level; u32 data; + u32 inten; unsigned long flags; int ret; @@ -3536,8 +3537,19 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) return -EINVAL; } + /* + * Accroding to the steps of gpio interrupt, write GPIO_INTEN[x] as + * 1 to enable GPIO’s interrupt should be done after the level and + * polarity configured. + */ + + inten = readl_relaxed(gc->reg_base + GPIO_INTEN); + inten &= ~mask; + writel_relaxed(inten, gc->reg_base + GPIO_INTEN); writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); + inten |= mask; + writel_relaxed(inten, gc->reg_base + GPIO_INTEN); irq_gc_unlock(gc); raw_spin_unlock_irqrestore(&bank->slock, flags);