From 7ef4b6eef9694b23457b24f1d69342ad074bbaa2 Mon Sep 17 00:00:00 2001 From: Zheng Yang Date: Tue, 5 Dec 2017 18:39:47 +0800 Subject: [PATCH] drm: bridge: dw-hdmi: fix VP_PR_CD pixel repetition factor configuration The configured value sets H13T PHY PLL to multiply pixel clock by the factor in order to obtain the desired repetition clock. For the CEA modes some are already defined with pixel repetition in the input video. So for CEA modes this shall be always 0. Change-Id: Iea4a00247f25c134dbd67ba77c00eb4393622385 Signed-off-by: Zheng Yang --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 20df42edbb8e..a0e2ce12e95c 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1217,11 +1217,8 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi) } /* set the packetizer registers */ - val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & - HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | - ((hdmi_data->pix_repet_factor << - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); + val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & + HDMI_VP_PR_CD_COLOR_DEPTH_MASK; hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,