From 8133d7dca66803e49e83bb153e8ae28ea14d52a7 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Tue, 27 Jul 2021 19:48:40 +0800 Subject: [PATCH] drivers: rkflash: Add some delay after DMA finish When internal DMA ready, the last spare data may still in fifo. Change-Id: I1cf670d2008ea62b67b517641e31386fd0877417 Signed-off-by: Jon Lin --- drivers/rkflash/nandc.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/rkflash/nandc.c b/drivers/rkflash/nandc.c index 69e3b0ed5598..efeeede068b9 100644 --- a/drivers/rkflash/nandc.c +++ b/drivers/rkflash/nandc.c @@ -323,26 +323,29 @@ static void nandc_xfer_done(void) do { fl_reg.d32 = nandc_readl(NANDC_V9_FLCTL); stat_reg.d32 = nandc_readl(NANDC_V9_MTRANS_STAT); + usleep_range(20, 30); } while (stat_reg.V9.mtrans_cnt < fl_reg.V9.page_num || fl_reg.V9.tr_rdy == 0); + udelay(5); if (master.mapped) { rknandc_dma_unmap_single((u64)master.page_phy, - fl_reg.V6.page_num * 1024, + fl_reg.V9.page_num * 1024, 0); rknandc_dma_unmap_single((u64)master.spare_phy, - fl_reg.V6.page_num * 64, + fl_reg.V9.page_num * 64, 0); } } else { do { fl_reg.d32 = nandc_readl(NANDC_V9_FLCTL); + usleep_range(20, 30); } while (fl_reg.V9.tr_rdy == 0); if (master.mapped) { rknandc_dma_unmap_single((u64)master.page_phy, - fl_reg.V6.page_num * 1024, + fl_reg.V9.page_num * 1024, 1); rknandc_dma_unmap_single((u64)master.spare_phy, - fl_reg.V6.page_num * 64, + fl_reg.V9.page_num * 64, 1); } } @@ -355,6 +358,7 @@ static void nandc_xfer_done(void) do { fl_reg.d32 = nandc_readl(NANDC_FLCTL); stat_reg.d32 = nandc_readl(NANDC_MTRANS_STAT); + usleep_range(20, 30); } while (stat_reg.V6.mtrans_cnt < fl_reg.V6.page_num || fl_reg.V6.tr_rdy == 0); @@ -371,6 +375,7 @@ static void nandc_xfer_done(void) } else { do { fl_reg.d32 = nandc_readl(NANDC_FLCTL); + usleep_range(20, 30); } while (fl_reg.V6.tr_rdy == 0); if (master.mapped) { rknandc_dma_unmap_single(