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ARM: TC2: basic PM support
Signed-off-by: Nicolas Pitre <nico@linaro.org>
This commit is contained in:
Nicolas Pitre
committed by
Jon Medhurst
Jon Medhurst
parent
f8c889662f
commit
81543a9102
@@ -71,4 +71,12 @@ config ARCH_VEXPRESS_TC2_PM
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config ARCH_VEXPRESS_CA9X4
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bool "Versatile Express Cortex-A9x4 tile"
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config ARCH_VEXPRESS_TC2
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bool "TC2 cluster management"
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depends on MCPM
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select ARM_SPC
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select ARM_CCI
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help
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Support for CPU and cluster power management on TC2.
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endmenu
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@@ -6,6 +6,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
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obj-y := v2m.o
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obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
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obj-$(CONFIG_ARCH_VEXPRESS_TC2) += tc2_pm.o tc2_pm_setup.o
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obj-$(CONFIG_SMP) += platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += cpuidle-tc2.o hotplug-asm.o tc2-sleep.o
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234
arch/arm/mach-vexpress/tc2_pm.c
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234
arch/arm/mach-vexpress/tc2_pm.c
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@@ -0,0 +1,234 @@
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/*
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* arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
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*
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* Created by: Nicolas Pitre, October 2012
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* Copyright: (C) 2012 Linaro Limited
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*
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* Some portions of this file were originally written by Achin Gupta
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* Copyright: (C) 2012 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <asm/mcpm.h>
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#include <asm/proc-fns.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/cp15.h>
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#include <mach/motherboard.h>
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#include <linux/vexpress.h>
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#include <linux/arm-cci.h>
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/*
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* We can't use regular spinlocks. In the switcher case, it is possible
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* for an outbound CPU to call power_down() after its inbound counterpart
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* is already live using the same logical CPU number which trips lockdep
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* debugging.
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*/
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static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
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static int tc2_pm_use_count[3][2];
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static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster)
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{
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= 2 || cpu >= vexpress_spc_get_nb_cpus(cluster))
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return -EINVAL;
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/*
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* Since this is called with IRQs enabled, and no arch_spin_lock_irq
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* variant exists, we need to disable IRQs manually here.
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*/
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local_irq_disable();
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arch_spin_lock(&tc2_pm_lock);
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if (!tc2_pm_use_count[0][cluster] &&
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!tc2_pm_use_count[1][cluster] &&
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!tc2_pm_use_count[2][cluster])
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vexpress_spc_powerdown_enable(cluster, 0);
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tc2_pm_use_count[cpu][cluster]++;
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if (tc2_pm_use_count[cpu][cluster] == 1) {
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vexpress_spc_write_bxaddr_reg(cluster, cpu,
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virt_to_phys(mcpm_entry_point));
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vexpress_spc_set_cpu_wakeup_irq(cpu, cluster, 1);
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} else if (tc2_pm_use_count[cpu][cluster] != 2) {
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/*
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* The only possible values are:
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* 0 = CPU down
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* 1 = CPU (still) up
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* 2 = CPU requested to be up before it had a chance
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* to actually make itself down.
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* Any other value is a bug.
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*/
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BUG();
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}
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arch_spin_unlock(&tc2_pm_lock);
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local_irq_enable();
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return 0;
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}
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static void tc2_pm_power_down(void)
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{
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unsigned int mpidr, cpu, cluster;
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bool last_man = false, skip_wfi = false;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= 2 || cpu >= vexpress_spc_get_nb_cpus(cluster));
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__mcpm_cpu_going_down(cpu, cluster);
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arch_spin_lock(&tc2_pm_lock);
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BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
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tc2_pm_use_count[cpu][cluster]--;
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if (tc2_pm_use_count[cpu][cluster] == 0) {
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vexpress_spc_set_cpu_wakeup_irq(cpu, cluster, 1);
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if (!tc2_pm_use_count[0][cluster] &&
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!tc2_pm_use_count[1][cluster] &&
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!tc2_pm_use_count[2][cluster]) {
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vexpress_spc_powerdown_enable(cluster, 1);
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vexpress_spc_set_global_wakeup_intr(1);
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last_man = true;
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}
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} else if (tc2_pm_use_count[cpu][cluster] == 1) {
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/*
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* A power_up request went ahead of us.
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* Even if we do not want to shut this CPU down,
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* the caller expects a certain state as if the WFI
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* was aborted. So let's continue with cache cleaning.
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*/
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skip_wfi = true;
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} else
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BUG();
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if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
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arch_spin_unlock(&tc2_pm_lock);
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set_cr(get_cr() & ~CR_C);
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flush_cache_all();
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asm volatile ("clrex");
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set_auxcr(get_auxcr() & ~(1 << 6));
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disable_cci(cluster);
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/*
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* Ensure that both C & I bits are disabled in the SCTLR
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* before disabling ACE snoops. This ensures that no
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* coherency traffic will originate from this cpu after
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* ACE snoops are turned off.
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*/
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cpu_proc_fin();
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__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
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} else {
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/*
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* If last man then undo any setup done previously.
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*/
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if (last_man) {
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vexpress_spc_powerdown_enable(cluster, 0);
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vexpress_spc_set_global_wakeup_intr(0);
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}
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arch_spin_unlock(&tc2_pm_lock);
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set_cr(get_cr() & ~CR_C);
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flush_cache_louis();
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asm volatile ("clrex");
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set_auxcr(get_auxcr() & ~(1 << 6));
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}
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__mcpm_cpu_down(cpu, cluster);
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/* Now we are prepared for power-down, do it: */
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if (!skip_wfi)
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wfi();
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/* Not dead at this point? Let our caller cope. */
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}
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static void tc2_pm_powered_up(void)
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{
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unsigned int mpidr, cpu, cluster;
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unsigned long flags;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= 2 || cpu >= vexpress_spc_get_nb_cpus(cluster));
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local_irq_save(flags);
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arch_spin_lock(&tc2_pm_lock);
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if (!tc2_pm_use_count[0][cluster] &&
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!tc2_pm_use_count[1][cluster] &&
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!tc2_pm_use_count[2][cluster]) {
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vexpress_spc_powerdown_enable(cluster, 0);
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vexpress_spc_set_global_wakeup_intr(0);
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}
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if (!tc2_pm_use_count[cpu][cluster])
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tc2_pm_use_count[cpu][cluster] = 1;
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vexpress_spc_set_cpu_wakeup_irq(cpu, cluster, 0);
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vexpress_spc_write_bxaddr_reg(cluster, cpu, 0);
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arch_spin_unlock(&tc2_pm_lock);
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local_irq_restore(flags);
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}
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static const struct mcpm_platform_ops tc2_pm_power_ops = {
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.power_up = tc2_pm_power_up,
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.power_down = tc2_pm_power_down,
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.powered_up = tc2_pm_powered_up,
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};
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static void __init tc2_pm_usage_count_init(void)
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{
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unsigned int mpidr, cpu, cluster;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cpu >= 3 || cluster >= 2);
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tc2_pm_use_count[cpu][cluster] = 1;
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}
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extern void tc2_pm_power_up_setup(unsigned int affinity_level);
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static int __init tc2_pm_init(void)
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{
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int ret;
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if (!vexpress_spc_check_loaded())
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return -ENODEV;
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tc2_pm_usage_count_init();
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ret = mcpm_platform_register(&tc2_pm_power_ops);
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if (!ret)
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ret = mcpm_sync_init(tc2_pm_power_up_setup);
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if (!ret)
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pr_info("TC2 power management initialized\n");
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return ret;
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}
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early_initcall(tc2_pm_init);
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88
arch/arm/mach-vexpress/tc2_pm_setup.S
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88
arch/arm/mach-vexpress/tc2_pm_setup.S
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@@ -0,0 +1,88 @@
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/*
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* arch/arm/include/asm/tc2_pm_setup.S
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*
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* Created by: Nicolas Pitre, October 2012
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( (based on dcscb_setup.S by Dave Martin)
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* Copyright: (C) 2012 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/mcpm.h>
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#define SPC_PHYS_BASE 0x7FFF0000
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#define SNOOP_CTL_A15 0x404
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#define SNOOP_CTL_A7 0x504
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#define A15_SNOOP_MASK (0x3 << 7)
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#define A7_SNOOP_MASK (0x1 << 13)
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#define A15_BX_ADDR0 0xB68
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#define CCI_PHYS_BASE 0x2c090000
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#define SLAVE_SNOOPCTL_OFFSET 0
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#define SNOOPCTL_SNOOP_ENABLE (1 << 0)
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#define SNOOPCTL_DVM_ENABLE (1 << 1)
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#define CCI_STATUS_OFFSET 0xc
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#define STATUS_CHANGE_PENDING (1 << 0)
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#define CCI_SLAVE_OFFSET(n) (0x1000 + 0x1000 * (n))
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#define CCI_SLAVE_A15 3
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#define CCI_SLAVE_A7 4
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#define CCI_A15_OFFSET CCI_SLAVE_OFFSET(CCI_SLAVE_A15)
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#define CCI_A7_OFFSET CCI_SLAVE_OFFSET(CCI_SLAVE_A7)
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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* The ACTLR SMP bit does not need to be set here, because cpu_resume()
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* already restores that.
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*/
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ENTRY(tc2_pm_power_up_setup)
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cmp r0, #0
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beq 2f
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@ Enable CCI snoops
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mrc p15, 0, r0, c0, c0, 5 @ MPIDR
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ubfx r0, r0, #8, #4 @ cluster
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ldr r3, =CCI_PHYS_BASE + CCI_A15_OFFSET
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cmp r0, #0 @ A15 cluster?
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addne r3, r3, #CCI_A7_OFFSET - CCI_A15_OFFSET
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@ r3 now points to the correct CCI slave register block
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ldr r0, [r3, #SLAVE_SNOOPCTL_OFFSET]
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orr r0, r0, #SNOOPCTL_SNOOP_ENABLE | SNOOPCTL_DVM_ENABLE
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str r0, [r3, #SLAVE_SNOOPCTL_OFFSET] @ enable CCI snoops
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@ Wait for snoop control change to complete:
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ldr r3, =CCI_PHYS_BASE
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1: ldr r0, [r3, #CCI_STATUS_OFFSET]
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tst r0, #STATUS_CHANGE_PENDING
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bne 1b
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bx lr
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2: @ Clear the BX addr register
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ldr r3, =SPC_PHYS_BASE + A15_BX_ADDR0
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mrc p15, 0, r0, c0, c0, 5 @ MPIDR
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ubfx r1, r0, #8, #4 @ cluster
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ubfx r0, r0, #0, #4 @ cpu
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add r3, r3, r1, lsl #4
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mov r1, #0
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str r1, [r3, r0, lsl #2]
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dsb
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bx lr
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ENDPROC(tc2_pm_power_up_setup)
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