diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 082da7004539..862a31d8a1d0 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -323,7 +323,7 @@ config ARCH_ROCKCHIP_ODROID_COMMON bool config ARCH_ROCKCHIP_ODROIDM1 - bool "Hardkernel's ODROID-M1 Single Board Computer" + bool "Hardkernel's ODROID-M1/M1S Single Board Computer" select ARCH_ROCKCHIP_ODROID_COMMON help This enables support for the board ODROID-M1 of Hardkernel diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index d8ee4545e9f5..afd6b68a3115 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -215,5 +215,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-rk806-single-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-odroid-m1s.dtb subdir-$(CONFIG_ARCH_ROCKCHIP_ODROIDM1) += overlays/odroidm1 diff --git a/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts b/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts new file mode 100644 index 000000000000..1075d1dd4795 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts @@ -0,0 +1,1250 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Hardkernel Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Hardkernel ODROID-M1S"; + + aliases { + serial0 = &uart6; + serial1 = &uart0; + serial6 = &uart1; + spi0 = &spi1; + spi1 = &spi0; + i2c0 = &i2c3; + i2c3 = &i2c0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + status = "disabled"; + + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip-hdmi0"; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip-rk809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; //HP_HOOK + }; + + vcc_sys: vcc-5v { + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + }; + + vcc5v0_usb3: vcc5v0-usb3-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb3_en>; + regulator-name = "vcc5v0_usb3"; + regulator-always-on; + regulator-boot-on; + }; + + pcie20_3v3: pcie20-3v3-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_3v3_en>; + regulator-name = "pcie20_3v3"; + regulator-always-on; + regulator-boot-on; + }; + + lcd_pwren: lcd-pwren { + compatible = "regulator-fixed"; + regulator-name = "lcd_pwren"; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + }; + + + leds { + compatible = "gpio-leds"; + status = "okay"; + + power_led: power { + gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + work_led: work { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&threshold { + temperature = <60000>; +}; + +&dfi { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&i2c0 { + status = "okay"; + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_ddr: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0-A3 */ + "", "", "", "", + /* GPIO0_A4-A7 */ + "", "", "", "", + + /* GPIO0_B0-B3 */ + "", "", "", "PIN_28", + /* GPIO0_B4-B7 */ + "PIN_27", "PIN_33", "PIN_7", "", + + /* GPIO0_C0-C3 */ + "PIN_11", "PIN_13", "PIN_15", "", + /* GPIO0_C4-C7 */ + "", "", "", "", + + /* GPIO0_D0-D3 */ + "", "", "", "", + /* GPIO0_D4-D7 */ + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0-A3 */ + "", "", "", "", + /* GPIO1_A4-A7 */ + "", "", "", "", + + /* GPIO1_B0-B3 */ + "", "", "", "", + /* GPIO1_B4-B7 */ + "", "", "", "", + + /* GPIO1_C0-C3 */ + "", "", "", "", + /* GPIO1_C4-C7 */ + "", "", "", "", + + /* GPIO1_D0-D3 */ + "", "", "", "", + /* GPIO1_D4-D7 */ + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0-A3 */ + "", "", "", "PIN_10", + /* GPIO2_A4-A7 */ + "PIN_8", "PINN_35", "PIN_36", "PIN_12", + + /* GPIO2_B0-B3 */ + "PIN_22", "PIN_26", "PIN_32", "", + /* GPIO2_B4-B7 */ + "", "PIN_16", "PIN_18", "PIN_31", + + /* GPIO2_C0-C3 */ + "PIN_29", "", "", "", + /* GPIO2_C4-C7 */ + "", "", "", "", + + /* GPIO2_D0-D3 */ + "", "", "", "", + /* GPIO2_D4-D7 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0-A3 */ + "", "PIN_24", "", "", + /* GPIO3_A4-A7 */ + "", "", "", "", + + /* GPIO3_B0-B3 */ + "", "", "", "EXTPIN_13", + /* GPIO3_B4-B7 */ + "EXTPIN_14", "PIN_5", "PIN_3", "", + + /* GPIO3_C0-C3 */ + "", "PIN_19", "PIN_21", "PIN_23", + /* GPIO3_C4-C7 */ + "EXTPIN_11", "EXTPIN_12", "", "", + + /* GPIO3_D0-D3 */ + "", "", "", "", + /* GPIO3_D4-D7 */ + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0-A3 */ + "", "", "", "", + /* GPIO4_A4-A7 */ + "", "", "", "", + + /* GPIO4_B0-B3 */ + "", "", "", "", + /* GPIO4_B4-B7 */ + "", "", "", "", + + /* GPIO4_C0-C3 */ + "", "", "", "", + /* GPIO4_C4-C7 */ + "", "", "", "", + + /* GPIO4_D0-D3 */ + "", "", "", "", + /* GPIO4_D4-D7 */ + "", "", "", ""; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; +}; + +&i2c3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; +}; + +&i2c4 { + status = "disabled"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm1 { + status = "disabled"; + pinctrl-0 = <&pwm1m1_pins>; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; +}; + +&rknpu_mmu { + status = "disabled"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + pinctrl-0 = <&emmc_bus8 + &emmc_clk + &emmc_cmd + &emmc_datastrobe + &emmc_rstnout>; + pinctrl-names = "default"; + + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + mmc-hs200-1_8v; + cap-mmc-hw-reset; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1m1_pins>; + pinctrl-1 = <&spi1m1_pins_hs>; + num_chipselect = <1>; + + cs-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; +}; + +&uart6 { + dma-names = "tx", "rx"; + pinctrl-1 = <&uart6m0_xfer &uart6m0_ctsn &uart6m0_rtsn>; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + + tx_delay = <0x4f>; + rx_delay = <0x2d>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb3>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; + pinctrl-names = "default"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie20_3v3>; + pinctrl-0 = <&pcie20m2_pins>; + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_CENTER_OFF + | RKPM_SLP_HW_PLLS_OFF + | RKPM_SLP_PMUALIVE_32K + | RKPM_SLP_32K_PVTM + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; +}; + +&pinctrl { + can_pins { + mcp2515_int_pins: mcp2515_int_pins { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1m1_miim: gmac1m1-miim { + rockchip,pins = + /* gmac1_mdcm1 */ + <4 RK_PB6 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_mdiom1 */ + <4 RK_PB7 3 &pcfg_pull_none_drv_level_15>; + }; + + /omit-if-no-ref/ + gmac1m1_clkinout: gmac1m1-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm1 */ + <4 RK_PC1 3 &pcfg_pull_none_drv_level_15>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_bus2: gmac1m1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m1 */ + <4 RK_PA7 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_rxd1m1 */ + <4 RK_PB0 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_rxdvcrsm1 */ + <4 RK_PB1 3 &pcfg_pull_none_drv_level_15>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2: gmac1m1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none_drv_level_15>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_15>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_15>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_ctl: led-ctl { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + lcd { + lcd_pwr_en: lcd-pwr-en { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_gpios: touch-gpios { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + }; + + pcie { + pcie20_3v3_en: pcie20-3v3-en { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb3_en: vcc5v0-usb3-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tc358762 { + vcc_mipi_en: vcc-mipi-en { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&dsi0 { + status = "disabled"; + + connect = <&vp1_out_dsi0>; + + dsi0_panel: panel@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-property/ disable-delay-ms; + /delete-property/ enable-delay-ms; + /delete-property/ panel-exit-sequence; + /delete-property/ panel-init-sequence; + /delete-property/ reset-delay-ms; + /delete-property/ prepare-delay-ms; + /delete-property/ unprepare-delay-ms; + + status = "disabled"; + + reg = <0>; + + backlight = <&backlight>; + power-supply = <&lcd_pwren>; + + reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; diff --git a/arch/arm64/configs/odroidm1_defconfig b/arch/arm64/configs/odroidm1_defconfig index f8609a4bb34a..014b7fd48ab1 100644 --- a/arch/arm64/configs/odroidm1_defconfig +++ b/arch/arm64/configs/odroidm1_defconfig @@ -3874,6 +3874,7 @@ CONFIG_FB_DEFERRED_IO=y # CONFIG_FB_SIMPLE is not set # CONFIG_FB_SSD1307 is not set # CONFIG_FB_SM712 is not set +CONFIG_FB_SH1106=m # end of Frame buffer Devices # diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index 4f02db65dede..619f96da06e5 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig @@ -2236,6 +2236,20 @@ config FB_SM712 called sm712fb. If you want to compile it as a module, say M here and read . +config FB_SH1106 + tristate "Sino Wealth SH1106 framebuffer support" + depends on FB && I2C + depends on OF + depends on GPIOLIB || COMPILE_TEST + select FB_SYS_FOPS + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_DEFERRED_IO + help + This driver implements support for the Sino Wealth SH1106 + OLED controller over I2C. + source "drivers/video/fbdev/omap/Kconfig" source "drivers/video/fbdev/omap2/Kconfig" source "drivers/video/fbdev/mmp/Kconfig" diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile index 477b9624b703..841b7670d882 100644 --- a/drivers/video/fbdev/Makefile +++ b/drivers/video/fbdev/Makefile @@ -129,6 +129,7 @@ obj-$(CONFIG_FB_MX3) += mx3fb.o obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o obj-$(CONFIG_FB_SSD1307) += ssd1307fb.o obj-$(CONFIG_FB_SIMPLE) += simplefb.o +obj-$(CONFIG_FB_SH1106) += sh1106fb.o # the test framebuffer is last obj-$(CONFIG_FB_VIRTUAL) += vfb.o diff --git a/drivers/video/fbdev/sh1106fb.c b/drivers/video/fbdev/sh1106fb.c new file mode 100644 index 000000000000..9c037238eef4 --- /dev/null +++ b/drivers/video/fbdev/sh1106fb.c @@ -0,0 +1,626 @@ +/* + * Driver for the Sino Wealth SSD1307 OLED controller + * + * Copyright 2020 Dongjin Kim + * + * This version is based on : + * linux/drivers/video/fbdevssd1307fb.c -- Solomon SSD1307 OLED controller + * + * Copyright 2012 Free Electrons + * + * Licensed under the GPLv2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SH1106_DATA 0x40 +#define SH1106_COMMAND 0x80 + +#define SH1106_SET_ADDRESS_MODE 0x20 +#define SH1106_SET_ADDRESS_MODE_HORIZONTAL (0x00) +#define SH1106_SET_ADDRESS_MODE_VERTICAL (0x01) +#define SH1106_SET_ADDRESS_MODE_PAGE (0x02) +#define SH1106_SET_COL_RANGE 0x21 +#define SH1106_SET_PAGE_RANGE 0x22 +#define SH1106_CONTRAST 0x81 +#define SH1106_CHARGE_PUMP 0x8d +#define SH1106_SEG_REMAP_ON 0xa1 +#define SH1106_DISPLAY_OFF 0xae +#define SH1106_SET_MULTIPLEX_RATIO 0xa8 +#define SH1106_DISPLAY_ON 0xaf +#define SH1106_START_PAGE_ADDRESS 0xb0 +#define SH1106_SET_DISPLAY_OFFSET 0xd3 +#define SH1106_SET_CLOCK_FREQ 0xd5 +#define SH1106_SET_PRECHARGE_PERIOD 0xd9 +#define SH1106_SET_COM_PINS_CONFIG 0xda +#define SH1106_SET_VCOMH 0xdb + +#define MAX_CONTRAST 255 + +#define REFRESHRATE 20 + +static u_int refreshrate = REFRESHRATE; +module_param(refreshrate, uint, 0); + +static u_int rotate; +module_param(rotate, uint, 0); + +struct sh1106fb_par; + +struct sh1106fb_deviceinfo { + u32 default_vcomh; + u32 default_dclk_div; + u32 default_dclk_frq; + int need_chargepump; +}; + +struct sh1106fb_par { + u32 com_invdir; + u32 com_lrremap; + u32 com_offset; + u32 com_seq; + u32 contrast; + u32 dclk_div; + u32 dclk_frq; + const struct sh1106fb_deviceinfo *device_info; + struct i2c_client *client; + u32 height; + struct fb_info *info; + u32 page_offset; + u32 prechargep1; + u32 prechargep2; + u32 seg_remap; + u32 vcomh; + u32 width; + u32 rotate; +}; + +struct sh1106fb_array { + u8 type; + u8 data[0]; +}; + +static const struct fb_fix_screeninfo sh1106fb_fix = { + .id = "SH1106 OLED", + .type = FB_TYPE_PACKED_PIXELS, + .visual = FB_VISUAL_MONO10, + .xpanstep = 0, + .ypanstep = 0, + .ywrapstep = 0, + .accel = FB_ACCEL_NONE, +}; + +static const struct fb_var_screeninfo sh1106fb_var = { + .bits_per_pixel = 1, +}; + +static struct sh1106fb_array *sh1106fb_alloc_array(u32 len, u8 type) +{ + struct sh1106fb_array *array; + + array = kzalloc(sizeof(struct sh1106fb_array) + len, GFP_KERNEL); + if (!array) + return NULL; + + array->type = type; + + return array; +} + +static int sh1106fb_write_array(struct i2c_client *client, + struct sh1106fb_array *array, u32 len) +{ + int ret; + + len += sizeof(struct sh1106fb_array); + + ret = i2c_master_send(client, (u8 *)array, len); + if (ret != len) { + dev_err(&client->dev, "Couldn't send I2C command.\n"); + return ret; + } + + return 0; +} + +static inline int sh1106fb_write_cmd(struct i2c_client *client, u8 cmd) +{ + struct sh1106fb_array *array; + int ret; + + array = sh1106fb_alloc_array(1, SH1106_COMMAND); + if (!array) + return -ENOMEM; + + array->data[0] = cmd; + + ret = sh1106fb_write_array(client, array, 1); + kfree(array); + + return ret; +} + +static void sh1106fb_update_display(struct sh1106fb_par *par) +{ + struct sh1106fb_array *array; + u8 *vmem = par->info->screen_base; + int i, j, k; + + array = sh1106fb_alloc_array(par->width * par->height / 8, + SH1106_DATA); + if (!array) + return; + + /* + * The screen is divided in pages, each having a height of 8 + * pixels, and the width of the screen. When sending a byte of + * data to the controller, it gives the 8 bits for the current + * column. I.e, the first byte are the 8 bits of the first + * column, then the 8 bits for the second column, etc. + * + * + * Representation of the screen, assuming it is 5 bits + * wide. Each letter-number combination is a bit that controls + * one pixel. + * + * A0 A1 A2 A3 A4 + * B0 B1 B2 B3 B4 + * C0 C1 C2 C3 C4 + * D0 D1 D2 D3 D4 + * E0 E1 E2 E3 E4 + * F0 F1 F2 F3 F4 + * G0 G1 G2 G3 G4 + * H0 H1 H2 H3 H4 + * + * If you want to update this screen, you need to send 5 bytes: + * (1) A0 B0 C0 D0 E0 F0 G0 H0 + * (2) A1 B1 C1 D1 E1 F1 G1 H1 + * (3) A2 B2 C2 D2 E2 F2 G2 H2 + * (4) A3 B3 C3 D3 E3 F3 G3 H3 + * (5) A4 B4 C4 D4 E4 F4 G4 H4 + */ + + if (par->rotate == 0) { + for (i = 0; i < (par->height / 8); i++) { + for (j = 0; j < par->width; j++) { + u32 array_idx = i * par->width + j; + + array->data[array_idx] = 0; + for (k = 0; k < 8; k++) { + u32 page_length = par->width * i; + u32 index = page_length + (par->width * k + j) / 8; + u8 byte = *(vmem + index); + u8 bit = byte & (1 << (j % 8)); + bit = bit >> (j % 8); + array->data[array_idx] |= bit << k; + } + } + } + } else if (par->rotate == 180) { + for (i = 0; i < (par->height / 8); i++) { + for (j = 0; j < par->width; j++) { + u32 array_idx = i * par->width + j; + + array->data[array_idx] = 0; + for (k = 0; k < 8; k++) { + u32 page_length = par->width * (7 - i); + u32 index = page_length + (par->width * (7 - k) + j) / 8; + u8 byte = *(vmem + index); + u8 bit = byte & (1 << (j % 8)); + bit = bit >> (j % 8); + array->data[array_idx] |= bit << k; + } + } + } + } + + sh1106fb_write_array(par->client, array, par->width * par->height / 8); + kfree(array); +} + +static ssize_t sh1106fb_write(struct fb_info *info, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct sh1106fb_par *par = info->par; + unsigned long total_size; + unsigned long p = *ppos; + u8 __iomem *dst; + + total_size = info->fix.smem_len; + + if (p > total_size) + return -EINVAL; + + if (count + p > total_size) + count = total_size - p; + + if (!count) + return -EINVAL; + + dst = (void __force *) (info->screen_base + p); + + if (copy_from_user(dst, buf, count)) + return -EFAULT; + + sh1106fb_update_display(par); + + *ppos += count; + + return count; +} + +static int sh1106fb_blank(int blank_mode, struct fb_info *info) +{ + struct sh1106fb_par *par = info->par; + + if (blank_mode != FB_BLANK_UNBLANK) + return sh1106fb_write_cmd(par->client, SH1106_DISPLAY_OFF); + else + return sh1106fb_write_cmd(par->client, SH1106_DISPLAY_ON); +} + +static void sh1106fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) +{ + struct sh1106fb_par *par = info->par; + sys_fillrect(info, rect); + sh1106fb_update_display(par); +} + +static void sh1106fb_copyarea(struct fb_info *info, const struct fb_copyarea *area) +{ + struct sh1106fb_par *par = info->par; + sys_copyarea(info, area); + sh1106fb_update_display(par); +} + +static void sh1106fb_imageblit(struct fb_info *info, const struct fb_image *image) +{ + struct sh1106fb_par *par = info->par; + sys_imageblit(info, image); + sh1106fb_update_display(par); +} + +static struct fb_ops sh1106fb_ops = { + .owner = THIS_MODULE, + .fb_read = fb_sys_read, + .fb_write = sh1106fb_write, + .fb_blank = sh1106fb_blank, + .fb_fillrect = sh1106fb_fillrect, + .fb_copyarea = sh1106fb_copyarea, + .fb_imageblit = sh1106fb_imageblit, +}; + +static void sh1106fb_deferred_io(struct fb_info *info, + struct list_head *pagelist) +{ + sh1106fb_update_display(info->par); +} + +static int sh1106fb_init(struct sh1106fb_par *par) +{ + int ret; + u32 precharge, dclk, com_invdir, compins; + + /* Set initial contrast */ + ret = sh1106fb_write_cmd(par->client, SH1106_CONTRAST); + if (ret < 0) + return ret; + + ret = sh1106fb_write_cmd(par->client, par->contrast); + if (ret < 0) + return ret; + + /* Set segment re-map */ + if (par->seg_remap) { + ret = sh1106fb_write_cmd(par->client, SH1106_SEG_REMAP_ON); + if (ret < 0) + return ret; + }; + + /* Set COM direction */ + com_invdir = 0xc0 | (par->com_invdir & 0x1) << 3; + ret = sh1106fb_write_cmd(par->client, com_invdir); + if (ret < 0) + return ret; + + /* Set multiplex ratio value */ + ret = sh1106fb_write_cmd(par->client, SH1106_SET_MULTIPLEX_RATIO); + if (ret < 0) + return ret; + + ret = sh1106fb_write_cmd(par->client, par->height - 1); + if (ret < 0) + return ret; + + /* set display offset value */ + ret = sh1106fb_write_cmd(par->client, SH1106_SET_DISPLAY_OFFSET); + if (ret < 0) + return ret; + + ret = sh1106fb_write_cmd(par->client, par->com_offset); + if (ret < 0) + return ret; + + /* Set clock frequency */ + ret = sh1106fb_write_cmd(par->client, SH1106_SET_CLOCK_FREQ); + if (ret < 0) + return ret; + + dclk = ((par->dclk_div - 1) & 0xf) | (par->dclk_frq & 0xf) << 4; + ret = sh1106fb_write_cmd(par->client, dclk); + if (ret < 0) + return ret; + + /* Set precharge period in number of ticks from the internal clock */ + ret = sh1106fb_write_cmd(par->client, SH1106_SET_PRECHARGE_PERIOD); + if (ret < 0) + return ret; + + precharge = (par->prechargep1 & 0xf) | (par->prechargep2 & 0xf) << 4; + ret = sh1106fb_write_cmd(par->client, precharge); + if (ret < 0) + return ret; + + /* Set COM pins configuration */ + ret = sh1106fb_write_cmd(par->client, SH1106_SET_COM_PINS_CONFIG); + if (ret < 0) + return ret; + + compins = 0x02 | !(par->com_seq & 0x1) << 4 + | (par->com_lrremap & 0x1) << 5; + ret = sh1106fb_write_cmd(par->client, compins); + if (ret < 0) + return ret; + + /* Set VCOMH */ + ret = sh1106fb_write_cmd(par->client, SH1106_SET_VCOMH); + if (ret < 0) + return ret; + + ret = sh1106fb_write_cmd(par->client, par->vcomh); + if (ret < 0) + return ret; + + /* Turn on the DC-DC Charge Pump */ + ret = sh1106fb_write_cmd(par->client, SH1106_CHARGE_PUMP); + if (ret < 0) + return ret; + + ret = sh1106fb_write_cmd(par->client, + BIT(4) | (par->device_info->need_chargepump ? BIT(2) : 0)); + if (ret < 0) + return ret; + + /* Switch to horizontal addressing mode */ + ret = sh1106fb_write_cmd(par->client, SH1106_SET_ADDRESS_MODE); + if (ret < 0) + return ret; + + ret = sh1106fb_write_cmd(par->client, + SH1106_SET_ADDRESS_MODE_HORIZONTAL); + if (ret < 0) + return ret; + + /* Set column range */ + ret = sh1106fb_write_cmd(par->client, SH1106_SET_COL_RANGE); + if (ret < 0) + return ret; + + ret = sh1106fb_write_cmd(par->client, 0x0); + if (ret < 0) + return ret; + + ret = sh1106fb_write_cmd(par->client, par->width - 1); + if (ret < 0) + return ret; + + /* Set page range */ + ret = sh1106fb_write_cmd(par->client, SH1106_SET_PAGE_RANGE); + if (ret < 0) + return ret; + + ret = sh1106fb_write_cmd(par->client, par->page_offset); + if (ret < 0) + return ret; + + ret = sh1106fb_write_cmd(par->client, + par->page_offset + (par->height / 8) - 1); + if (ret < 0) + return ret; + + /* Turn on the display */ + ret = sh1106fb_write_cmd(par->client, SH1106_DISPLAY_ON); + if (ret < 0) + return ret; + + return 0; +} + +static struct sh1106fb_deviceinfo sh1106fb_sh1106_deviceinfo = { + .default_vcomh = 0x40, + .default_dclk_div = 2, + .default_dclk_frq = 12, + .need_chargepump = 1, +}; + +static const struct of_device_id sh1106fb_of_match[] = { + { + .compatible = "sinowealth,sh1106-i2c", + .data = (void *)&sh1106fb_sh1106_deviceinfo, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, sh1106fb_of_match); + +static int sh1106fb_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct fb_info *info; + struct device_node *node = client->dev.of_node; + struct fb_deferred_io *sh1106fb_defio; + u32 vmem_size; + struct sh1106fb_par *par; + u8 *vmem; + int ret; + + if (!node) { + dev_err(&client->dev, "No device tree data found!\n"); + return -EINVAL; + } + + info = framebuffer_alloc(sizeof(struct sh1106fb_par), &client->dev); + if (!info) { + dev_err(&client->dev, "Couldn't allocate framebuffer.\n"); + return -ENOMEM; + } + + par = info->par; + par->info = info; + par->client = client; + + par->device_info = of_device_get_match_data(&client->dev); + + if (of_property_read_u32(node, "width", &par->width)) + par->width = 96; + + if (of_property_read_u32(node, "height", &par->height)) + par->height = 16; + + if (of_property_read_u32(node, "page-offset", &par->page_offset)) + par->page_offset = 0; + + if (of_property_read_u32(node, "com-offset", &par->com_offset)) + par->com_offset = 0; + + if (of_property_read_u32(node, "prechargep1", &par->prechargep1)) + par->prechargep1 = 2; + + if (of_property_read_u32(node, "prechargep2", &par->prechargep2)) + par->prechargep2 = 2; + + if (of_property_read_u32(node, "rotate", &par->rotate)) + par->rotate = rotate; + + par->seg_remap = !of_property_read_bool(node, "segment-no-remap"); + par->com_seq = of_property_read_bool(node, "com-seq"); + par->com_lrremap = of_property_read_bool(node, "com-lrremap"); + par->com_invdir = of_property_read_bool(node, "com-invdir"); + + par->contrast = 127; + par->vcomh = par->device_info->default_vcomh; + + /* Setup display timing */ + par->dclk_div = par->device_info->default_dclk_div; + par->dclk_frq = par->device_info->default_dclk_frq; + + vmem_size = par->width * par->height / 8; + + vmem = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, + get_order(vmem_size)); + if (!vmem) { + dev_err(&client->dev, "Couldn't allocate graphical memory.\n"); + ret = -ENOMEM; + goto fb_alloc_error; + } + + sh1106fb_defio = devm_kzalloc(&client->dev, sizeof(struct fb_deferred_io), GFP_KERNEL); + if (!sh1106fb_defio) { + dev_err(&client->dev, "Couldn't allocate deferred io.\n"); + ret = -ENOMEM; + goto fb_alloc_error; + } + + sh1106fb_defio->delay = HZ / refreshrate; + sh1106fb_defio->deferred_io = sh1106fb_deferred_io; + + info->fbops = &sh1106fb_ops; + info->fix = sh1106fb_fix; + info->fix.line_length = par->width / 8; + info->fbdefio = sh1106fb_defio; + + info->var = sh1106fb_var; + info->var.xres = par->width; + info->var.xres_virtual = par->width; + info->var.yres = par->height; + info->var.yres_virtual = par->height; + + info->var.red.length = 1; + info->var.red.offset = 0; + info->var.green.length = 1; + info->var.green.offset = 0; + info->var.blue.length = 1; + info->var.blue.offset = 0; + + info->screen_base = (u8 __force __iomem *)vmem; + info->fix.smem_start = __pa(vmem); + info->fix.smem_len = vmem_size; + + fb_deferred_io_init(info); + + i2c_set_clientdata(client, info); + + ret = sh1106fb_init(par); + if (ret) + goto reset_oled_error; + + ret = register_framebuffer(info); + if (ret) { + dev_err(&client->dev, "Couldn't register the framebuffer\n"); + goto panel_init_error; + } + + dev_info(&client->dev, "fb%d: %s framebuffer device registered, using %d bytes of video memory\n", info->node, info->fix.id, vmem_size); + + return 0; + +panel_init_error: +reset_oled_error: + fb_deferred_io_cleanup(info); +fb_alloc_error: + framebuffer_release(info); + return ret; +} + +static int sh1106fb_remove(struct i2c_client *client) +{ + struct fb_info *info = i2c_get_clientdata(client); + struct sh1106fb_par *par = info->par; + + sh1106fb_write_cmd(par->client, SH1106_DISPLAY_OFF); + + unregister_framebuffer(info); + fb_deferred_io_cleanup(info); + __free_pages(__va(info->fix.smem_start), get_order(info->fix.smem_len)); + framebuffer_release(info); + + return 0; +} + +static const struct i2c_device_id sh1106fb_i2c_id[] = { + { "sh1106fb", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, sh1106fb_i2c_id); + +static struct i2c_driver sh1106fb_driver = { + .probe = sh1106fb_probe, + .remove = sh1106fb_remove, + .id_table = sh1106fb_i2c_id, + .driver = { + .name = "sh1106fb", + .of_match_table = sh1106fb_of_match, + }, +}; + +module_i2c_driver(sh1106fb_driver); + +MODULE_DESCRIPTION("FB driver for the Sino Wealth SH1106 OLED controller"); +MODULE_AUTHOR("Dongjin Kim "); +MODULE_LICENSE("GPL");