From 8177616addbb4ed84ef4d0c84b23d8cfbf4d0682 Mon Sep 17 00:00:00 2001 From: William Wu Date: Mon, 29 Jan 2018 20:40:44 +0800 Subject: [PATCH] usb: dwc3: rockchip: reduce the delay of controller reset The dwc3 controller gets clocks from the pipe_clk(125MHz), utmi_clk(30MHz) and aclk(300MHz). It requires to wait several clock cycles for the reset controller operation done. The minimum clock is utmi_clk 30MHz, and suppose that 10 clock cycles are required, it's about 0.33us. So delay 1us is enough. Change-Id: I6980b92249356efc20c1f537aa3c83f91561cdd4 Signed-off-by: William Wu --- drivers/usb/dwc3/dwc3-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-rockchip.c b/drivers/usb/dwc3/dwc3-rockchip.c index c018b2007922..e313a0755f7f 100644 --- a/drivers/usb/dwc3/dwc3-rockchip.c +++ b/drivers/usb/dwc3/dwc3-rockchip.c @@ -439,7 +439,7 @@ static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work) */ if (!rockchip->skip_suspend) { reset_control_assert(rockchip->otg_rst); - usleep_range(1000, 1200); + udelay(1); reset_control_deassert(rockchip->otg_rst); pm_runtime_get_sync(rockchip->dev); @@ -487,7 +487,7 @@ static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work) * registers while the reset is asserted, with unknown impact. */ reset_control_assert(rockchip->otg_rst); - usleep_range(1000, 1200); + udelay(1); reset_control_deassert(rockchip->otg_rst); /*