From 8247f021eea30cee0cd7abd6c16622bd011f673a Mon Sep 17 00:00:00 2001
From: Jianing Ren <jianing.ren@rock-chips.com>
Date: Mon, 20 Jan 2020 17:01:19 +0800
Subject: [PATCH] ARM: dts: rockchip: add usb & phy nodes for rv1126

Change-Id: I5ec5b401fc0d640d3e0b1791d635fab3ea2b7ff2
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
---
 arch/arm/boot/dts/rv1126.dtsi | 100 ++++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
index b6b3322a60d2..855cd1545671 100644
--- a/arch/arm/boot/dts/rv1126.dtsi
+++ b/arch/arm/boot/dts/rv1126.dtsi
@@ -634,6 +634,49 @@
 			<&pmucru CLK_OSC0_DIV32K>;
 	};
 
+	u2phy0: usb2-phy@ff4c0000 {
+		compatible = "rockchip,rv1126-usb2phy";
+		reg = <0xff4c0000 0x8000>;
+		clocks = <&cru CLK_USBPHY_OTG_REF>, <&cru PCLK_USBPHY_OTG>;
+		clock-names = "phyclk", "pclk";
+		resets = <&cru SRST_USBPHYPOR_OTG>, <&cru SRST_USBPHY_OTG_P>;
+		reset-names = "u2phy", "u2phy-apb";
+		#clock-cells = <0>;
+		clock-output-names = "usb480m_phy0";
+		status = "disabled";
+
+		u2phy_otg: otg-port {
+			#phy-cells = <0>;
+			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "otg-bvalid", "otg-id",
+					  "linestate", "disconnect";
+			status = "disabled";
+		};
+	};
+
+	u2phy1: usb2-phy@ff4c8000 {
+		compatible = "rockchip,rv1126-usb2phy";
+		reg = <0xff4c8000 0x8000>;
+		clocks = <&cru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>;
+		clock-names = "phyclk", "pclk";
+		resets = <&cru SRST_USBPHYPOR_HOST>, <&cru SRST_USBPHY_HOST_P>;
+		reset-names = "u2phy", "u2phy-apb";
+		#clock-cells = <0>;
+		clock-output-names = "usb480m_phy1";
+		status = "disabled";
+
+		u2phy_host: host-port {
+			#phy-cells = <0>;
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "linestate", "disconnect";
+			status = "disabled";
+		};
+	};
+
 	mipi_dphy: mipi-dphy@ff4d0000 {
 		compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk1808-mipi-dphy";
 		reg = <0xff4d0000 0x500>;
@@ -1311,6 +1354,63 @@
 		status = "disabled";
 	};
 
+	usbdrd: usb0 {
+		compatible = "rockchip,rv1126-dwc3", "rockchip,rk3399-dwc3";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clocks = <&cru CLK_USBOTG_REF>, <&cru ACLK_USBOTG>;
+		clock-names = "ref_clk", "bus_clk";
+		status = "disabled";
+
+		usbdrd_dwc3: dwc3@ffd00000 {
+			compatible = "snps,dwc3";
+			reg = <0xffd00000 0x100000>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "otg";
+			maximum-speed = "high-speed";
+			phys = <&u2phy_otg>;
+			phy-names = "usb2-phy";
+			phy_type = "utmi_wide";
+			power-domains = <&power RV1126_PD_USB>;
+			resets = <&cru SRST_USBOTG_A>;
+			reset-names = "usb3-otg";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,tx-ipgap-linecheck-dis-quirk;
+			snps,xhci-trb-ent-quirk;
+			status = "disabled";
+		};
+	};
+
+	usb_host0_ehci: usb@ffe00000 {
+		compatible = "generic-ehci";
+		reg = <0xffe00000 0x20000>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
+			 <&u2phy1>;
+		clock-names = "usbhost", "arbiter", "utmi";
+		phys = <&u2phy_host>;
+		phy-names = "usb";
+		power-domains = <&power RV1126_PD_USB>;
+		status = "disabled";
+	};
+
+	usb_host0_ohci: usb@ffe10000 {
+		compatible = "generic-ohci";
+		reg = <0xffe20000 0x20000>;
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
+			 <&u2phy1>;
+		clock-names = "usbhost", "arbiter", "utmi";
+		phys = <&u2phy_host>;
+		phy-names = "usb";
+		power-domains = <&power RV1126_PD_USB>;
+		status = "disabled";
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rv1126-pinctrl";
 		rockchip,grf = <&grf>;