From 8260665f10360e52e39152dc97b0b74e4832f735 Mon Sep 17 00:00:00 2001
From: Jianqun Xu <jay.xu@rock-chips.com>
Date: Tue, 26 Jun 2018 15:05:47 +0800
Subject: [PATCH] arm64: dts: rockchip: add dts file for rk1808-fpga

Add dts file for rk1808-fpga, enable fiq-debugger and
set the baudrate to be 1500000Hz.

Support emmc and sdmmc for now.
Add clk_ignore_unused.

Change-Id: Ie2c3debd6f6f162a261061e5bcf6db5ab59b4c31
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/Makefile        |  1 +
 arch/arm64/boot/dts/rockchip/rk1808-fpga.dts | 56 ++++++++++++++++++++
 2 files changed, 57 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk1808-fpga.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 86702d25737d..46c08def97c7 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-lvds-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr4-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk1808-evb-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk1808-fpga.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-ai-va-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-amic-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-amic-v11.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk1808-fpga.dts b/arch/arm64/boot/dts/rockchip/rk1808-fpga.dts
new file mode 100644
index 000000000000..c1f8668d316b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk1808-fpga.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
+
+/dts-v1/;
+#include "rk1808.dtsi"
+
+/ {
+	model = "Rockchip rk1808 fpga board";
+	compatible = "rockchip,fpga", "rockchip,rk1808";
+
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 root=/dev/mmcblk1p8 rootfstype=ext4 rootwait clk_ignore_unused";
+	};
+
+	memory@200000 {
+		device_type = "memory";
+		reg = <0x0 0x00200000 0x0 0x0FE00000>;
+	};
+
+	fiq_debugger: fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <2>;
+		rockchip,wake-irq = <0>;
+		rockchip,irq-mode-enable = <1>;
+		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+		status = "okay";
+	};
+};
+
+&emmc {
+	max-frequency = <400000>;
+	clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>;
+	clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+	mmc-hs200-1_8v;
+	supports-emmc;
+	num-slots = <1>;
+	status = "okay";
+};
+
+&npu {
+	status = "okay";
+};
+
+&sdmmc {
+	max-frequency = <400000>;
+	clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>;
+	clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+	supports-sd;
+	status = "okay";
+};
+
+/* If fiq_debugger set okay, need to define uart2 and to be disabled */
+&uart2 {
+	status = "disabled";
+};