From 8263003c2879820c2a86679b22ad6d44edb65b78 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Wed, 8 Dec 2021 14:36:47 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: Add config for rk3588 pcie This patch aims to configure pcie for better compatibility. 1.PLL LPF C1 85pf R1 1.25kohm 2.ck100m_pcie from PLL Change-Id: I5115cf6ce7341c0891f13639f2c59db86ae9014b Signed-off-by: Kever Yang Signed-off-by: Jon Lin --- .../phy/rockchip/phy-rockchip-naneng-combphy.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 5d6a4c861b67..06c11a08a1e9 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -748,7 +748,23 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) break; case 100000000: param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); - if (priv->mode == PHY_TYPE_SATA) { + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~GENMASK(4, 2); + val |= 0x4 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ + val = 0x4c; + writel(val, priv->mmio + (0x1b << 2)); + + /* Set up su_trim: */ + val = 0xf0; + writel(val, priv->mmio + (0xa << 2)); + val = 0x4; + writel(val, priv->mmio + (0xb << 2)); + } else if (priv->mode == PHY_TYPE_SATA) { /* downward spread spectrum +500ppm */ val = readl(priv->mmio + (0x1f << 2)); val &= ~GENMASK(7, 4);