From 827bf4adc0f5466cd3bca018dbaa703b70df5bc2 Mon Sep 17 00:00:00 2001 From: Zhihuan He Date: Wed, 30 Oct 2024 17:27:01 +0800 Subject: [PATCH] clk: rockchip: rk3576: add PCLK_DDR_MON_CH for ddr monitor Change-Id: I2239f6d96d144f7a314a7df2fd2fe60477464233 Signed-off-by: Zhihuan He --- drivers/clk/rockchip/clk-rk3576.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c index 450338d6b852..5dc235c70e5c 100644 --- a/drivers/clk/rockchip/clk-rk3576.c +++ b/drivers/clk/rockchip/clk-rk3576.c @@ -878,8 +878,10 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { COMPOSITE(PCLK_DDR_ROOT, "pclk_ddr_root", gpll_cpll_24m_p, CLK_IS_CRITICAL, RK3576_CLKSEL_CON(76), 5, 2, MFLAGS, 0, 5, DFLAGS, RK3576_CLKGATE_CON(21), 0, GFLAGS), - GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", CLK_IGNORE_UNUSED, + GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", 0, RK3576_CLKGATE_CON(21), 1, GFLAGS), + GATE(PCLK_DDR_MON_CH1, "pclk_ddr_mon_ch1", "pclk_ddr_root", 0, + RK3576_CLKGATE_CON(21), 14, GFLAGS), COMPOSITE(HCLK_DDR_ROOT, "hclk_ddr_root", gpll_cpll_p, CLK_IGNORE_UNUSED, RK3576_CLKSEL_CON(77), 5, 1, MFLAGS, 0, 5, DFLAGS, RK3576_CLKGATE_CON(22), 11, GFLAGS),