From 82d02d02c55bfedd6b95ecc758a37a4bcfdd7fb5 Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 29 Dec 2021 08:51:22 +0000 Subject: [PATCH] phy: rockchip: mipi-dcphy: reduce time when phy power up Change-Id: I64e6b11c7f68d76ab1bdecb35f618d4033cadbec Signed-off-by: Guochun Huang --- .../phy/rockchip/phy-rockchip-samsung-dcphy.c | 86 ++++++------------- 1 file changed, 27 insertions(+), 59 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c index 03a6f259366f..b1feb8018ee2 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c @@ -1215,57 +1215,41 @@ static void samsung_mipi_dcphy_bias_block_disable(struct samsung_mipi_dcphy *sam static void samsung_mipi_dphy_lane_enable(struct samsung_mipi_dcphy *samsung) { - u32 sts; - int ret; - regmap_write(samsung->regmap, DPHY_MC_GNR_CON1, T_PHY_READY(0x2000)); - regmap_write(samsung->regmap, COMBO_MD0_GNR_CON1, T_PHY_READY(0x2000)); - regmap_write(samsung->regmap, COMBO_MD1_GNR_CON1, T_PHY_READY(0x2000)); - regmap_write(samsung->regmap, COMBO_MD2_GNR_CON1, T_PHY_READY(0x2000)); - regmap_write(samsung->regmap, DPHY_MD3_GNR_CON1, T_PHY_READY(0x2000)); - regmap_update_bits(samsung->regmap, DPHY_MC_GNR_CON0, PHY_ENABLE, PHY_ENABLE); - regmap_update_bits(samsung->regmap, COMBO_MD0_GNR_CON0, - PHY_ENABLE, PHY_ENABLE); - regmap_update_bits(samsung->regmap, COMBO_MD1_GNR_CON0, - PHY_ENABLE, PHY_ENABLE); - regmap_update_bits(samsung->regmap, COMBO_MD2_GNR_CON0, - PHY_ENABLE, PHY_ENABLE); - regmap_update_bits(samsung->regmap, DPHY_MD3_GNR_CON0, - PHY_ENABLE, PHY_ENABLE); - ret = regmap_read_poll_timeout(samsung->regmap, DPHY_MC_GNR_CON0, - sts, (sts & PHY_READY), 200, 2000); - if (ret < 0) - dev_err(samsung->dev, "D-PHY clk lane is not locked\n"); - - ret = regmap_read_poll_timeout(samsung->regmap, COMBO_MD0_GNR_CON0, - sts, (sts & PHY_READY), 200, 2000); - if (ret < 0) - dev_err(samsung->dev, "D-PHY Data0 lane is not locked\n"); - - ret = regmap_read_poll_timeout(samsung->regmap, COMBO_MD1_GNR_CON0, - sts, (sts & PHY_READY), 200, 2000); - if (ret < 0) - dev_err(samsung->dev, "D-PHY Data1 lane is not locked\n"); - - ret = regmap_read_poll_timeout(samsung->regmap, COMBO_MD2_GNR_CON0, - sts, (sts & PHY_READY), 200, 2000); - if (ret < 0) - dev_err(samsung->dev, "D-PHY Data2 lane is not locked\n"); - - ret = regmap_read_poll_timeout(samsung->regmap, DPHY_MD3_GNR_CON0, - sts, (sts & PHY_READY), 200, 2000); - if (ret < 0) - dev_err(samsung->dev, "D-PHY Data3 lane is not locked\n"); + switch (samsung->lanes) { + case 4: + regmap_write(samsung->regmap, DPHY_MD3_GNR_CON1, + T_PHY_READY(0x2000)); + regmap_update_bits(samsung->regmap, DPHY_MD3_GNR_CON0, + PHY_ENABLE, PHY_ENABLE); + fallthrough; + case 3: + regmap_write(samsung->regmap, COMBO_MD2_GNR_CON1, + T_PHY_READY(0x2000)); + regmap_update_bits(samsung->regmap, COMBO_MD2_GNR_CON0, + PHY_ENABLE, PHY_ENABLE); + fallthrough; + case 2: + regmap_write(samsung->regmap, COMBO_MD1_GNR_CON1, + T_PHY_READY(0x2000)); + regmap_update_bits(samsung->regmap, COMBO_MD1_GNR_CON0, + PHY_ENABLE, PHY_ENABLE); + fallthrough; + case 1: + default: + regmap_write(samsung->regmap, COMBO_MD0_GNR_CON1, + T_PHY_READY(0x2000)); + regmap_update_bits(samsung->regmap, COMBO_MD0_GNR_CON0, + PHY_ENABLE, PHY_ENABLE); + break; + } } static void samsung_mipi_cphy_lane_enable(struct samsung_mipi_dcphy *samsung) { - u32 sts; - int ret; - regmap_write(samsung->regmap, COMBO_MD0_GNR_CON1, T_PHY_READY(0x2000)); regmap_write(samsung->regmap, COMBO_MD1_GNR_CON1, T_PHY_READY(0x2000)); regmap_write(samsung->regmap, COMBO_MD2_GNR_CON1, T_PHY_READY(0x2000)); @@ -1276,22 +1260,6 @@ static void samsung_mipi_cphy_lane_enable(struct samsung_mipi_dcphy *samsung) PHY_ENABLE, PHY_ENABLE); regmap_update_bits(samsung->regmap, COMBO_MD2_GNR_CON0, PHY_ENABLE, PHY_ENABLE); - - /* 200us is needed for locking the PLL */ - ret = regmap_read_poll_timeout(samsung->regmap, COMBO_MD0_GNR_CON0, - sts, (sts & PHY_READY), 200, 2000); - if (ret < 0) - dev_err(samsung->dev, "C-PHY Data0 lane is not locked\n"); - - ret = regmap_read_poll_timeout(samsung->regmap, COMBO_MD1_GNR_CON0, - sts, (sts & PHY_READY), 200, 2000); - if (ret < 0) - dev_err(samsung->dev, "C-PHY Data1 lane is not locked\n"); - - ret = regmap_read_poll_timeout(samsung->regmap, COMBO_MD2_GNR_CON0, - sts, (sts & PHY_READY), 200, 2000); - if (ret < 0) - dev_err(samsung->dev, "C-PHY Data2 lane is not locked\n"); } static void samsung_mipi_dphy_lane_disable(struct samsung_mipi_dcphy *samsung)