From 83297698a17bebc3a6fbdf64a00f63cec8bd46a2 Mon Sep 17 00:00:00 2001 From: David Wu Date: Thu, 22 Oct 2020 16:56:01 +0800 Subject: [PATCH] arm64: dts: rockchip: Add gmac node for rk3568-evb Signed-off-by: David Wu Change-Id: I112dfd391fb447fff2eaa22665e9a77182ccd3b4 --- .../dts/rockchip/rk3566-evb2-lp4x-v10.dts | 30 ++++++++++ .../rockchip/rk3568-evb1-ddr4-v10-linux.dts | 60 +++++++++++++++++++ .../dts/rockchip/rk3568-evb1-ddr4-v10.dts | 60 +++++++++++++++++++ .../dts/rockchip/rk3568-evb6-ddr3-v10.dts | 30 ++++++++++ 4 files changed, 180 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dts index 39832d857874..0c2d74e5be58 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dts @@ -15,3 +15,33 @@ model = "Rockchip RK3566 EVB2 LP4X V10 Board"; compatible = "rockchip,rk3566-evb2-lp4x-v10", "rockchip,rk3568"; }; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim_pins &gmac1m1_rgmii_pins>; + + tx_delay = <0x2a>; + rx_delay = <0x1a>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-linux.dts index da3ab16cbb49..cc8d7d80a296 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-linux.dts @@ -65,3 +65,63 @@ vin-supply = <&vcc5v0_sys>; }; }; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim_pins &gmac0_rgmii_pins>; + + tx_delay = <0x2a>; + rx_delay = <0x1a>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim_pins &gmac1m1_rgmii_pins>; + + tx_delay = <0x2a>; + rx_delay = <0x1a>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dts index 4bc1a92b7b69..0f773bb7e496 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dts @@ -65,3 +65,63 @@ vin-supply = <&vcc5v0_sys>; }; }; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim_pins &gmac0_rgmii_pins>; + + tx_delay = <0x2a>; + rx_delay = <0x1a>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim_pins &gmac1m1_rgmii_pins>; + + tx_delay = <0x2a>; + rx_delay = <0x1a>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dts index d034c903866c..df61a1fde975 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dts @@ -13,3 +13,33 @@ model = "Rockchip RK3568 EVB6 DDR3 V10 Board"; compatible = "rockchip,rk3568-evb6-ddr3-v10", "rockchip,rk3568"; }; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim_pins &gmac1m0_rgmii_pins>; + + tx_delay = <0x2a>; + rx_delay = <0x1a>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +};