diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index b1ec0c35947b..1bdf78cae12a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -768,7 +768,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) /* stage config flush mask */ ctl->ops.update_pending_flush_dspp(ctl, - mixer[i].hw_dspp->idx); + mixer[i].hw_dspp->idx, DPU_DSPP_PCC); } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index b39e72a72d58..7b8a5a5cfec7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -66,7 +66,10 @@ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) #define CTL_SC7280_MASK \ - (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG)) + (BIT(DPU_CTL_ACTIVE_CFG) | \ + BIT(DPU_CTL_FETCH_ACTIVE) | \ + BIT(DPU_CTL_VM_CFG) | \ + BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) #define CTL_SM8550_MASK \ (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index ae85b40e282b..63d7c6b15110 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -169,10 +169,12 @@ enum { * DSPP sub-blocks * @DPU_DSPP_PCC Panel color correction block * @DPU_DSPP_GC Gamma correction block + * @DPU_DSPP_IGC Inverse gamma correction block */ enum { DPU_DSPP_PCC = 0x1, DPU_DSPP_GC, + DPU_DSPP_IGC, DPU_DSPP_MAX }; @@ -200,6 +202,7 @@ enum { * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) * @DPU_CTL_VM_CFG: CTL config to support multiple VMs * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register + * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush * @DPU_CTL_MAX */ enum { @@ -208,6 +211,7 @@ enum { DPU_CTL_FETCH_ACTIVE, DPU_CTL_VM_CFG, DPU_CTL_HAS_LAYER_EXT4, + DPU_CTL_DSPP_SUB_BLOCK_FLUSH, DPU_CTL_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 6c53ea560ffa..bbdc95ce374a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -26,15 +26,16 @@ #define CTL_SW_RESET 0x030 #define CTL_LAYER_EXTN_OFFSET 0x40 #define CTL_MERGE_3D_ACTIVE 0x0E4 +#define CTL_DSC_ACTIVE 0x0E8 #define CTL_WB_ACTIVE 0x0EC #define CTL_INTF_ACTIVE 0x0F4 +#define CTL_FETCH_PIPE_ACTIVE 0x0FC #define CTL_MERGE_3D_FLUSH 0x100 -#define CTL_DSC_ACTIVE 0x0E8 #define CTL_DSC_FLUSH 0x104 #define CTL_WB_FLUSH 0x108 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 -#define CTL_FETCH_PIPE_ACTIVE 0x0FC +#define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) #define CTL_MIXER_BORDER_OUT BIT(24) #define CTL_FLUSH_MASK_CTL BIT(17) @@ -44,6 +45,7 @@ #define DSC_IDX 22 #define INTF_IDX 31 #define WB_IDX 16 +#define DSPP_IDX 29 /* From DPU hw rev 7.x.x */ #define CTL_INVALID_BIT 0xffff #define CTL_DEFAULT_GROUP_ID 0xf @@ -115,6 +117,9 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask, dpu_hw_ctl_get_flush_register(ctx)); ctx->pending_flush_mask = 0x0; + + memset(ctx->pending_dspp_flush_mask, 0, + sizeof(ctx->pending_dspp_flush_mask)); } static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx, @@ -132,6 +137,8 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { + int dspp; + if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, ctx->pending_merge_3d_flush_mask); @@ -142,6 +149,13 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(&ctx->hw, CTL_WB_FLUSH, ctx->pending_wb_flush_mask); + if (ctx->pending_flush_mask & BIT(DSPP_IDX)) + for (dspp = DSPP_0; dspp < DSPP_MAX; dspp++) { + if (ctx->pending_dspp_flush_mask[dspp - DSPP_0]) + DPU_REG_WRITE(&ctx->hw, + CTL_DSPP_n_FLUSH(dspp - DSPP_0), + ctx->pending_dspp_flush_mask[dspp - DSPP_0]); + } DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); } @@ -289,7 +303,7 @@ static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx, } static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx, - enum dpu_dspp dspp) + enum dpu_dspp dspp, u32 dspp_sub_blk) { switch (dspp) { case DSPP_0: @@ -309,6 +323,29 @@ static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx, } } +static void dpu_hw_ctl_update_pending_flush_dspp_sub_blocks( + struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk) +{ + if (dspp >= DSPP_MAX) + return; + + switch (dspp_sub_blk) { + case DPU_DSPP_IGC: + ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(2); + break; + case DPU_DSPP_PCC: + ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(4); + break; + case DPU_DSPP_GC: + ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(5); + break; + default: + return; + } + + ctx->pending_flush_mask |= BIT(DSPP_IDX); +} + static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us) { struct dpu_hw_blk_reg_map *c = &ctx->hw; @@ -630,7 +667,11 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->setup_blendstage = dpu_hw_ctl_setup_blendstage; ops->update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp; ops->update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer; - ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp; + if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) + ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks; + else + ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp; + if (cap & BIT(DPU_CTL_FETCH_ACTIVE)) ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 96c012ec8467..78611a831697 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -152,9 +152,11 @@ struct dpu_hw_ctl_ops { * No effect on hardware * @ctx : ctl path ctx pointer * @blk : DSPP block index + * @dspp_sub_blk : DSPP sub-block index */ void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx, - enum dpu_dspp blk); + enum dpu_dspp blk, u32 dspp_sub_blk); + /** * Write the value of the pending_flush_mask to hardware * @ctx : ctl path ctx pointer @@ -242,6 +244,7 @@ struct dpu_hw_ctl { u32 pending_intf_flush_mask; u32 pending_wb_flush_mask; u32 pending_merge_3d_flush_mask; + u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0]; /* ops */ struct dpu_hw_ctl_ops ops;