From 843fd2249d31cdfd434a0503875d9714273c1d13 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Sat, 3 Sep 2022 14:35:32 +0000 Subject: [PATCH] phy/rockchip: samsung-hdptx: correct SDC_N According to the datasheet rev1.05 Table 5-1: SDC_N is 1 for HBR/HBR2. However datasheet wasn't correct. Signed-off-by: Wyon Bi Change-Id: I1cf6d573a6e886a32999dbf1b0e2ad43c5cdc30c --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 8a7d76511d05..80dc8439b9b9 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -830,8 +830,8 @@ static void rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy *hdptx) FIELD_PREP(ROPLL_SDC_N_RBR, 0x2)); regmap_update_bits(hdptx->regmap, 0x01a8, ROPLL_SDC_N_HBR | ROPLL_SDC_N_HBR2, - FIELD_PREP(ROPLL_SDC_N_HBR, 0x1) | - FIELD_PREP(ROPLL_SDC_N_HBR2, 0x1)); + FIELD_PREP(ROPLL_SDC_N_HBR, 0x2) | + FIELD_PREP(ROPLL_SDC_N_HBR2, 0x2)); regmap_write(hdptx->regmap, 0x01b0, FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x3));