diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5f2038e8a158..ae6662c42809 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -522,6 +522,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3128-fireprime.dtb \ rk3188-radxarock.dtb \ rk3228-evb.dtb \ + rk3229-at-3nod.dtb \ rk3229-echo-v10.dtb \ rk3229-evb.dtb \ rk3229-gva-sdk.dtb \ diff --git a/arch/arm/boot/dts/rk3229-at-3nod.dts b/arch/arm/boot/dts/rk3229-at-3nod.dts new file mode 100644 index 000000000000..34dd20caf14b --- /dev/null +++ b/arch/arm/boot/dts/rk3229-at-3nod.dts @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk3229-at-som.dtsi" + +/ { + model = "RK3229 ANDROID THINGS 3NOD Board"; + compatible = "rockchip,rk3229-at-3nod", "rockchip,rk3229"; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk805 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* GPIO3_B7 */ + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk805 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart11_rts>; + pinctrl-1 = <&uart11_rts_gpio>; + BT,reset_gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6255"; + WIFI,host_wake_irq = <&gpio0 28 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power_key { + label = "GPIO Key Power"; + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + linux,code = <116>; + debounce-interval = <100>; + wakeup-source; + }; + + }; +}; + +&emmc { + /* + * enable emmc ddr mode, choose the + * according parameter base on the emmc + * io voltage. + */ + mmc-ddr-1_8v; + //mmc-ddr-1_2v; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&nandc { + status = "disabled"; +}; + +&pinctrl { + pinctrl-names = "default", "gpio_pwm0", "gpio_pwm1", "gpio_spdif", "gpio_irrx"; + /* + * sdmmc pins are defaultly set as gpio, if you want to enable + * it, please remove below line. + */ + pinctrl-0 = <&gpio1b6_gpio &gpio1b7_gpio &gpio1c0_gpio + &gpio1c1_gpio &gpio1c2_gpio &gpio1c3_gpio + &gpio1c4_gpio &gpio1c5_gpio>; + /* + * pwm0 pins are defaultly set as gpio, if you want to enable + * it, please remove below line. + */ + pinctrl-1 = <&gpio3c5_gpio>; + /* + * pwm1 pins are defaultly set as gpio, if you want to enable + * it, please remove below line. + */ + pinctrl-2 = <&gpio1b4_gpio>; + /* + * spdif pins are defaultly set as gpio, if you want to enable + * it, please remove below line. + */ + pinctrl-3 = <&gpio3d7_gpio>; + /* + * ir_rx pins are defaultly set as gpio, if you want to enable + * it, please remove below line. + */ + pinctrl-4 = <&gpio1b3_gpio>; + + ir-rx-gpio { + gpio1b3_gpio: gpio1b3-gpio { + rockchip,pins = + <1 11 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <3 23 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pwm0-gpio { + gpio3c5_gpio: gpio3c5-gpio { + rockchip,pins = + <3 21 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pwm2-gpio { + gpio1b4_gpio: gpio1b4-gpio { + rockchip,pins = + <1 12 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 15 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc-gpio { + gpio1b6_gpio: gpio1b6-gpio { + rockchip,pins = + <1 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + gpio1b7_gpio: gpio1b7-gpio { + rockchip,pins = + <1 15 RK_FUNC_GPIO &pcfg_pull_up>; + }; + gpio1c0_gpio: gpio1c0-gpio { + rockchip,pins = + <1 16 RK_FUNC_GPIO &pcfg_pull_none>; + }; + gpio1c1_gpio: gpio1c1-gpio { + rockchip,pins = + <1 17 RK_FUNC_GPIO &pcfg_pull_up>; + }; + gpio1c2_gpio: gpio1c2-gpio { + rockchip,pins = + <1 18 RK_FUNC_GPIO &pcfg_pull_up>; + }; + gpio1c3_gpio: gpio1c3-gpio { + rockchip,pins = + <1 19 RK_FUNC_GPIO &pcfg_pull_up>; + }; + gpio1c4_gpio: gpio1c4-gpio { + rockchip,pins = + <1 20 RK_FUNC_GPIO &pcfg_pull_up>; + }; + gpio1c5_gpio: gpio1c5-gpio { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + spdif-out-gpio { + gpio3d7_gpio: gpio3d7-gpio { + rockchip,pins = + <3 31 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&sdio { + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + num-slots = <1>; + sd-uhs-sdr104; + status = "okay"; +}; + +/* + * If sdmmc is enabled on hardware, set status to okay. + * and remove the according pinctrl nodes above. + */ +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + max-frequency = <50000000>; + num-slots = <1>; + supports-sd; + status = "disabled"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP>; + assigned-clock-parents = <&cru HDMIPHY>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3229-at-common.dtsi b/arch/arm/boot/dts/rk3229-at-common.dtsi new file mode 100644 index 000000000000..0c736d7ae05a --- /dev/null +++ b/arch/arm/boot/dts/rk3229-at-common.dtsi @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "rk322x.dtsi" +#include "rk3229-cpu-opp.dtsi" + +/ { + chosen { + bootargs = "earlycon=uart8250,mmio32,0x11030000"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + interrupts = ; + rockchip,serial-id = <2>; + rockchip,signal-irq = <159>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart21_xfer>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; +}; + +&cpu0 { + enable-method = "psci"; +}; + +&cpu1 { + enable-method = "psci"; +}; + +&cpu2 { + enable-method = "psci"; +}; + +&cpu3 { + enable-method = "psci"; +}; + +&emmc { + max-frequency = <125000000>; + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + supports-emmc; + disable-wp; + non-removable; + num-slots = <1>; + /delete-property/ default-sample-phase; + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&gpu { + mali-supply = <&vdd_logic>; +}; + +&i2c0 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + status = "okay"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + spinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + gpio-controller; + #gpio-cells = <2>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + + rtc { + status = "okay"; + }; + + pwrkey { + status = "okay"; + }; + + gpio { + status = "okay"; + }; + + regulators { + compatible = "rk805-regulator"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_arm: RK805_DCDC1@0 { + regulator-compatible = "RK805_DCDC1"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <0x1>; + regulator-ramp-delay = <12500>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_logic: RK805_DCDC2@1 { + regulator-compatible = "RK805_DCDC2"; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <0x1>; + regulator-ramp-delay = <12500>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: RK805_DCDC3@2 { + regulator-compatible = "RK805_DCDC3"; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + }; + }; + + vcc_io: RK805_DCDC4@3 { + regulator-compatible = "RK805_DCDC4"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: RK805_LDO1@4 { + regulator-compatible = "RK805_LDO1"; + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18emmc: RK805_LDO2@5 { + regulator-compatible = "RK805_LDO2"; + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: RK805_LDO3@6 { + regulator-compatible = "RK805_LDO3"; + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_18>; + vccio4-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio1_a1 */ + }; + }; + +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3229-at-som.dtsi b/arch/arm/boot/dts/rk3229-at-som.dtsi new file mode 100644 index 000000000000..08b135091621 --- /dev/null +++ b/arch/arm/boot/dts/rk3229-at-som.dtsi @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +#include "rk3229-at-common.dtsi" + +/ { + + hdmi_sound: hdmi-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,hdmi"; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + rk3229_codec: rk3229_codec{ + compatible = "rk3229_codec"; + #sound-dai-cells = <0>; + clocks = <&cru SCLK_I2S_OUT>; + clock-names = "mclk"; + status = "okay"; + }; + + rk3229_sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + simple-audio-card,name = "rockchip,rk3229-dummy"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + dailink0_master:simple-audio-card,codec { + sound-dai = <&rk3229_codec>; + }; + }; +}; + +&hdmi { + status = "okay"; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + rockchip,phy_table = + <165000000 0 0 4 4 4 4>, + <225000000 0 0 6 6 6 6>, + <340000000 1 0 6 10 10 10>, + <594000000 1 0 7 10 10 10>; +}; + +&hdmi_phy { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + cw2015@62 { + status = "okay"; + compatible = "cw201x"; + reg = <0x62>; + bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 + 0x4D 0x48 0x48 0x44 0x44 0x46 0x49 0x48 0x32 + 0x24 0x20 0x17 0x13 0x0F 0x19 0x3E 0x51 0x45 + 0x08 0x76 0x0B 0x85 0x0E 0x1C 0x2E 0x3E 0x4D + 0x52 0x52 0x57 0x3D 0x1B 0x6A 0x2D 0x25 0x43 + 0x52 0x87 0x8F 0x91 0x94 0x52 0x82 0x8C 0x92 + 0x96 0xFF 0x7B 0xBB 0xCB 0x2F 0x7D 0x72 0xA5 + 0xB5 0xC1 0x46 0xAE>; + monitor_sec = <5>; + virtual_power = <0>; + divider_res1 = <200>; + divider_res2 = <200>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2s1 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + rockchip,bclk-fs = <64>; + #sound-dai-cells = <0>; +}; + +&pinctrl { + pinctrl-names = "default"; + + pinctrl-0 = <&fixed0_gpio &fixed1_gpio &fixed2_gpio + &fixed3_gpio &fixed4_gpio &fixed5_gpio + &fixed6_gpio &fixed7_gpio &fixed8_gpio + &fixed9_gpio &fixed10_gpio &fixed11_gpio + &fixed12_gpio &fixed13_gpio &fixed14_gpio + &fixed15_gpio &fixed16_gpio &fixed17_gpio + &fixed18_gpio &fixed19_gpio &fixed20_gpio + &fixed21_gpio &fixed22_gpio>; + + fixed_gpio { + fixed0_gpio: gpio2c3-gpio { + rockchip,pins = + <2 19 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed1_gpio: gpio2c2-gpio { + rockchip,pins = + <2 18 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed2_gpio: gpio2c1-gpio { + rockchip,pins = + <2 17 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed3_gpio: gpio2c0-gpio { + rockchip,pins = + <2 16 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed4_gpio: gpio2b7-gpio { + rockchip,pins = + <2 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed5_gpio: gpio2b6-gpio { + rockchip,pins = + <2 14 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed6_gpio: gpio2b5-gpio { + rockchip,pins = + <2 13 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed7_gpio: gpio2b4-gpio { + rockchip,pins = + <2 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed8_gpio: gpio2b3-gpio { + rockchip,pins = + <2 11 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed9_gpio: gpio2b2-gpio { + rockchip,pins = + <2 10 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed10_gpio: gpio2b1-gpio { + rockchip,pins = + <2 9 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed11_gpio: gpio2b0-gpio { + rockchip,pins = + <2 8 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed12_gpio: gpio1a7-gpio { + rockchip,pins = + <1 7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed13_gpio: gpio1a3-gpio { + rockchip,pins = + <1 3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed14_gpio: gpio1a0-gpio { + rockchip,pins = + <1 0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed15_gpio: gpio1b0-gpio { + rockchip,pins = + <1 8 RK_FUNC_GPIO &pcfg_pull_up>; + }; + fixed16_gpio: gpio0c1-gpio { + rockchip,pins = + <0 17 RK_FUNC_GPIO &pcfg_pull_up>; + }; + fixed17_gpio: gpio0d0-gpio { + rockchip,pins = + <0 24 RK_FUNC_GPIO &pcfg_pull_up>; + }; + fixed18_gpio: gpio3c4-gpio { + rockchip,pins = + <3 20 RK_FUNC_GPIO &pcfg_pull_down>; + }; + fixed19_gpio: gpio2d1-gpio { + rockchip,pins = + <2 25 RK_FUNC_GPIO &pcfg_pull_up>; + }; + fixed20_gpio: gpio2d0-gpio { + rockchip,pins = + <2 24 RK_FUNC_GPIO &pcfg_pull_up>; + }; + fixed21_gpio: gpio2c6-gpio { + rockchip,pins = + <2 22 RK_FUNC_GPIO &pcfg_pull_up>; + }; + fixed22_gpio: gpio2c7-gpio { + rockchip,pins = + <2 23 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + }; + +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-mode-config = < + (0 + |RKPM_CTR_GTCLKS + |RKPM_CTR_IDLESRAM_MD + |RKPM_CTR_PMIC + ) + >; +}; + +&sdio { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cap-sdio-irq; + non-removable; + ignore-pm-notify; + keep-power-in-suspend; + max-frequency = <150000000>; + supports-sdio; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>; + status = "okay"; +}; + +&u2phy0 { + otg-vbus-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart11_xfer &uart11_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_SRC>; + assigned-clock-rates = <50000000>; + clock_in_out = "output"; + phy-supply = <&vcc_18>; + phy-mode = "rmii"; + phy-is-integrated; + status = "okay"; +};