From 863c95ebe8d4864188e474baa4d0f8cc3e0c26e8 Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Thu, 10 Aug 2023 17:20:39 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: fix U3 RX long cable test failed for RK3528 1.Set slow slew rate control for PI 2.Set CDR phase path with 2x gain Signed-off-by: Jianwei Zheng Change-Id: I2d0811b0be7b1d4764ecd738d069b06e4da5eaa2 --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 730dcb706bd8..5a41b9c04568 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -458,6 +458,12 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) /* Enable adaptive CTLE for USB3.0 Rx */ rockchip_combphy_updatel(priv, GENMASK(17, 17), BIT(17), 0x200); + /* Set slow slew rate control for PI */ + rockchip_combphy_updatel(priv, GENMASK(2, 0), 0x07, 0x204); + + /* Set CDR phase path with 2x gain */ + rockchip_combphy_updatel(priv, GENMASK(5, 5), BIT(5), 0x204); + /* Set Rx squelch input filler bandwidth */ rockchip_combphy_updatel(priv, GENMASK(2, 0), 0x06, 0x20c);