diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 67569ffc8dfa..794aa0d220fc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1151,6 +1151,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1106g-evb2-v10-dual-camera.dtb \ rv1106g-evb2-v11-emmc.dtb \ rv1106g-evb2-v11-trailcam-emmc.dtb \ + rv1106g-evb2-v12-aov-spi-nor.dtb \ rv1106g-evb2-v12-nofastae-emmc.dtb \ rv1106g-evb2-v12-nofastae-spi-nand.dtb \ rv1106g-evb2-v12-nofastae-spi-nor.dtb \ diff --git a/arch/arm/boot/dts/rv1106g-evb2-v12-aov-spi-nor.dts b/arch/arm/boot/dts/rv1106g-evb2-v12-aov-spi-nor.dts new file mode 100644 index 000000000000..7a5daaf59659 --- /dev/null +++ b/arch/arm/boot/dts/rv1106g-evb2-v12-aov-spi-nor.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rv1106g-evb2-v10.dts" + +/ { + model = "Rockchip RV1106G EVB2 V12 Board"; + compatible = "rockchip,rv1106g-evb2-v12", "rockchip,rv1106"; +}; + +&rkcif_mipi_lvds { + rtt-suspend; + status = "okay"; +}; + +&rkisp_vir0 { + memory-region-thunderboot = <&rkisp_thunderboot>; + rtt-suspend; + status = "okay"; +}; + +&thunder_boot_service { + memory-no-free; + status = "okay"; +}; diff --git a/arch/arm/configs/rk3126_linux.config b/arch/arm/configs/rk3126_linux.config index 52f5022f6845..8720e2206048 100644 --- a/arch/arm/configs/rk3126_linux.config +++ b/arch/arm/configs/rk3126_linux.config @@ -47,7 +47,6 @@ CONFIG_DEBUG_GPIO=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DNS_RESOLVER is not set -# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set # CONFIG_ECRYPT_FS is not set # CONFIG_ETHERNET is not set @@ -227,7 +226,9 @@ CONFIG_GS_MMA7660=y # CONFIG_GS_SC7A30 is not set # CONFIG_GYROSCOPE_DEVICE is not set # CONFIG_HALL_DEVICE is not set +# CONFIG_IAM20680_ACC is not set # CONFIG_ICM2060X_ACC is not set +# CONFIG_ICM4260X_ACC is not set CONFIG_INLINE_READ_UNLOCK=y CONFIG_INLINE_READ_UNLOCK_IRQ=y CONFIG_INLINE_SPIN_UNLOCK_IRQ=y diff --git a/arch/arm/configs/rk3126_linux_slc_nand.config b/arch/arm/configs/rk3126_linux_slc_nand.config index 17185cae51b7..a4d1b929dd27 100644 --- a/arch/arm/configs/rk3126_linux_slc_nand.config +++ b/arch/arm/configs/rk3126_linux_slc_nand.config @@ -46,7 +46,6 @@ CONFIG_DEBUG_GPIO=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DNS_RESOLVER is not set -# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set # CONFIG_ECRYPT_FS is not set # CONFIG_ETHERNET is not set @@ -232,7 +231,9 @@ CONFIG_GS_MMA7660=y # CONFIG_GS_SC7A30 is not set # CONFIG_GYROSCOPE_DEVICE is not set # CONFIG_HALL_DEVICE is not set +# CONFIG_IAM20680_ACC is not set # CONFIG_ICM2060X_ACC is not set +# CONFIG_ICM4260X_ACC is not set # CONFIG_INFTL is not set CONFIG_INLINE_READ_UNLOCK=y CONFIG_INLINE_READ_UNLOCK_IRQ=y diff --git a/arch/arm/configs/rk3128_linux.config b/arch/arm/configs/rk3128_linux.config index d93cbab25c46..f953797fd9a6 100644 --- a/arch/arm/configs/rk3128_linux.config +++ b/arch/arm/configs/rk3128_linux.config @@ -24,7 +24,6 @@ CONFIG_DEBUG_GPIO=y # CONFIG_DEBUG_LIST is not set CONFIG_DETECT_HUNG_TASK=y # CONFIG_DNS_RESOLVER is not set -# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set CONFIG_DRM_UDL=y # CONFIG_ECRYPT_FS is not set @@ -56,8 +55,6 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_SCHED_STACK_END_CHECK is not set CONFIG_SENSOR_DEVICE=y # CONFIG_SERIAL_OF_PLATFORM is not set -CONFIG_SND_SOC_ROCKCHIP_HDMI=y -CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_SPI_SPIDEV is not set # CONFIG_TEE is not set @@ -110,7 +107,9 @@ CONFIG_GS_MMA7660=y # CONFIG_GS_SC7A30 is not set # CONFIG_GYROSCOPE_DEVICE is not set # CONFIG_HALL_DEVICE is not set +# CONFIG_IAM20680_ACC is not set # CONFIG_ICM2060X_ACC is not set +# CONFIG_ICM4260X_ACC is not set # CONFIG_INTERVAL_TREE_TEST is not set CONFIG_IPC_NS=y # CONFIG_LIGHT_DEVICE is not set diff --git a/arch/arm/configs/rk3128_linux_spi_nand.config b/arch/arm/configs/rk3128_linux_spi_nand.config index 597aef83e926..9da93dcdb095 100644 --- a/arch/arm/configs/rk3128_linux_spi_nand.config +++ b/arch/arm/configs/rk3128_linux_spi_nand.config @@ -24,7 +24,6 @@ CONFIG_DEBUG_GPIO=y # CONFIG_DEBUG_LIST is not set CONFIG_DETECT_HUNG_TASK=y # CONFIG_DNS_RESOLVER is not set -# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set CONFIG_DRM_UDL=y # CONFIG_ECRYPT_FS is not set @@ -58,7 +57,6 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_SCHED_STACK_END_CHECK is not set CONFIG_SENSOR_DEVICE=y # CONFIG_SERIAL_OF_PLATFORM is not set -CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_SPI_SPIDEV is not set # CONFIG_TEE is not set @@ -111,7 +109,9 @@ CONFIG_GS_MMA7660=y # CONFIG_GS_SC7A30 is not set # CONFIG_GYROSCOPE_DEVICE is not set # CONFIG_HALL_DEVICE is not set +# CONFIG_IAM20680_ACC is not set # CONFIG_ICM2060X_ACC is not set +# CONFIG_ICM4260X_ACC is not set # CONFIG_INTERVAL_TREE_TEST is not set CONFIG_IPC_NS=y # CONFIG_LIGHT_DEVICE is not set @@ -128,6 +128,7 @@ CONFIG_PID_NS=y # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set # CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set +# CONFIG_ROCKCHIP_RAM_VENDOR_STORAGE is not set # CONFIG_ROCKCHIP_RGA2 is not set # CONFIG_STK8BAXX_ACC is not set # CONFIG_TEMPERATURE_DEVICE is not set diff --git a/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi index d3f937b38228..97345c0e59ef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-linux.dtsi @@ -60,6 +60,13 @@ }; }; + minidump: minidump { + compatible = "rockchip,minidump"; + smem-region = <&minidump_smem>; + minidump-region = <&minidump_mem>; + status = "disabled"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -84,12 +91,28 @@ ramoops: ramoops@110000 { compatible = "ramoops"; - reg = <0x0 0x110000 0x0 0xf0000>; - record-size = <0x20000>; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ console-size = <0x80000>; + pmsg-size = <0x30000>; ftrace-size = <0x00000>; - pmsg-size = <0x50000>; + record-size = <0x14000>; }; + + minidump_smem: minidump-smem@1f0000 { + reg = <0x0 0x1f0000 0x0 0x100>; /* do not change */ + no-map; + status = "disabled"; + }; + + minidump_mem: minidump-mem@c000000 { + reg = <0x0 0x0c000000 0x0 0x2000000>; /* changing according to your project */ + no-map; + status = "disabled"; + }; + }; }; diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index d00ce804440c..cefba84a765e 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -791,6 +791,26 @@ config VIDEO_JX_K17 config VIDEO_MAX9271_LIB tristate +config VIDEO_MIS2031 + tristate "ImageDesign mis2031 sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the ImageDesign + MIS2031 camera. + +config VIDEO_MIS4001 + tristate "ImageDesign mis4001 sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the ImageDesign + MIS4001 camera. + config VIDEO_MT9M001 tristate "mt9m001 support" depends on I2C && VIDEO_DEV @@ -1712,6 +1732,17 @@ config VIDEO_SC2336 This is a Video4Linux2 sensor driver for the SmartSens SC2336 camera. +config VIDEO_SC2355 + tristate "SmartSens SC2355 sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + Support for the SmartSens SC2355 sensor. + To compile this driver as a module, choose M here: the + module will be called sc2355. + config VIDEO_SC301IOT tristate "SmartSens SC301IOT sensor support" depends on I2C && VIDEO_DEV diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 9af35022a119..dbfbb2b65292 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -121,6 +121,8 @@ obj-$(CONFIG_VIDEO_MAX96712) += max96712.o obj-$(CONFIG_VIDEO_MAX96714) += max96714.o obj-$(CONFIG_VIDEO_MAX96722) += max96722.o obj-$(CONFIG_VIDEO_MAX96756) += max96756.o +obj-$(CONFIG_VIDEO_MIS2031) += mis2031.o +obj-$(CONFIG_VIDEO_MIS4001) += mis4001.o obj-$(CONFIG_VIDEO_ML86V7667) += ml86v7667.o obj-$(CONFIG_VIDEO_MSP3400) += msp3400.o obj-$(CONFIG_VIDEO_MT9M001) += mt9m001.o @@ -220,6 +222,7 @@ obj-$(CONFIG_VIDEO_SC223A) += sc223a.o obj-$(CONFIG_VIDEO_SC230AI) += sc230ai.o obj-$(CONFIG_VIDEO_SC2310) += sc2310.o obj-$(CONFIG_VIDEO_SC2336) += sc2336.o +obj-$(CONFIG_VIDEO_SC2355) += sc2355.o obj-$(CONFIG_VIDEO_SC301IOT) += sc301iot.o obj-$(CONFIG_VIDEO_SC3336) += sc3336.o obj-$(CONFIG_VIDEO_SC3338) += sc3338.o diff --git a/drivers/media/i2c/max96756.c b/drivers/media/i2c/max96756.c index ae95794bb0f5..2cb28127b270 100644 --- a/drivers/media/i2c/max96756.c +++ b/drivers/media/i2c/max96756.c @@ -6,6 +6,8 @@ * * V0.0X01.0X00 first version. * + * V0.0X01.0X01 + * - Support V4L2 DV class features */ #define DEBUG @@ -22,21 +24,29 @@ #include #include #include +#include #include #include #include +#include +#include +#include #include #include #include "max96756.h" -#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00) +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01) + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "debug level (0-3)"); #ifndef V4L2_CID_DIGITAL_GAIN #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN #endif -#define MAX96756_LINK_FREQ_450MHZ (450 * 1000 * 1000UL) -#define MAX96756_PIXEL_RATE (MAX96756_LINK_FREQ_450MHZ * 2LL * 4LL / 8LL) +#define MAX96756_LINK_FREQ_MHZ(x) ((x)*1000 * 1000ULL) +#define MAX96756_PIXEL_RATE (450LL * 2 * 4 / 8) #define MAX96756_REG_CHIP_ID 0x0D #define CHIP_ID 0x90 @@ -92,30 +102,43 @@ struct max96756_mode { const struct regval *reg_list; }; +static const struct v4l2_dv_timings_cap max96756_timings_cap = { + .type = V4L2_DV_BT_656_1120, + .reserved = { 0 }, + V4L2_INIT_BT_TIMINGS( + 1, 10000, 1, 10000, 0, 800000000, + V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | + V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, + V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED | + V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM) +}; + struct max96756 { struct i2c_client *client; struct clk *xvclk; struct gpio_desc *pwdn_gpio; - struct regulator_bulk_data supplies[MAX96756_NUM_SUPPLIES]; struct pinctrl *pinctrl; struct pinctrl_state *pins_default; struct pinctrl_state *pins_sleep; + struct gpio_desc *lock_gpio; + int lock_irq; + struct delayed_work delayed_work_lock; + struct work_struct work_i2c_poll; + struct v4l2_subdev subdev; struct media_pad pad; + struct v4l2_fwnode_endpoint bus_cfg; struct v4l2_ctrl_handler ctrl_handler; - struct v4l2_ctrl *exposure; - struct v4l2_ctrl *anal_gain; - struct v4l2_ctrl *digi_gain; - struct v4l2_ctrl *hblank; - struct v4l2_ctrl *vblank; + struct v4l2_ctrl *lock_det; struct v4l2_ctrl *pixel_rate; struct v4l2_ctrl *link_freq; struct v4l2_ctrl *test_pattern; + struct v4l2_dv_timings timings; struct mutex mutex; bool streaming; @@ -223,8 +246,22 @@ static const struct max96756_mode supported_modes[] = { }, }; +static const struct max96756_mode supported_modes_dcphy[] = { + { + .width = 1920, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .reg_list = max96756_mipi_1080p_60fps, + .link_freq_idx = 1, + }, +}; + static const s64 link_freq_items[] = { - MAX96756_LINK_FREQ_450MHZ, + MAX96756_LINK_FREQ_MHZ(450), + MAX96756_LINK_FREQ_MHZ(900), }; static int max96756_write_reg(struct i2c_client *client, u16 reg, u32 len, @@ -478,6 +515,9 @@ static long max96756_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) case RKMODULE_GET_MODULE_INFO: max96756_get_module_inf(max96756, (struct rkmodule_inf *)arg); break; + case RKMODULE_GET_HDMI_MODE: + *(int *)arg = RKMODULE_HDMIIN_MODE; + break; case RKMODULE_SET_QUICK_STREAM: stream = *((u32 *)arg); if (stream) @@ -522,11 +562,11 @@ static long max96756_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd, { void __user *up = compat_ptr(arg); struct rkmodule_inf *inf; - struct rkmodule_awb_cfg *cfg; struct rkmodule_vicap_reset_info *vicap_rst_inf; long ret = 0; int *seq; u32 stream = 0; + struct rkmodule_csi_dphy_param *dphy_param; switch (cmd) { case RKMODULE_GET_MODULE_INFO: @@ -544,19 +584,20 @@ static long max96756_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd, } kfree(inf); break; - case RKMODULE_AWB_CFG: - cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); - if (!cfg) { + case RKMODULE_GET_HDMI_MODE: + seq = kzalloc(sizeof(*seq), GFP_KERNEL); + if (!seq) { ret = -ENOMEM; return ret; } - ret = copy_from_user(cfg, up, sizeof(*cfg)); - if (!ret) - ret = max96756_ioctl(sd, cmd, cfg); - else - ret = -EFAULT; - kfree(cfg); + ret = max96756_ioctl(sd, cmd, seq); + if (!ret) { + ret = copy_to_user(up, seq, sizeof(*seq)); + if (ret) + ret = -EFAULT; + } + kfree(seq); break; case RKMODULE_GET_VICAP_RST_INFO: vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL); @@ -588,21 +629,6 @@ static long max96756_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd, ret = -EFAULT; kfree(vicap_rst_inf); break; - case RKMODULE_GET_START_STREAM_SEQ: - seq = kzalloc(sizeof(*seq), GFP_KERNEL); - if (!seq) { - ret = -ENOMEM; - return ret; - } - - ret = max96756_ioctl(sd, cmd, seq); - if (!ret) { - ret = copy_to_user(up, seq, sizeof(*seq)); - if (ret) - ret = -EFAULT; - } - kfree(seq); - break; case RKMODULE_SET_QUICK_STREAM: ret = copy_from_user(&stream, up, sizeof(u32)); if (!ret) @@ -610,6 +636,35 @@ static long max96756_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd, else ret = -EFAULT; break; + case RKMODULE_SET_CSI_DPHY_PARAM: + dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL); + if (!dphy_param) { + ret = -ENOMEM; + return ret; + } + + ret = copy_from_user(dphy_param, up, sizeof(*dphy_param)); + if (!ret) + ret = max96756_ioctl(sd, cmd, dphy_param); + else + ret = -EFAULT; + kfree(dphy_param); + break; + case RKMODULE_GET_CSI_DPHY_PARAM: + dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL); + if (!dphy_param) { + ret = -ENOMEM; + return ret; + } + + ret = max96756_ioctl(sd, cmd, dphy_param); + if (!ret) { + ret = copy_to_user(up, dphy_param, sizeof(*dphy_param)); + if (ret) + ret = -EFAULT; + } + kfree(dphy_param); + break; default: ret = -ENOIOCTLCMD; break; @@ -619,6 +674,19 @@ static long max96756_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd, } #endif +static int max96756_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + switch (sub->type) { + case V4L2_EVENT_SOURCE_CHANGE: + return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); + case V4L2_EVENT_CTRL: + return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); + default: + return -EINVAL; + } +} + static int __max96756_start_stream(struct max96756 *max96756) { int ret; @@ -656,6 +724,143 @@ static int __max96756_stop_stream(struct max96756 *max96756) return ret; } +static bool max96756_match_timings(const struct v4l2_dv_timings *t1, + const struct v4l2_dv_timings *t2) +{ + if (t1->type != t2->type || t1->type != V4L2_DV_BT_656_1120) + return false; + if (t1->bt.width == t2->bt.width && t1->bt.height == t2->bt.height && + t1->bt.interlaced == t2->bt.interlaced) + return true; + + return false; +} + +static inline bool max96756_detect_lock_status(struct max96756 *max96756) +{ + bool ret; + int val, i, cnt; + + /* if not use lock gpio */ + if (!max96756->lock_gpio) + return true; + + cnt = 0; + for (i = 0; i < 5; i++) { + val = gpiod_get_value(max96756->lock_gpio); + if (val > 0) + cnt++; + usleep_range(500, 600); + } + + ret = (cnt >= 3) ? true : false; + + v4l2_dbg(1, debug, &max96756->subdev, "%s: %d\n", __func__, ret); + + return ret; +} + +static bool max96756_check_signal(struct max96756 *max96756) +{ + u32 val = 0; + + max96756_read_reg(max96756->client, 0x11A, MAX96756_REG_VALUE_08BIT, + &val); + + return val & (1 << 6); +} + +static int max96756_g_input_status(struct v4l2_subdev *sd, u32 *status) +{ + struct max96756 *max96756 = to_max96756(sd); + *status = 0; + *status |= max96756_check_signal(max96756) ? V4L2_IN_ST_NO_SIGNAL : 0; + + v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); + + return 0; +} + +static int max96756_s_dv_timings(struct v4l2_subdev *sd, + struct v4l2_dv_timings *timings) +{ + struct max96756 *max96756 = to_max96756(sd); + + if (!timings) + return -EINVAL; + + if (debug) + v4l2_print_dv_timings(sd->name, "s_dv_timings: ", timings, + false); + + if (max96756_match_timings(&max96756->timings, timings)) { + v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); + return 0; + } + + if (!v4l2_valid_dv_timings(timings, &max96756_timings_cap, NULL, + NULL)) { + v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); + return -ERANGE; + } + + max96756->timings = *timings; + + __max96756_stop_stream(max96756); + + return 0; +} +static int max96756_g_dv_timings(struct v4l2_subdev *sd, + struct v4l2_dv_timings *timings) +{ + struct max96756 *max96756 = to_max96756(sd); + + *timings = max96756->timings; + + return 0; +} + +static int max96756_enum_dv_timings(struct v4l2_subdev *sd, + struct v4l2_enum_dv_timings *timings) +{ + if (timings->pad != 0) + return -EINVAL; + + return v4l2_enum_dv_timings_cap(timings, &max96756_timings_cap, NULL, + NULL); +} + +static int max96756_query_dv_timings(struct v4l2_subdev *sd, + struct v4l2_dv_timings *timings) +{ + struct max96756 *max96756 = to_max96756(sd); + + *timings = max96756->timings; + if (debug) + v4l2_print_dv_timings(sd->name, "query_dv_timings: ", timings, + false); + + if (!v4l2_valid_dv_timings(timings, &max96756_timings_cap, NULL, + NULL)) { + v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); + + return -ERANGE; + } + + return 0; +} + +static int max96756_dv_timings_cap(struct v4l2_subdev *sd, + struct v4l2_dv_timings_cap *cap) +{ + if (cap->pad != 0) + return -EINVAL; + + *cap = max96756_timings_cap; + + return 0; +} + static int max96756_s_stream(struct v4l2_subdev *sd, int on) { struct max96756 *max96756 = to_max96756(sd); @@ -831,8 +1036,6 @@ static int max96756_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad, { config->type = V4L2_MBUS_CSI2_DPHY; config->flags = V4L2_MBUS_CSI2_4_LANE | V4L2_MBUS_CSI2_CHANNEL_0 | - V4L2_MBUS_CSI2_CHANNEL_1 | V4L2_MBUS_CSI2_CHANNEL_2 | - V4L2_MBUS_CSI2_CHANNEL_3 | V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; return 0; @@ -866,6 +1069,8 @@ static const struct v4l2_subdev_internal_ops max96756_internal_ops = { static const struct v4l2_subdev_core_ops max96756_core_ops = { .s_power = max96756_s_power, + .subscribe_event = max96756_subscribe_event, + .unsubscribe_event = v4l2_event_subdev_unsubscribe, .ioctl = max96756_ioctl, #ifdef CONFIG_COMPAT .compat_ioctl32 = max96756_compat_ioctl32, @@ -873,6 +1078,10 @@ static const struct v4l2_subdev_core_ops max96756_core_ops = { }; static const struct v4l2_subdev_video_ops max96756_video_ops = { + .g_input_status = max96756_g_input_status, + .s_dv_timings = max96756_s_dv_timings, + .g_dv_timings = max96756_g_dv_timings, + .query_dv_timings = max96756_query_dv_timings, .s_stream = max96756_s_stream, .g_frame_interval = max96756_g_frame_interval, }; @@ -885,6 +1094,8 @@ static const struct v4l2_subdev_pad_ops max96756_pad_ops = { .set_fmt = max96756_set_fmt, .get_selection = max96756_get_selection, .get_mbus_config = max96756_g_mbus_config, + .enum_dv_timings = max96756_enum_dv_timings, + .dv_timings_cap = max96756_dv_timings_cap, }; static const struct v4l2_subdev_ops max96756_subdev_ops = { @@ -901,20 +1112,26 @@ static int max96756_initialize_controls(struct max96756 *max96756) handler = &max96756->ctrl_handler; mode = max96756->cur_mode; - ret = v4l2_ctrl_handler_init(handler, 2); + ret = v4l2_ctrl_handler_init(handler, 3); if (ret) return ret; handler->lock = &max96756->mutex; - max96756->link_freq = v4l2_ctrl_new_int_menu( - handler, NULL, V4L2_CID_LINK_FREQ, 1, 0, link_freq_items); - + max96756->link_freq = + v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_items) - 1, 0, + link_freq_items); max96756->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0, MAX96756_PIXEL_RATE, 1, MAX96756_PIXEL_RATE); + max96756->lock_det = v4l2_ctrl_new_std( + handler, NULL, V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0); + __v4l2_ctrl_s_ctrl_int64(max96756->pixel_rate, MAX96756_PIXEL_RATE); __v4l2_ctrl_s_ctrl(max96756->link_freq, mode->link_freq_idx); + __v4l2_ctrl_s_ctrl(max96756->lock_det, + max96756_detect_lock_status(max96756)); if (handler->error) { ret = handler->error; @@ -952,6 +1169,29 @@ static int max96756_check_sensor_id(struct max96756 *max96756, return 0; } +static void max96756_delayed_work_lock(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct max96756 *max96756 = + container_of(dwork, struct max96756, delayed_work_lock); + + __v4l2_ctrl_s_ctrl(max96756->lock_det, + max96756_detect_lock_status(max96756)); +} + +static irqreturn_t lock_irq_handler(int irq, void *dev_id) +{ + struct max96756 *max96756 = dev_id; + + mutex_lock(&max96756->mutex); + if (max96756->streaming) + schedule_delayed_work(&max96756->delayed_work_lock, + msecs_to_jiffies(50)); + mutex_unlock(&max96756->mutex); + + return IRQ_HANDLED; +} + static int max96756_configure_regulators(struct max96756 *max96756) { unsigned int i; @@ -964,8 +1204,7 @@ static int max96756_configure_regulators(struct max96756 *max96756) max96756->supplies); } -static int max96756_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int max96756_probe(struct i2c_client *client) { struct device *dev = &client->dev; struct device_node *node = dev->of_node; @@ -1001,6 +1240,25 @@ static int max96756_probe(struct i2c_client *client, if (IS_ERR(max96756->pwdn_gpio)) dev_warn(dev, "Failed to get pwdn-gpios\n"); + max96756->lock_gpio = devm_gpiod_get_optional(dev, "lock", GPIOD_IN); + if (IS_ERR(max96756->lock_gpio)) { + dev_warn(dev, "failed to get lock gpio, will use i2c poll\n"); + } else { + max96756->lock_irq = gpiod_to_irq(max96756->lock_gpio); + if (max96756->lock_irq < 0) + dev_err(dev, "failed to get lock irq, maybe no use\n"); + + ret = devm_request_threaded_irq( + dev, max96756->lock_irq, NULL, lock_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | + IRQF_ONESHOT, + "max96756", max96756); + if (ret) + dev_err(dev, + "failed to register lock irq (%d), maybe no use\n", + ret); + } + ret = max96756_configure_regulators(max96756); if (ret) { dev_err(dev, "Failed to get power regulators\n"); @@ -1036,9 +1294,12 @@ static int max96756_probe(struct i2c_client *client, if (ret) goto err_power_off; + INIT_DELAYED_WORK(&max96756->delayed_work_lock, + max96756_delayed_work_lock); + #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API sd->internal_ops = &max96756_internal_ops; - sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; #endif #if defined(CONFIG_MEDIA_CONTROLLER) max96756->pad.flags = MEDIA_PAD_FL_SOURCE; @@ -1088,6 +1349,8 @@ static int max96756_remove(struct i2c_client *client) struct v4l2_subdev *sd = i2c_get_clientdata(client); struct max96756 *max96756 = to_max96756(sd); + cancel_delayed_work_sync(&max96756->delayed_work_lock); + v4l2_async_unregister_subdev(sd); #if defined(CONFIG_MEDIA_CONTROLLER) media_entity_cleanup(&sd->entity); @@ -1122,26 +1385,13 @@ static struct i2c_driver max96756_i2c_driver = { .pm = &max96756_pm_ops, .of_match_table = of_match_ptr(max96756_of_match), }, - .probe = &max96756_probe, + .probe_new = &max96756_probe, .remove = &max96756_remove, .id_table = max96756_match_id, }; -int max96756_sensor_mod_init(void) -{ - return i2c_add_driver(&max96756_i2c_driver); -} +module_i2c_driver(max96756_i2c_driver); -#ifndef CONFIG_VIDEO_REVERSE_IMAGE -device_initcall_sync(max96756_sensor_mod_init); -#endif - -static void __exit sensor_mod_exit(void) -{ - i2c_del_driver(&max96756_i2c_driver); -} - -module_exit(sensor_mod_exit); - -MODULE_DESCRIPTION("Maxim max96756 sensor driver"); +MODULE_DESCRIPTION("Maxim MAX96756 GMSL1/2 CSI display deserializer driver"); +MODULE_AUTHOR("Cody Xie "); MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/mis2031.c b/drivers/media/i2c/mis2031.c new file mode 100644 index 000000000000..16f310d787c4 --- /dev/null +++ b/drivers/media/i2c/mis2031.c @@ -0,0 +1,1651 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * mis2031 driver + * + * Copyright (C) 2023 Rockchip Electronics Co., Ltd. + * + * V0.0X01.0X01 first version + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../platform/rockchip/isp/rkisp_tb_helper.h" + +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01) + +#define MIS2031_LANES 2 +#define MIS2031_BITS_PER_SAMPLE 10 +#define MIS2031_LINK_FREQ_185 185600000 //37.125mbps + +#define PIXEL_RATE_WITH_315M_10BIT (MIS2031_LINK_FREQ_185 * 2 * \ + MIS2031_LANES / MIS2031_BITS_PER_SAMPLE) +#define MIS2031_XVCLK_FREQ 27000000 + +#define CHIP_ID 0x2009 +#define MIS2031_REG_CHIP_ID 0x3000 + +#define MIS2031_REG_CTRL_MODE 0x3006 +#define MIS2031_MODE_SW_STANDBY BIT(1) +#define MIS2031_MODE_STREAMING 0x0 + +#define MIS2031_REG_EXPOSURE_H 0x3100 +#define MIS2031_REG_EXPOSURE_L 0x3101 +#define MIS2031_EXPOSURE_MIN 1 +#define MIS2031_EXPOSURE_STEP 1 +#define MIS2031_FETCH_EXP_H(VAL) (((VAL) >> 8) & 0xFF) +#define MIS2031_FETCH_EXP_L(VAL) ((VAL) & 0xFF) + +#define MIS2031_REG_DIG_GAIN 0x3700 +#define MIS2031_REG_DIG_FINE_GAIN 0x3701 +#define MIS2031_REG_ANA_GAIN 0x3109 +#define MIS2031_REG_ANA_FINE_GAIN 0x310a +#define MIS2031_GAIN_MIN 0x20 +#define MIS2031_GAIN_MAX (64 * 16 * 32) +#define MIS2031_GAIN_STEP 1 +#define MIS2031_GAIN_DEFAULT 0x20 +#define MIS2031_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03) +#define MIS2031_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF) + +#define MIS2031_REG_GAIN_EXP_VALID 0x300c +#define MIS2031_REG_GAIN_EXP_VALID_VAL BIT(0) + +#define MIS2031_VTS_MAX 0xffff +#define MIS2031_REG_VTS_H 0x3200 +#define MIS2031_REG_VTS_L 0x3201 + +#define MIS2031_FLIP_MIRROR_REG 0x3007 +#define MIRROR_BIT_MASK BIT(0) +#define FLIP_BIT_MASK BIT(1) +#define MIS2031_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x01 : VAL & 0xfe) +#define MIS2031_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x10 : VAL & 0xfd) + +#define MIS2031_REG_TEST_PATTERN 0x3500 +#define MIS2031_TEST_PATTERN_BIT_MASK BIT(0) + +#define REG_DELAY 0xFFFE +#define REG_NULL 0xFFFF + +#define MIS2031_REG_VALUE_08BIT 1 +#define MIS2031_REG_VALUE_16BIT 2 +#define MIS2031_REG_VALUE_24BIT 3 + +#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" +#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" +#define MIS2031_NAME "mis2031" + +static const char * const mis2031_supply_names[] = { + "avdd", /* Analog power */ + "dovdd", /* Digital I/O power */ + "dvdd", /* Digital core power */ +}; + +#define MIS2031_NUM_SUPPLIES ARRAY_SIZE(mis2031_supply_names) + +struct regval { + u16 addr; + u8 val; +}; + +struct mis2031_mode { + u32 bus_fmt; + u32 width; + u32 height; + struct v4l2_fract max_fps; + u32 hts_def; + u32 vts_def; + u32 exp_def; + const struct regval *reg_list; + u32 hdr_mode; + u32 vc[PAD_MAX]; +}; + +struct mis2031 { + struct i2c_client *client; + struct clk *xvclk; + struct gpio_desc *reset_gpio; + struct gpio_desc *pwdn_gpio; + struct regulator_bulk_data supplies[MIS2031_NUM_SUPPLIES]; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_sleep; + + struct v4l2_subdev subdev; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *anal_gain; + struct v4l2_ctrl *digi_gain; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *test_pattern; + struct mutex mutex; + bool streaming; + bool power_on; + const struct mis2031_mode *cur_mode; + struct v4l2_fract cur_fps; + u32 module_index; + const char *module_facing; + const char *module_name; + const char *len_name; + u32 cur_vts; + bool is_thunderboot; + bool is_first_streamoff; +}; + +#define to_mis2031(sd) container_of(sd, struct mis2031, subdev) + +/* + * Xclk 24Mhz + */ +static const struct regval mis2031_global_regs[] = { + {REG_NULL, 0x00}, +}; + +/* + * Xclk 24Mhz + * max_framerate 30fps + * mipi_datarate per lane 630Mbps, 2lane + */ +static const struct regval mis2031_linear_10_1920x1080_regs[] = { + {0x300b, 0x01}, + {0x3006, 0x02}, + {REG_DELAY, 0x50}, + {0x330c, 0x01}, + {0x3020, 0x01}, + {0x3021, 0x02}, + {0x3201, 0x65}, + {0x3200, 0x04}, + {0x3203, 0x98}, + {0x3202, 0x08}, + {0x3205, 0x00}, + {0x3204, 0x00}, + {0x3207, 0x3b}, + {0x3206, 0x04}, + {0x3209, 0x08}, + {0x3208, 0x00}, + {0x320b, 0x87}, + {0x320a, 0x07}, + {0x3102, 0x00}, + {0x3105, 0x00}, + {0x3108, 0x00}, + {0x3007, 0x00}, + {0x300a, 0x01}, + {0x330c, 0x01}, + {0x3300, 0x6e}, + {0x3301, 0x01}, + {0x3302, 0x02}, + {0x3303, 0x06}, + {0x3309, 0x01}, + {0x3307, 0x02}, + {0x330b, 0x0a}, + {0x3014, 0x00}, + {0x330f, 0x00}, + {0x310f, 0x00}, + {0x3986, 0x02}, + {0x3986, 0x02}, + {0x3900, 0x00}, + {0x3902, 0x11}, + {0x3901, 0x00}, + {0x3904, 0x44}, + {0x3903, 0x06}, + {0x3906, 0xff}, + {0x3905, 0x1f}, + {0x3908, 0xff}, + {0x3907, 0x1f}, + {0x390a, 0x42}, + {0x3909, 0x02}, + {0x390c, 0x19}, + {0x390b, 0x03}, + {0x390e, 0x30}, + {0x390d, 0x06}, + {0x3910, 0xff}, + {0x390f, 0x1f}, + {0x3911, 0x01}, + {0x3917, 0x00}, + {0x3916, 0x00}, + {0x3919, 0x90}, + {0x3918, 0x01}, + {0x3913, 0x11}, + {0x3912, 0x00}, + {0x3915, 0x52}, + {0x3914, 0x02}, + {0x391b, 0x00}, + {0x391a, 0x00}, + {0x391d, 0x41}, + {0x391c, 0x06}, + {0x391f, 0xff}, + {0x391e, 0x1f}, + {0x3921, 0xff}, + {0x3920, 0x1f}, + {0x3923, 0x00}, + {0x3922, 0x00}, + {0x3925, 0x46}, + {0x3924, 0x02}, + {0x394c, 0x00}, + {0x394e, 0x74}, + {0x394d, 0x00}, + {0x3950, 0x84}, + {0x394f, 0x00}, + {0x3952, 0x63}, + {0x3951, 0x00}, + {0x3954, 0x71}, + {0x3953, 0x02}, + {0x3927, 0x00}, + {0x3926, 0x00}, + {0x3929, 0xc6}, + {0x3928, 0x00}, + {0x392b, 0x9d}, + {0x392a, 0x01}, + {0x392d, 0x31}, + {0x392c, 0x02}, + {0x392f, 0xcc}, + {0x392e, 0x03}, + {0x3931, 0x60}, + {0x3930, 0x06}, + {0x3933, 0x60}, + {0x3932, 0x06}, + {0x3935, 0x60}, + {0x3934, 0x06}, + {0x3937, 0x60}, + {0x3936, 0x06}, + {0x3939, 0x60}, + {0x3938, 0x06}, + {0x393b, 0x60}, + {0x393a, 0x06}, + {0x3991, 0x40}, + {0x3990, 0x00}, + {0x3993, 0x80}, + {0x3992, 0x06}, + {0x3995, 0xff}, + {0x3994, 0x1f}, + {0x3997, 0x00}, + {0x3996, 0x00}, + {0x393d, 0x74}, + {0x393c, 0x00}, + {0x393f, 0x9d}, + {0x393e, 0x01}, + {0x3941, 0x4a}, + {0x3940, 0x03}, + {0x3943, 0x9c}, + {0x3942, 0x03}, + {0x3945, 0x00}, + {0x3944, 0x00}, + {0x3947, 0xe7}, + {0x3946, 0x00}, + {0x3949, 0xe7}, + {0x3948, 0x00}, + {0x394b, 0x35}, + {0x394a, 0x06}, + {0x395a, 0x00}, + {0x3959, 0x00}, + {0x395c, 0x09}, + {0x395b, 0x00}, + {0x395e, 0x2f}, + {0x395d, 0x02}, + {0x3960, 0x39}, + {0x395f, 0x03}, + {0x3956, 0x09}, + {0x3955, 0x00}, + {0x3958, 0x35}, + {0x3957, 0x06}, + {0x3962, 0x00}, + {0x3961, 0x00}, + {0x3964, 0x84}, + {0x3963, 0x00}, + {0x3966, 0x00}, + {0x3965, 0x00}, + {0x3968, 0x74}, + {0x3967, 0x00}, + {0x3989, 0x00}, + {0x3988, 0x00}, + {0x398b, 0xa5}, + {0x398a, 0x00}, + {0x398d, 0x00}, + {0x398c, 0x00}, + {0x398f, 0x84}, + {0x398e, 0x00}, + {0x396a, 0x62}, + {0x3969, 0x06}, + {0x396d, 0x00}, + {0x396c, 0x01}, + {0x396f, 0x60}, + {0x396e, 0x00}, + {0x3971, 0x60}, + {0x3970, 0x00}, + {0x3973, 0x60}, + {0x3972, 0x00}, + {0x3975, 0x60}, + {0x3974, 0x00}, + {0x3977, 0x60}, + {0x3976, 0x00}, + {0x3979, 0xa0}, + {0x3978, 0x01}, + {0x397b, 0xa0}, + {0x397a, 0x01}, + {0x397d, 0xa0}, + {0x397c, 0x01}, + {0x397f, 0xa0}, + {0x397e, 0x01}, + {0x3981, 0xa0}, + {0x3980, 0x01}, + {0x3983, 0xa0}, + {0x3982, 0x01}, + {0x3985, 0xa0}, + {0x3984, 0x05}, + {0x3c42, 0x03}, + {0x3012, 0x2b}, + {0x3205, 0x08}, + {0x3204, 0x00}, + {0x310f, 0x00}, + {0x3600, 0x63}, + {0x3630, 0x00}, + {0x3631, 0xFF}, + {0x3632, 0xFF}, + {0x364e, 0x63}, + {0x367e, 0x00}, + {0x367f, 0xFF}, + {0x3680, 0xFF}, + {0x369c, 0x63}, + {0x36cc, 0x00}, + {0x36cd, 0xFF}, + {0x36ce, 0xFF}, + {0x3706, 0x01}, + {0x3707, 0x00}, + {0x3708, 0x01}, + {0x3709, 0x00}, + {0x370a, 0x01}, + {0x370b, 0x00}, + {0x210b, 0x00}, + {0x3021, 0x00}, + {0x3a00, 0x00}, + {0x3a04, 0x03}, + {0x3a05, 0x78}, + {0x3a0a, 0x3a}, + {0x3a2a, 0x54}, + {0x3a2e, 0x10}, + {0x3a14, 0x04}, + {0x3a1c, 0x01}, + {0x3a36, 0x01}, + {0x3a07, 0x56}, + {0x3a35, 0x07}, + {0x3a30, 0x52}, + {0x3a31, 0x35}, + {0x3a19, 0x08}, + {0x3a1a, 0x08}, + {0x3a36, 0x01}, + {0x3006, 0x00}, + {0x3100, 0x00}, + {0x3101, 0x52}, + {0x3109, 0x00}, + {0x310a, 0x00}, + {REG_NULL, 0x00}, +}; + +static const struct mis2031_mode supported_modes[] = { + { + .width = 1920, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .exp_def = 0x0052, + .hts_def = 0x0898, + .vts_def = 0x0465, + .bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10, + .reg_list = mis2031_linear_10_1920x1080_regs, + .hdr_mode = NO_HDR, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, + } +}; + +static const s64 link_freq_menu_items[] = { + MIS2031_LINK_FREQ_185 +}; + +static const char * const mis2031_test_pattern_menu[] = { + "Disabled", + "Vertical Color Bar Type 1", + "Vertical Color Bar Type 2", + "Vertical Color Bar Type 3", + "Vertical Color Bar Type 4" +}; + +/* Write registers up to 4 at a time */ +static int mis2031_write_reg(struct i2c_client *client, u16 reg, + u32 len, u32 val) +{ + u32 buf_i, val_i; + u8 buf[6]; + u8 *val_p; + __be32 val_be; + + if (len > 4) + return -EINVAL; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + + val_be = cpu_to_be32(val); + val_p = (u8 *)&val_be; + buf_i = 2; + val_i = 4 - len; + + while (val_i < 4) + buf[buf_i++] = val_p[val_i++]; + + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + return 0; +} + +static int mis2031_write_array(struct i2c_client *client, + const struct regval *regs) +{ + u32 i; + int ret = 0; + + for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) { + if (regs[i].addr == REG_DELAY) + mdelay(regs[i].val); + else + ret = mis2031_write_reg(client, regs[i].addr, + MIS2031_REG_VALUE_08BIT, regs[i].val); + } + + return ret; +} + +/* Read registers up to 4 at a time */ +static int mis2031_read_reg(struct i2c_client *client, u16 reg, unsigned int len, + u32 *val) +{ + struct i2c_msg msgs[2]; + u8 *data_be_p; + __be32 data_be = 0; + __be16 reg_addr_be = cpu_to_be16(reg); + int ret; + + if (len > 4 || !len) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = (u8 *)®_addr_be; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_be_p[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = be32_to_cpu(data_be); + + return 0; +} + +static void mis2031_set_orientation_reg(struct mis2031 *mis2031, u32 en_flip_mir) +{ + switch (en_flip_mir) { + case 0: + mis2031_write_reg(mis2031->client, 0x3007, MIS2031_REG_VALUE_08BIT, 0x00); + mis2031_write_reg(mis2031->client, 0x3205, MIS2031_REG_VALUE_08BIT, 0x00); + mis2031_write_reg(mis2031->client, 0x3207, MIS2031_REG_VALUE_08BIT, 0x3b); + mis2031_write_reg(mis2031->client, 0x3209, MIS2031_REG_VALUE_08BIT, 0x08); + mis2031_write_reg(mis2031->client, 0x320b, MIS2031_REG_VALUE_08BIT, 0x87); + break; + case 1: + mis2031_write_reg(mis2031->client, 0x3007, MIS2031_REG_VALUE_08BIT, 0x01); + mis2031_write_reg(mis2031->client, 0x3205, MIS2031_REG_VALUE_08BIT, 0x00); + mis2031_write_reg(mis2031->client, 0x3207, MIS2031_REG_VALUE_08BIT, 0x3b); + mis2031_write_reg(mis2031->client, 0x3209, MIS2031_REG_VALUE_08BIT, 0x09); + mis2031_write_reg(mis2031->client, 0x320b, MIS2031_REG_VALUE_08BIT, 0x88); + break; + case 2: + mis2031_write_reg(mis2031->client, 0x3007, MIS2031_REG_VALUE_08BIT, 0x02); + mis2031_write_reg(mis2031->client, 0x3205, MIS2031_REG_VALUE_08BIT, 0x01); + mis2031_write_reg(mis2031->client, 0x3207, MIS2031_REG_VALUE_08BIT, 0x3c); + mis2031_write_reg(mis2031->client, 0x3209, MIS2031_REG_VALUE_08BIT, 0x08); + mis2031_write_reg(mis2031->client, 0x320b, MIS2031_REG_VALUE_08BIT, 0x87); + break; + case 3: + mis2031_write_reg(mis2031->client, 0x3007, MIS2031_REG_VALUE_08BIT, 0x03); + mis2031_write_reg(mis2031->client, 0x3205, MIS2031_REG_VALUE_08BIT, 0x01); + mis2031_write_reg(mis2031->client, 0x3207, MIS2031_REG_VALUE_08BIT, 0x3c); + mis2031_write_reg(mis2031->client, 0x3209, MIS2031_REG_VALUE_08BIT, 0x09); + mis2031_write_reg(mis2031->client, 0x320b, MIS2031_REG_VALUE_08BIT, 0x88); + break; + default: + break; + } +} + +static int mis2031_set_gain_reg(struct mis2031 *mis2031, u32 gain) +{ + u32 coarse_again = 0, coarse_dgian = 0, fine_dgian = 0; + u32 dgain; + int ret = 0; + + if (gain < 32) + gain = 32; + else if (gain > MIS2031_GAIN_MAX - 1) + gain = MIS2031_GAIN_MAX - 1; + + if (gain < 32*64) { + coarse_again = 1024 - (1024*32/gain); + coarse_dgian = 0x1; + fine_dgian = 0; + } else if (gain < MIS2031_GAIN_MAX) { + coarse_again = 1008; + coarse_dgian = (gain/64)/32; + fine_dgian = (gain/64)%32; + } + dgain = ((coarse_dgian << 5) | fine_dgian); + ret = mis2031_write_reg(mis2031->client, + MIS2031_REG_DIG_GAIN, + MIS2031_REG_VALUE_08BIT, + MIS2031_FETCH_AGAIN_H(dgain)); + ret |= mis2031_write_reg(mis2031->client, + MIS2031_REG_DIG_FINE_GAIN, + MIS2031_REG_VALUE_08BIT, + MIS2031_FETCH_AGAIN_L(dgain)); + ret |= mis2031_write_reg(mis2031->client, + MIS2031_REG_ANA_GAIN, + MIS2031_REG_VALUE_08BIT, + MIS2031_FETCH_AGAIN_H(coarse_again)); + ret |= mis2031_write_reg(mis2031->client, + MIS2031_REG_ANA_FINE_GAIN, + MIS2031_REG_VALUE_08BIT, + MIS2031_FETCH_AGAIN_L(coarse_again)); + ret |= mis2031_write_reg(mis2031->client, + MIS2031_REG_GAIN_EXP_VALID, + MIS2031_REG_VALUE_08BIT, + MIS2031_REG_GAIN_EXP_VALID_VAL); + return ret; +} + +static int mis2031_get_reso_dist(const struct mis2031_mode *mode, + struct v4l2_mbus_framefmt *framefmt) +{ + return abs(mode->width - framefmt->width) + + abs(mode->height - framefmt->height); +} + +static const struct mis2031_mode * +mis2031_find_best_fit(struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *framefmt = &fmt->format; + int dist; + int cur_best_fit = 0; + int cur_best_fit_dist = -1; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + dist = mis2031_get_reso_dist(&supported_modes[i], framefmt); + if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } + } + + return &supported_modes[cur_best_fit]; +} + +static int mis2031_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct mis2031 *mis2031 = to_mis2031(sd); + const struct mis2031_mode *mode; + s64 h_blank, vblank_def; + + mutex_lock(&mis2031->mutex); + + mode = mis2031_find_best_fit(fmt); + fmt->format.code = mode->bus_fmt; + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.field = V4L2_FIELD_NONE; + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format; +#else + mutex_unlock(&mis2031->mutex); + return -ENOTTY; +#endif + } else { + mis2031->cur_mode = mode; + h_blank = mode->hts_def - mode->width; + __v4l2_ctrl_modify_range(mis2031->hblank, h_blank, + h_blank, 1, h_blank); + vblank_def = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(mis2031->vblank, vblank_def, + MIS2031_VTS_MAX - mode->height, + 1, vblank_def); + mis2031->cur_fps = mode->max_fps; + } + + mutex_unlock(&mis2031->mutex); + + return 0; +} + +static int mis2031_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct mis2031 *mis2031 = to_mis2031(sd); + const struct mis2031_mode *mode = mis2031->cur_mode; + + mutex_lock(&mis2031->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad); +#else + mutex_unlock(&mis2031->mutex); + return -ENOTTY; +#endif + } else { + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = mode->bus_fmt; + fmt->format.field = V4L2_FIELD_NONE; + /* format info: width/height/data type/virctual channel */ + if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR) + fmt->reserved[0] = mode->vc[fmt->pad]; + else + fmt->reserved[0] = mode->vc[PAD0]; + } + mutex_unlock(&mis2031->mutex); + + return 0; +} + +static int mis2031_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct mis2031 *mis2031 = to_mis2031(sd); + + if (code->index != 0) + return -EINVAL; + code->code = mis2031->cur_mode->bus_fmt; + + return 0; +} + +static int mis2031_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (fse->code != supported_modes[0].bus_fmt) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = supported_modes[fse->index].width; + fse->max_height = supported_modes[fse->index].height; + fse->min_height = supported_modes[fse->index].height; + + return 0; +} + +static int mis2031_enable_test_pattern(struct mis2031 *mis2031, u32 pattern) +{ + u32 val = 0; + int ret = 0; + + ret = mis2031_read_reg(mis2031->client, MIS2031_REG_TEST_PATTERN, + MIS2031_REG_VALUE_08BIT, &val); + if (pattern) + val |= MIS2031_TEST_PATTERN_BIT_MASK; + else + val &= ~MIS2031_TEST_PATTERN_BIT_MASK; + + ret |= mis2031_write_reg(mis2031->client, MIS2031_REG_TEST_PATTERN, + MIS2031_REG_VALUE_08BIT, val); + return ret; +} + +static int mis2031_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct mis2031 *mis2031 = to_mis2031(sd); + const struct mis2031_mode *mode = mis2031->cur_mode; + + if (mis2031->streaming) + fi->interval = mis2031->cur_fps; + else + fi->interval = mode->max_fps; + + return 0; +} + +static int mis2031_g_mbus_config(struct v4l2_subdev *sd, + unsigned int pad_id, + struct v4l2_mbus_config *config) +{ + struct mis2031 *mis2031 = to_mis2031(sd); + const struct mis2031_mode *mode = mis2031->cur_mode; + u32 val = 1 << (MIS2031_LANES - 1) | + V4L2_MBUS_CSI2_CHANNEL_0 | + V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + + if (mode->hdr_mode != NO_HDR) + val |= V4L2_MBUS_CSI2_CHANNEL_1; + if (mode->hdr_mode == HDR_X3) + val |= V4L2_MBUS_CSI2_CHANNEL_2; + + config->type = V4L2_MBUS_CSI2_DPHY; + config->flags = val; + + return 0; +} + +static void mis2031_get_module_inf(struct mis2031 *mis2031, + struct rkmodule_inf *inf) +{ + memset(inf, 0, sizeof(*inf)); + strscpy(inf->base.sensor, MIS2031_NAME, sizeof(inf->base.sensor)); + strscpy(inf->base.module, mis2031->module_name, + sizeof(inf->base.module)); + strscpy(inf->base.lens, mis2031->len_name, sizeof(inf->base.lens)); +} + +static long mis2031_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct mis2031 *mis2031 = to_mis2031(sd); + struct rkmodule_hdr_cfg *hdr; + u32 i, h, w; + long ret = 0; + u32 stream = 0; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + mis2031_get_module_inf(mis2031, (struct rkmodule_inf *)arg); + break; + case RKMODULE_GET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + hdr->esp.mode = HDR_NORMAL_VC; + hdr->hdr_mode = mis2031->cur_mode->hdr_mode; + break; + case RKMODULE_SET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + w = mis2031->cur_mode->width; + h = mis2031->cur_mode->height; + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (w == supported_modes[i].width && + h == supported_modes[i].height && + supported_modes[i].hdr_mode == hdr->hdr_mode) { + mis2031->cur_mode = &supported_modes[i]; + break; + } + } + if (i == ARRAY_SIZE(supported_modes)) { + dev_err(&mis2031->client->dev, + "not find hdr mode:%d %dx%d config\n", + hdr->hdr_mode, w, h); + ret = -EINVAL; + } else { + w = mis2031->cur_mode->hts_def - mis2031->cur_mode->width; + h = mis2031->cur_mode->vts_def - mis2031->cur_mode->height; + __v4l2_ctrl_modify_range(mis2031->hblank, w, w, 1, w); + __v4l2_ctrl_modify_range(mis2031->vblank, h, + MIS2031_VTS_MAX - mis2031->cur_mode->height, 1, h); + } + break; + case RKMODULE_SET_QUICK_STREAM: + + stream = *((u32 *)arg); + + if (stream) + ret = mis2031_write_reg(mis2031->client, MIS2031_REG_CTRL_MODE, + MIS2031_REG_VALUE_08BIT, MIS2031_MODE_STREAMING); + else + ret = mis2031_write_reg(mis2031->client, MIS2031_REG_CTRL_MODE, + MIS2031_REG_VALUE_08BIT, MIS2031_MODE_SW_STANDBY); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +#ifdef CONFIG_COMPAT +static long mis2031_compat_ioctl32(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + void __user *up = compat_ptr(arg); + struct rkmodule_inf *inf; + struct rkmodule_hdr_cfg *hdr; + struct preisp_hdrae_exp_s *hdrae; + long ret; + u32 stream = 0; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + inf = kzalloc(sizeof(*inf), GFP_KERNEL); + if (!inf) { + ret = -ENOMEM; + return ret; + } + + ret = mis2031_ioctl(sd, cmd, inf); + if (!ret) { + if (copy_to_user(up, inf, sizeof(*inf))) + ret = -EFAULT; + } + kfree(inf); + break; + case RKMODULE_GET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = mis2031_ioctl(sd, cmd, hdr); + if (!ret) { + if (copy_to_user(up, hdr, sizeof(*hdr))) + ret = -EFAULT; + } + kfree(hdr); + break; + case RKMODULE_SET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = copy_from_user(hdr, up, sizeof(*hdr)); + if (!ret) + ret = mis2031_ioctl(sd, cmd, hdr); + else + ret = -EFAULT; + kfree(hdr); + break; + case PREISP_CMD_SET_HDRAE_EXP: + hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL); + if (!hdrae) { + ret = -ENOMEM; + return ret; + } + + ret = copy_from_user(hdrae, up, sizeof(*hdrae)); + if (!ret) + ret = mis2031_ioctl(sd, cmd, hdrae); + else + ret = -EFAULT; + kfree(hdrae); + break; + case RKMODULE_SET_QUICK_STREAM: + ret = copy_from_user(&stream, up, sizeof(u32)); + if (!ret) + ret = mis2031_ioctl(sd, cmd, &stream); + else + ret = -EFAULT; + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} +#endif + +static int __mis2031_start_stream(struct mis2031 *mis2031) +{ + int ret; + + if (!mis2031->is_thunderboot) { + ret = mis2031_write_array(mis2031->client, mis2031->cur_mode->reg_list); + if (ret) + return ret; + /* In case these controls are set before streaming */ + ret = __v4l2_ctrl_handler_setup(&mis2031->ctrl_handler); + if (ret) + return ret; + } + + ret = mis2031_write_reg(mis2031->client, MIS2031_REG_CTRL_MODE, + MIS2031_REG_VALUE_08BIT, MIS2031_MODE_STREAMING); + return ret; +} + +static int __mis2031_stop_stream(struct mis2031 *mis2031) +{ + if (mis2031->is_thunderboot) { + mis2031->is_first_streamoff = true; + pm_runtime_put(&mis2031->client->dev); + } + return mis2031_write_reg(mis2031->client, MIS2031_REG_CTRL_MODE, + MIS2031_REG_VALUE_08BIT, MIS2031_MODE_SW_STANDBY); +} + +static int __mis2031_power_on(struct mis2031 *mis2031); +static int mis2031_s_stream(struct v4l2_subdev *sd, int on) +{ + struct mis2031 *mis2031 = to_mis2031(sd); + struct i2c_client *client = mis2031->client; + int ret = 0; + + mutex_lock(&mis2031->mutex); + on = !!on; + if (on == mis2031->streaming) + goto unlock_and_return; + + if (on) { + if (mis2031->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) { + mis2031->is_thunderboot = false; + __mis2031_power_on(mis2031); + } + + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = __mis2031_start_stream(mis2031); + if (ret) { + v4l2_err(sd, "start stream failed while write regs\n"); + pm_runtime_put(&client->dev); + goto unlock_and_return; + } + } else { + __mis2031_stop_stream(mis2031); + pm_runtime_put(&client->dev); + } + + mis2031->streaming = on; + +unlock_and_return: + mutex_unlock(&mis2031->mutex); + + return ret; +} + +static int mis2031_s_power(struct v4l2_subdev *sd, int on) +{ + struct mis2031 *mis2031 = to_mis2031(sd); + struct i2c_client *client = mis2031->client; + int ret = 0; + + mutex_lock(&mis2031->mutex); + + /* If the power state is not modified - no work to do. */ + if (mis2031->power_on == !!on) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + if (!mis2031->is_thunderboot) { + ret = mis2031_write_array(mis2031->client, mis2031_global_regs); + if (ret) { + v4l2_err(sd, "could not set init registers\n"); + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + } + + mis2031->power_on = true; + } else { + pm_runtime_put(&client->dev); + mis2031->power_on = false; + } + +unlock_and_return: + mutex_unlock(&mis2031->mutex); + + return ret; +} + +/* Calculate the delay in us by clock rate and clock cycles */ +static inline u32 mis2031_cal_delay(u32 cycles) +{ + return DIV_ROUND_UP(cycles, MIS2031_XVCLK_FREQ / 1000 / 1000); +} + +static int __mis2031_power_on(struct mis2031 *mis2031) +{ + int ret; + u32 delay_us; + struct device *dev = &mis2031->client->dev; + + if (!IS_ERR_OR_NULL(mis2031->pins_default)) { + ret = pinctrl_select_state(mis2031->pinctrl, + mis2031->pins_default); + if (ret < 0) + dev_err(dev, "could not set pins\n"); + } + ret = clk_set_rate(mis2031->xvclk, MIS2031_XVCLK_FREQ); + if (ret < 0) + dev_warn(dev, "Failed to set xvclk rate (24MHz)\n"); + if (clk_get_rate(mis2031->xvclk) != MIS2031_XVCLK_FREQ) + dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n"); + ret = clk_prepare_enable(mis2031->xvclk); + if (ret < 0) { + dev_err(dev, "Failed to enable xvclk\n"); + return ret; + } + if (mis2031->is_thunderboot) + return 0; + + if (!IS_ERR(mis2031->reset_gpio)) + gpiod_set_value_cansleep(mis2031->reset_gpio, 0); + + ret = regulator_bulk_enable(MIS2031_NUM_SUPPLIES, mis2031->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators\n"); + goto disable_clk; + } + + if (!IS_ERR(mis2031->reset_gpio)) + gpiod_set_value_cansleep(mis2031->reset_gpio, 1); + + usleep_range(500, 1000); + if (!IS_ERR(mis2031->pwdn_gpio)) + gpiod_set_value_cansleep(mis2031->pwdn_gpio, 1); + + if (!IS_ERR(mis2031->reset_gpio)) + usleep_range(6000, 8000); + else + usleep_range(12000, 16000); + + /* 8192 cycles prior to first SCCB transaction */ + delay_us = mis2031_cal_delay(8192); + usleep_range(delay_us, delay_us * 2); + return 0; + +disable_clk: + clk_disable_unprepare(mis2031->xvclk); + + return ret; +} + +static void __mis2031_power_off(struct mis2031 *mis2031) +{ + int ret; + struct device *dev = &mis2031->client->dev; + + clk_disable_unprepare(mis2031->xvclk); + if (mis2031->is_thunderboot) { + if (mis2031->is_first_streamoff) { + mis2031->is_thunderboot = false; + mis2031->is_first_streamoff = false; + } else { + return; + } + } + + if (!IS_ERR(mis2031->pwdn_gpio)) + gpiod_set_value_cansleep(mis2031->pwdn_gpio, 0); + if (!IS_ERR(mis2031->reset_gpio)) + gpiod_set_value_cansleep(mis2031->reset_gpio, 0); + if (!IS_ERR_OR_NULL(mis2031->pins_sleep)) { + ret = pinctrl_select_state(mis2031->pinctrl, + mis2031->pins_sleep); + if (ret < 0) + dev_dbg(dev, "could not set pins\n"); + } + regulator_bulk_disable(MIS2031_NUM_SUPPLIES, mis2031->supplies); +} + +static int __maybe_unused mis2031_runtime_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct mis2031 *mis2031 = to_mis2031(sd); + + return __mis2031_power_on(mis2031); +} + +static int __maybe_unused mis2031_runtime_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct mis2031 *mis2031 = to_mis2031(sd); + + __mis2031_power_off(mis2031); + + return 0; +} + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static int mis2031_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct mis2031 *mis2031 = to_mis2031(sd); + struct v4l2_mbus_framefmt *try_fmt = + v4l2_subdev_get_try_format(sd, fh->pad, 0); + const struct mis2031_mode *def_mode = &supported_modes[0]; + + mutex_lock(&mis2031->mutex); + /* Initialize try_fmt */ + try_fmt->width = def_mode->width; + try_fmt->height = def_mode->height; + try_fmt->code = def_mode->bus_fmt; + try_fmt->field = V4L2_FIELD_NONE; + + mutex_unlock(&mis2031->mutex); + /* No crop or compose */ + + return 0; +} +#endif + +static int mis2031_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +{ + if (fie->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + fie->code = supported_modes[fie->index].bus_fmt; + fie->width = supported_modes[fie->index].width; + fie->height = supported_modes[fie->index].height; + fie->interval = supported_modes[fie->index].max_fps; + fie->reserved[0] = supported_modes[fie->index].hdr_mode; + return 0; +} + +static const struct dev_pm_ops mis2031_pm_ops = { + SET_RUNTIME_PM_OPS(mis2031_runtime_suspend, + mis2031_runtime_resume, NULL) +}; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static const struct v4l2_subdev_internal_ops mis2031_internal_ops = { + .open = mis2031_open, +}; +#endif + +static const struct v4l2_subdev_core_ops mis2031_core_ops = { + .s_power = mis2031_s_power, + .ioctl = mis2031_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = mis2031_compat_ioctl32, +#endif +}; + +static const struct v4l2_subdev_video_ops mis2031_video_ops = { + .s_stream = mis2031_s_stream, + .g_frame_interval = mis2031_g_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops mis2031_pad_ops = { + .enum_mbus_code = mis2031_enum_mbus_code, + .enum_frame_size = mis2031_enum_frame_sizes, + .enum_frame_interval = mis2031_enum_frame_interval, + .get_fmt = mis2031_get_fmt, + .set_fmt = mis2031_set_fmt, + .get_mbus_config = mis2031_g_mbus_config, +}; + +static const struct v4l2_subdev_ops mis2031_subdev_ops = { + .core = &mis2031_core_ops, + .video = &mis2031_video_ops, + .pad = &mis2031_pad_ops, +}; + +static void mis2031_modify_fps_info(struct mis2031 *mis2031) +{ + const struct mis2031_mode *mode = mis2031->cur_mode; + + mis2031->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def / + mis2031->cur_vts; +} + +static int mis2031_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct mis2031 *mis2031 = container_of(ctrl->handler, + struct mis2031, ctrl_handler); + struct i2c_client *client = mis2031->client; + s64 max; + int ret = 0; + u32 val = 0; + + /* Propagate change of current control to all related controls */ + switch (ctrl->id) { + case V4L2_CID_VBLANK: + /* Update max exposure while meeting expected vblanking */ + max = mis2031->cur_mode->height + ctrl->val - 8; + __v4l2_ctrl_modify_range(mis2031->exposure, + mis2031->exposure->minimum, max, + mis2031->exposure->step, + mis2031->exposure->default_value); + break; + } + + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val); + if (mis2031->cur_mode->hdr_mode == NO_HDR) { + val = ctrl->val; + /* 4 least significant bits of expsoure are fractional part */ + ret = mis2031_write_reg(mis2031->client, + MIS2031_REG_EXPOSURE_H, + MIS2031_REG_VALUE_08BIT, + MIS2031_FETCH_EXP_H(val)); + ret |= mis2031_write_reg(mis2031->client, + MIS2031_REG_EXPOSURE_L, + MIS2031_REG_VALUE_08BIT, + MIS2031_FETCH_EXP_L(val)); + ret |= mis2031_write_reg(mis2031->client, + MIS2031_REG_GAIN_EXP_VALID, + MIS2031_REG_VALUE_08BIT, + MIS2031_REG_GAIN_EXP_VALID_VAL); + } + break; + case V4L2_CID_ANALOGUE_GAIN: + dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val); + if (mis2031->cur_mode->hdr_mode == NO_HDR) + ret = mis2031_set_gain_reg(mis2031, ctrl->val); + break; + case V4L2_CID_VBLANK: + dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val); + ret = mis2031_write_reg(mis2031->client, + MIS2031_REG_VTS_H, + MIS2031_REG_VALUE_08BIT, + (ctrl->val + mis2031->cur_mode->height) + >> 8); + ret |= mis2031_write_reg(mis2031->client, + MIS2031_REG_VTS_L, + MIS2031_REG_VALUE_08BIT, + (ctrl->val + mis2031->cur_mode->height) + & 0xff); + mis2031->cur_vts = ctrl->val + mis2031->cur_mode->height; + if (mis2031->cur_vts != mis2031->cur_mode->vts_def) + mis2031_modify_fps_info(mis2031); + break; + case V4L2_CID_TEST_PATTERN: + ret = mis2031_enable_test_pattern(mis2031, ctrl->val); + break; + case V4L2_CID_HFLIP: + ret = mis2031_read_reg(mis2031->client, MIS2031_FLIP_MIRROR_REG, + MIS2031_REG_VALUE_08BIT, &val); + if (ctrl->val) + val |= MIRROR_BIT_MASK; + else + val &= ~MIRROR_BIT_MASK; + mis2031_set_orientation_reg(mis2031, val); + break; + case V4L2_CID_VFLIP: + ret = mis2031_read_reg(mis2031->client, MIS2031_FLIP_MIRROR_REG, + MIS2031_REG_VALUE_08BIT, &val); + if (ctrl->val) + val |= FLIP_BIT_MASK; + else + val &= ~FLIP_BIT_MASK; + mis2031_set_orientation_reg(mis2031, val); + break; + default: + dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", + __func__, ctrl->id, ctrl->val); + break; + } + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops mis2031_ctrl_ops = { + .s_ctrl = mis2031_set_ctrl, +}; + +static int mis2031_initialize_controls(struct mis2031 *mis2031) +{ + const struct mis2031_mode *mode; + struct v4l2_ctrl_handler *handler; + struct v4l2_ctrl *ctrl; + s64 exposure_max, vblank_def; + u32 h_blank; + int ret; + + handler = &mis2031->ctrl_handler; + mode = mis2031->cur_mode; + ret = v4l2_ctrl_handler_init(handler, 9); + if (ret) + return ret; + handler->lock = &mis2031->mutex; + + ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, + 0, 0, link_freq_menu_items); + if (ctrl) + ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, + 0, PIXEL_RATE_WITH_315M_10BIT, 1, PIXEL_RATE_WITH_315M_10BIT); + + h_blank = mode->hts_def - mode->width; + mis2031->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, + h_blank, h_blank, 1, h_blank); + if (mis2031->hblank) + mis2031->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + vblank_def = mode->vts_def - mode->height; + mis2031->vblank = v4l2_ctrl_new_std(handler, &mis2031_ctrl_ops, + V4L2_CID_VBLANK, vblank_def, + MIS2031_VTS_MAX - mode->height, + 1, vblank_def); + mis2031->cur_fps = mode->max_fps; + exposure_max = mode->vts_def - 8; + mis2031->exposure = v4l2_ctrl_new_std(handler, &mis2031_ctrl_ops, + V4L2_CID_EXPOSURE, MIS2031_EXPOSURE_MIN, + exposure_max, MIS2031_EXPOSURE_STEP, + mode->exp_def); + mis2031->anal_gain = v4l2_ctrl_new_std(handler, &mis2031_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, MIS2031_GAIN_MIN, + MIS2031_GAIN_MAX, MIS2031_GAIN_STEP, + MIS2031_GAIN_DEFAULT); + mis2031->test_pattern = v4l2_ctrl_new_std_menu_items(handler, + &mis2031_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(mis2031_test_pattern_menu) - 1, + 0, 0, mis2031_test_pattern_menu); + v4l2_ctrl_new_std(handler, &mis2031_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + v4l2_ctrl_new_std(handler, &mis2031_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + if (handler->error) { + ret = handler->error; + dev_err(&mis2031->client->dev, + "Failed to init controls(%d)\n", ret); + goto err_free_handler; + } + + mis2031->subdev.ctrl_handler = handler; + + return 0; + +err_free_handler: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +static int mis2031_check_sensor_id(struct mis2031 *mis2031, + struct i2c_client *client) +{ + struct device *dev = &mis2031->client->dev; + u32 id = 0; + int ret; + + if (mis2031->is_thunderboot) { + dev_info(dev, "Enable thunderboot mode, skip sensor id check\n"); + return 0; + } + + ret = mis2031_read_reg(client, MIS2031_REG_CHIP_ID, + MIS2031_REG_VALUE_16BIT, &id); + if (id != CHIP_ID) { + dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret); + return -ENODEV; + } + + dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID); + + return 0; +} + +static int mis2031_configure_regulators(struct mis2031 *mis2031) +{ + unsigned int i; + + for (i = 0; i < MIS2031_NUM_SUPPLIES; i++) + mis2031->supplies[i].supply = mis2031_supply_names[i]; + + return devm_regulator_bulk_get(&mis2031->client->dev, + MIS2031_NUM_SUPPLIES, + mis2031->supplies); +} + +static int mis2031_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device_node *node = dev->of_node; + struct mis2031 *mis2031; + struct v4l2_subdev *sd; + char facing[2]; + int ret; + + dev_info(dev, "driver version: %02x.%02x.%02x", + DRIVER_VERSION >> 16, + (DRIVER_VERSION & 0xff00) >> 8, + DRIVER_VERSION & 0x00ff); + + mis2031 = devm_kzalloc(dev, sizeof(*mis2031), GFP_KERNEL); + if (!mis2031) + return -ENOMEM; + + ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, + &mis2031->module_index); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING, + &mis2031->module_facing); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME, + &mis2031->module_name); + ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME, + &mis2031->len_name); + if (ret) { + dev_err(dev, "could not get module information!\n"); + return -EINVAL; + } + + mis2031->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP); + mis2031->client = client; + mis2031->cur_mode = &supported_modes[0]; + + mis2031->xvclk = devm_clk_get(dev, "xvclk"); + if (IS_ERR(mis2031->xvclk)) { + dev_err(dev, "Failed to get xvclk\n"); + return -EINVAL; + } + + if (mis2031->is_thunderboot) { + mis2031->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS); + if (IS_ERR(mis2031->reset_gpio)) + dev_warn(dev, "Failed to get reset-gpios\n"); + + mis2031->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS); + if (IS_ERR(mis2031->pwdn_gpio)) + dev_warn(dev, "Failed to get pwdn-gpios\n"); + } else { + mis2031->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(mis2031->reset_gpio)) + dev_warn(dev, "Failed to get reset-gpios\n"); + + mis2031->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW); + if (IS_ERR(mis2031->pwdn_gpio)) + dev_warn(dev, "Failed to get pwdn-gpios\n"); + } + mis2031->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(mis2031->pinctrl)) { + mis2031->pins_default = + pinctrl_lookup_state(mis2031->pinctrl, + OF_CAMERA_PINCTRL_STATE_DEFAULT); + if (IS_ERR(mis2031->pins_default)) + dev_err(dev, "could not get default pinstate\n"); + + mis2031->pins_sleep = + pinctrl_lookup_state(mis2031->pinctrl, + OF_CAMERA_PINCTRL_STATE_SLEEP); + if (IS_ERR(mis2031->pins_sleep)) + dev_err(dev, "could not get sleep pinstate\n"); + } else { + dev_err(dev, "no pinctrl\n"); + } + + ret = mis2031_configure_regulators(mis2031); + if (ret) { + dev_err(dev, "Failed to get power regulators\n"); + return ret; + } + + mutex_init(&mis2031->mutex); + + sd = &mis2031->subdev; + v4l2_i2c_subdev_init(sd, client, &mis2031_subdev_ops); + ret = mis2031_initialize_controls(mis2031); + if (ret) + goto err_destroy_mutex; + + ret = __mis2031_power_on(mis2031); + if (ret) + goto err_free_handler; + + ret = mis2031_check_sensor_id(mis2031, client); + if (ret) + goto err_power_off; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + sd->internal_ops = &mis2031_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; +#endif +#if defined(CONFIG_MEDIA_CONTROLLER) + mis2031->pad.flags = MEDIA_PAD_FL_SOURCE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = media_entity_pads_init(&sd->entity, 1, &mis2031->pad); + if (ret < 0) + goto err_power_off; +#endif + + memset(facing, 0, sizeof(facing)); + if (strcmp(mis2031->module_facing, "back") == 0) + facing[0] = 'b'; + else + facing[0] = 'f'; + + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", + mis2031->module_index, facing, + MIS2031_NAME, dev_name(sd->dev)); + ret = v4l2_async_register_subdev_sensor_common(sd); + if (ret) { + dev_err(dev, "v4l2 async register subdev failed\n"); + goto err_clean_entity; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + if (mis2031->is_thunderboot) + pm_runtime_get_sync(dev); + else + pm_runtime_idle(dev); + + return 0; + +err_clean_entity: +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif +err_power_off: + __mis2031_power_off(mis2031); +err_free_handler: + v4l2_ctrl_handler_free(&mis2031->ctrl_handler); +err_destroy_mutex: + mutex_destroy(&mis2031->mutex); + + return ret; +} + +static int mis2031_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct mis2031 *mis2031 = to_mis2031(sd); + + v4l2_async_unregister_subdev(sd); +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif + v4l2_ctrl_handler_free(&mis2031->ctrl_handler); + mutex_destroy(&mis2031->mutex); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + __mis2031_power_off(mis2031); + pm_runtime_set_suspended(&client->dev); + + return 0; +} + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id mis2031_of_match[] = { + { .compatible = "imagedesign,mis2031" }, + {}, +}; +MODULE_DEVICE_TABLE(of, mis2031_of_match); +#endif + +static const struct i2c_device_id mis2031_match_id[] = { + { "imagedesign,mis2031", 0 }, + { }, +}; + +static struct i2c_driver mis2031_i2c_driver = { + .driver = { + .name = MIS2031_NAME, + .pm = &mis2031_pm_ops, + .of_match_table = of_match_ptr(mis2031_of_match), + }, + .probe = &mis2031_probe, + .remove = &mis2031_remove, + .id_table = mis2031_match_id, +}; + +static int __init sensor_mod_init(void) +{ + return i2c_add_driver(&mis2031_i2c_driver); +} + +static void __exit sensor_mod_exit(void) +{ + i2c_del_driver(&mis2031_i2c_driver); +} + +#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC) +subsys_initcall(sensor_mod_init); +#else +device_initcall_sync(sensor_mod_init); +#endif +module_exit(sensor_mod_exit); + +MODULE_DESCRIPTION("chengdu image design mis2031 sensor driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/mis4001.c b/drivers/media/i2c/mis4001.c new file mode 100644 index 000000000000..d73e92dd768c --- /dev/null +++ b/drivers/media/i2c/mis4001.c @@ -0,0 +1,1637 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * mis4001 driver + * + * Copyright (C) 2023 Rockchip Electronics Co., Ltd. + * + * V0.0X01.0X01 first version + */ + +//#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01) + +#ifndef V4L2_CID_DIGITAL_GAIN +#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN +#endif + +#define MIS4001_LANES 2 +#define MIS4001_BITS_PER_SAMPLE 10 +#define MIS4001_LINK_FREQ 337500000 +#define PIXEL_RATE_WITH_337M_10BIT (MIS4001_LINK_FREQ * 2 * \ + MIS4001_LANES / MIS4001_BITS_PER_SAMPLE) +#define MIS4001_XVCLK_FREQ 27000000 + +#define MIS4001_CHIP_ID 0x1311 +#define MIS4001_REG_CHIP_ID 0x3000 + +#define MIS4001_REG_CTRL_MODE 0x3006 +#define MIS4001_MODE_SW_STANDBY 0x3 +#define MIS4001_MODE_STREAMING 0x0 + +#define MIS4001_REG_EXPOSURE_H 0x3100 +#define MIS4001_REG_EXPOSURE_L 0x3101 +#define MIS4001_EXPOSURE_MIN 2 +#define MIS4001_EXPOSURE_STEP 1 +#define MIS4001_VTS_MAX 0x7fff + +#define MIS4001_REG_DIG_GAIN 0x3A00 +#define MIS4001_REG_DIG_FINE_GAIN 0x3A01 +#define MIS4001_REG_ANA_GAIN 0x3102 +#define MIS4001_GAIN_MIN 0x0080 +#define MIS4001_GAIN_MAX 32768 +#define MIS4001_GAIN_STEP 1 +#define MIS4001_GAIN_DEFAULT 0x80 + +#define MIS4001_REG_TEST_PATTERN 0x3400 +#define MIS4001_TEST_PATTERN_BIT_MASK BIT(3) + +#define MIS4001_REG_VTS_H 0x310c +#define MIS4001_REG_VTS_L 0x310d + +#define MIS4001_FLIP_MIRROR_REG 0x3007 +#define MIRROR_BIT_MASK BIT(0) +#define FLIP_BIT_MASK BIT(1) + + +#define MIS4001_FETCH_EXP_H(VAL) (((VAL) >> 8) & 0xFF) +#define MIS4001_FETCH_EXP_L(VAL) ((VAL) & 0xFF) + +#define MIS4001_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0xFF) +#define MIS4001_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF) + +#define MIS4001_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x01 : VAL & 0xFE) +#define MIS4001_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x02 : VAL & 0xFD) + +#define REG_NULL 0xFFFF + +#define MIS4001_REG_VALUE_08BIT 1 +#define MIS4001_REG_VALUE_16BIT 2 +#define MIS4001_REG_VALUE_24BIT 3 + +#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" +#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" +#define MIS4001_NAME "mis4001" + + +static const char * const mis4001_supply_names[] = { + "avdd", /* Analog power */ + "dovdd", /* Digital I/O power */ + "dvdd", /* Digital core power */ +}; + +#define MIS4001_NUM_SUPPLIES ARRAY_SIZE(mis4001_supply_names) + +struct regval { + u16 addr; + u8 val; +}; + +struct mis4001_mode { + u32 bus_fmt; + u32 width; + u32 height; + struct v4l2_fract max_fps; + u32 hts_def; + u32 vts_def; + u32 exp_def; + const struct regval *reg_list; + u32 hdr_mode; + u32 vc[PAD_MAX]; +}; + +struct mis4001 { + struct i2c_client *client; + struct clk *xvclk; + struct gpio_desc *reset_gpio; + struct gpio_desc *pwdn_gpio; + struct regulator_bulk_data supplies[MIS4001_NUM_SUPPLIES]; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_sleep; + + struct v4l2_subdev subdev; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *anal_gain; + struct v4l2_ctrl *digi_gain; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *test_pattern; + struct mutex mutex; + bool streaming; + bool power_on; + const struct mis4001_mode *cur_mode; + struct v4l2_fract cur_fps; + u32 module_index; + const char *module_facing; + const char *module_name; + const char *len_name; + u32 cur_vts; +}; + +#define to_mis4001(sd) container_of(sd, struct mis4001, subdev) + +/* + * Xclk 27Mhz + */ +static const struct regval mis4001_global_regs[] = { + {REG_NULL, 0x00}, +}; + +/* + * Xclk 27Mhz + * max_framerate 25fps + * mipi_datarate per lane 337.5Mbps, 2lane + */ +static const struct regval mis4001_linear_10_2560x1440_regs[] = { + {0x300a, 0x01}, + {0x3006, 0x02}, + {0x4220, 0x2b}, + {0x4221, 0x6b}, + {0x4222, 0xab}, + {0x4223, 0xeb}, + {0x3011, 0x2b}, + {0x3302, 0x02}, + {0x3307, 0x64}, + {0x3306, 0x01}, + {0x3309, 0x01}, + {0x3308, 0x03}, + {0x330a, 0x04}, + {0x330b, 0x09}, + {0x310f, 0x68}, + {0x310e, 0x0d}, + {0x310d, 0x25}, + {0x310c, 0x06}, + {0x3115, 0x10}, + {0x3114, 0x00}, + {0x3117, 0x0f}, + {0x3116, 0x0a}, + {0x3111, 0xfc}, + {0x3110, 0x00}, + {0x3113, 0x9d}, + {0x3112, 0x06}, + {0x3128, 0x0f},//FW<4096 FFF + {0x3129, 0xff}, + {0x3012, 0x03}, + {0x3f00, 0x01}, + {0x3f02, 0x07}, + {0x3f01, 0x00}, + {0x3f04, 0x2a}, + {0x3f03, 0x00}, + {0x3f06, 0xa5}, + {0x3f05, 0x04}, + {0x3f08, 0xff}, + {0x3f07, 0x1f}, + {0x3f0a, 0xa4}, + {0x3f09, 0x01}, + {0x3f0c, 0x38}, + {0x3f0b, 0x00}, + {0x3f0e, 0xff}, + {0x3f0d, 0x1f}, + {0x3f10, 0xff}, + {0x3f0f, 0x1f}, + {0x3f13, 0x07}, + {0x3f12, 0x00}, + {0x3f15, 0x9d}, + {0x3f14, 0x01}, + {0x3f17, 0x31}, + {0x3f16, 0x00}, + {0x3f19, 0x73}, + {0x3f18, 0x01}, + {0x3f1b, 0x00}, + {0x3f1a, 0x00}, + {0x3f1d, 0xa9}, + {0x3f1c, 0x04}, + {0x3f1f, 0xff}, + {0x3f1e, 0x1f}, + {0x3f21, 0xff}, + {0x3f20, 0x1f}, + {0x3f23, 0x85}, + {0x3f22, 0x00}, + {0x3f25, 0x27}, + {0x3f24, 0x01}, + {0x3f28, 0x46}, + {0x3f27, 0x00}, + {0x3f2a, 0x07}, + {0x3f29, 0x00}, + {0x3f2c, 0x3f}, + {0x3f2b, 0x00}, + {0x3f2e, 0x70}, + {0x3f2d, 0x01}, + {0x3f30, 0x38}, + {0x3f2f, 0x00}, + {0x3f32, 0x3f}, + {0x3f31, 0x00}, + {0x3f34, 0xd1}, + {0x3f33, 0x00}, + {0x3f36, 0xc0}, + {0x3f35, 0x00}, + {0x3f38, 0x2f}, + {0x3f37, 0x02}, + {0x3f3a, 0x5d}, + {0x3f39, 0x02}, + {0x3f4f, 0x5d}, + {0x3f4e, 0x02}, + {0x3f51, 0x5d}, + {0x3f50, 0x02}, + {0x3f53, 0x5d}, + {0x3f52, 0x02}, + {0x3f55, 0x5d}, + {0x3f54, 0x02}, + {0x3f3c, 0x9a}, + {0x3f3b, 0x00}, + {0x3f3e, 0x09}, + {0x3f3d, 0x04}, + {0x3f40, 0x93}, + {0x3f3f, 0x01}, + {0x3f42, 0x8f}, + {0x3f41, 0x00}, + {0x3f44, 0xb0}, + {0x3f43, 0x04}, + {0x3129, 0x45}, + {0x3128, 0x00}, + {0x312b, 0x4a}, + {0x312a, 0x00}, + {0x312f, 0xb2}, + {0x312e, 0x00}, + {0x3124, 0x09}, + {0x4200, 0x09}, + {0x4201, 0x00}, + {0x4214, 0x60}, + {0x420E, 0x94}, + {0x4240, 0x8d}, + {0x4242, 0x03}, + {0x4224, 0x00}, + {0x4225, 0x0a}, + {0x4226, 0xa0}, + {0x4227, 0x05}, + {0x4228, 0x00}, + {0x4229, 0x0a}, + {0x422a, 0xa0}, + {0x422b, 0x05}, + {0x422c, 0x00}, + {0x422d, 0x0a}, + {0x422e, 0xa0}, + {0x422f, 0x05}, + {0x4230, 0x00}, + {0x4231, 0x0a}, + {0x4232, 0xa0}, + {0x4233, 0x05}, + {0x4509, 0x0f}, + {0x4505, 0x00}, + {0x4501, 0xff}, + {0x4502, 0x33}, + {0x4503, 0x11}, + {0x4501, 0xf0}, + {0x4502, 0x30}, + {0x4503, 0x10}, + {0x3A01, 0xA0}, + {0x401E, 0x3C}, + {0x401d, 0xa0}, + {0x3012, 0x03}, + {0x3E00, 0x00}, + {0x3E01, 0x10}, + {0x400D, 0x30}, + {0x3500, 0x1b}, //1b/13 + {0x3501, 0x03}, + {0x3508, 0x0a}, + {0x3508, 0x04}, + {0x3513, 0x01}, + {0x3514, 0x09}, + {0x3515, 0x0b}, + {0x3702, 0x80}, + {0x3704, 0x80}, + {0x3706, 0x80}, + {0x3708, 0x80}, + {0x400D, 0x30}, //优化奇偶行及行噪 + {0x4004, 0x20}, //RCS CM电流最小优化横带 + {0x4005, 0x0c}, + {0x4009, 0x09}, + {0x400a, 0x48}, + {0x4006, 0x86}, + {0x4019, 0x08}, + {0x4003, 0x0a}, + {0x3f42, 0x58}, + {0x3f49, 0x60}, + {0x3f38, 0x4d}, + {REG_NULL, 0x00}, +}; + +static const struct mis4001_mode supported_modes[] = { + { + .width = 2560, + .height = 1440, + .max_fps = { + .numerator = 10000, + .denominator = 250000, + }, + .exp_def = 0x0040, + .hts_def = 3432, + .vts_def = 1573, + .bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10, + .reg_list = mis4001_linear_10_2560x1440_regs, + .hdr_mode = NO_HDR, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, + } +}; + +static const s64 link_freq_menu_items[] = { + MIS4001_LINK_FREQ +}; + +static const char * const mis4001_test_pattern_menu[] = { + "Disabled", + "Vertical Color Bar Type 1", + "Vertical Color Bar Type 2", + "Vertical Color Bar Type 3", + "Vertical Color Bar Type 4" +}; + +static int mis4001_write_reg(struct i2c_client *client, u16 reg, + u32 len, u32 val) +{ + u32 buf_i, val_i; + u8 buf[6]; + u8 *val_p; + __be32 val_be; + + if (len > 4) + return -EINVAL; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + + val_be = cpu_to_be32(val); + val_p = (u8 *)&val_be; + buf_i = 2; + val_i = 4 - len; + + while (val_i < 4) + buf[buf_i++] = val_p[val_i++]; + + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + return 0; +} + +static int mis4001_write_array(struct i2c_client *client, + const struct regval *regs) +{ + u32 i; + int ret = 0; + + for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) + ret = mis4001_write_reg(client, regs[i].addr, + MIS4001_REG_VALUE_08BIT, regs[i].val); + + return ret; +} + +/* Read registers up to 4 at a time */ +static int mis4001_read_reg(struct i2c_client *client, u16 reg, unsigned int len, + u32 *val) +{ + struct i2c_msg msgs[2]; + u8 *data_be_p; + __be32 data_be = 0; + __be16 reg_addr_be = cpu_to_be16(reg); + int ret; + + if (len > 4 || !len) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = (u8 *)®_addr_be; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_be_p[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = be32_to_cpu(data_be); + + return 0; +} + +static void mis4001_set_orientation_reg(struct mis4001 *mis4001, u32 en_flip_mir) +{ + switch (en_flip_mir) { + case 0: + mis4001_write_reg(mis4001->client, 0x3007, MIS4001_REG_VALUE_08BIT, 0x00); + mis4001_write_reg(mis4001->client, 0x3111, MIS4001_REG_VALUE_08BIT, 0xFC); + mis4001_write_reg(mis4001->client, 0x3113, MIS4001_REG_VALUE_08BIT, 0x9D); + mis4001_write_reg(mis4001->client, 0x3115, MIS4001_REG_VALUE_08BIT, 0x10); + mis4001_write_reg(mis4001->client, 0x3117, MIS4001_REG_VALUE_08BIT, 0x0F); + break; + case 1: + mis4001_write_reg(mis4001->client, 0x3007, MIS4001_REG_VALUE_08BIT, 0x01); + mis4001_write_reg(mis4001->client, 0x3111, MIS4001_REG_VALUE_08BIT, 0xFC); + mis4001_write_reg(mis4001->client, 0x3113, MIS4001_REG_VALUE_08BIT, 0x9D); + mis4001_write_reg(mis4001->client, 0x3115, MIS4001_REG_VALUE_08BIT, 0x11); + mis4001_write_reg(mis4001->client, 0x3117, MIS4001_REG_VALUE_08BIT, 0x10); + break; + case 2: + mis4001_write_reg(mis4001->client, 0x3007, MIS4001_REG_VALUE_08BIT, 0x01); + mis4001_write_reg(mis4001->client, 0x3111, MIS4001_REG_VALUE_08BIT, 0xFD); + mis4001_write_reg(mis4001->client, 0x3113, MIS4001_REG_VALUE_08BIT, 0x9E); + mis4001_write_reg(mis4001->client, 0x3115, MIS4001_REG_VALUE_08BIT, 0x10); + mis4001_write_reg(mis4001->client, 0x3117, MIS4001_REG_VALUE_08BIT, 0x0F); + break; + case 3: + mis4001_write_reg(mis4001->client, 0x3007, MIS4001_REG_VALUE_08BIT, 0x03); + mis4001_write_reg(mis4001->client, 0x3113, MIS4001_REG_VALUE_08BIT, 0XFD); + mis4001_write_reg(mis4001->client, 0x3207, MIS4001_REG_VALUE_08BIT, 0x9E); + mis4001_write_reg(mis4001->client, 0x3115, MIS4001_REG_VALUE_08BIT, 0x11); + mis4001_write_reg(mis4001->client, 0x3117, MIS4001_REG_VALUE_08BIT, 0x0F); + break; + default: + break; + } +} + +static int mis4001_set_gain_reg(struct mis4001 *mis4001, u32 gain) +{ + u8 gain_h, gain_l, u8Reg0x3102, u8Reg0x3a00, u8Reg0x3a01, u8Reg0x4003; + int ret = 0; + + if (gain < 128) + gain = 128; + else if (gain > MIS4001_GAIN_MAX) + gain = MIS4001_GAIN_MAX; + + if (128 <= gain && gain < 256) {//128 * 2 + gain_h = 0; + gain_l = (gain-128)/4 ; + u8Reg0x3a00 = 0; + u8Reg0x3a01 = 160; //128->160, 高亮偏粉 + } else if (gain >= 256 && gain < 512) {//128 * 4 + gain_h = 1; + gain_l = (gain-256)/8; + u8Reg0x3a00 = 0; + u8Reg0x3a01 = 160; + } else if (gain >= 512 && gain < 1024) {//128 * 8 + gain_h = 2; + gain_l = (gain-512)/16; + u8Reg0x3a00 = 0; + u8Reg0x3a01 = 160; + } else if (gain >= 1024 && gain < 2048) {//128 * 16 + gain_h = 3; + gain_l = (gain-1024)/32; + u8Reg0x3a00 = 0; + u8Reg0x3a01 = 160; + } else if (2048 <= gain && gain < 4096) {//128 * 32 Dgain + gain_h = 3; + gain_l = 31; + u8Reg0x3a00 = 0; + u8Reg0x3a01 = ((gain-2048)/16 + 128); + u8Reg0x3a01 = (u8Reg0x3a01<160)?160:u8Reg0x3a01; + } else if (gain >= 4096 && gain < 8192) {//128 * 64 + gain_h = 3; + gain_l = 31; + u8Reg0x3a00 = 1; + u8Reg0x3a01 =((gain-4096)/16); + } else if (gain >= 8192 && gain < 12288) {//128 * 96 + gain_h = 3; + gain_l = 31; + u8Reg0x3a00 = 2; + u8Reg0x3a01 = ((gain-8192)/16); + } else if (gain >= 12288 && gain < 16384) {//128 * 128 + gain_h = 3; + gain_l = 31; + u8Reg0x3a00 = 3; + u8Reg0x3a01 = ((gain-12288)/16); + } else if (gain >= 16384 && gain < 20480) {//128 * 160 + gain_h = 3; + gain_l = 31; + u8Reg0x3a00 = 4; + u8Reg0x3a01 = ((gain-16384)/16); + } else if (gain >= 20480 && gain < 24576) {//128 * 192 + gain_h = 3; + gain_l = 31; + u8Reg0x3a00 = 5; + u8Reg0x3a01 = ((gain-20480)/16); + } else if (gain >= 24576 && gain < 28672) {//128 * 224 + gain_h = 3; + gain_l = 31; + u8Reg0x3a00 = 6; + u8Reg0x3a01 = ((gain-24576)/16); + } else if (gain >= 28672 && gain < 32768) {//128 * 256 + gain_h = 3; + gain_l = 31; + u8Reg0x3a00 = 7; + u8Reg0x3a01 = ((gain-28672)/16); + } else { + gain_h = 3; + gain_l = 31; + u8Reg0x3a00 = 7; + u8Reg0x3a01 = 255; + } + + u8Reg0x3102 = ((gain_h << 5)|gain_l); + + // 竖条纹优化，但低增益下需添加防止太阳黑子逻辑 + if (128 <= gain && gain <= 256) + u8Reg0x4003 = 0xb; + else + u8Reg0x4003 = 0xa; + + ret = mis4001_write_reg(mis4001->client, + 0x4003, + MIS4001_REG_VALUE_08BIT, + u8Reg0x4003); + ret |= mis4001_write_reg(mis4001->client, + MIS4001_REG_DIG_GAIN, + MIS4001_REG_VALUE_08BIT, + u8Reg0x3a00); + ret |= mis4001_write_reg(mis4001->client, + MIS4001_REG_DIG_FINE_GAIN, + MIS4001_REG_VALUE_08BIT, + u8Reg0x3a01); + ret |= mis4001_write_reg(mis4001->client, + MIS4001_REG_ANA_GAIN, + MIS4001_REG_VALUE_08BIT, + u8Reg0x3102); + + return ret; +} + + +static int mis4001_get_reso_dist(const struct mis4001_mode *mode, + struct v4l2_mbus_framefmt *framefmt) +{ + return abs(mode->width - framefmt->width) + + abs(mode->height - framefmt->height); +} + +static const struct mis4001_mode * +mis4001_find_best_fit(struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *framefmt = &fmt->format; + int dist; + int cur_best_fit = 0; + int cur_best_fit_dist = -1; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + dist = mis4001_get_reso_dist(&supported_modes[i], framefmt); + if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } + } + + return &supported_modes[cur_best_fit]; +} + +static int mis4001_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct mis4001 *mis4001 = to_mis4001(sd); + const struct mis4001_mode *mode; + s64 h_blank, vblank_def; + + mutex_lock(&mis4001->mutex); + + mode = mis4001_find_best_fit(fmt); + fmt->format.code = mode->bus_fmt; + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.field = V4L2_FIELD_NONE; + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format; +#else + mutex_unlock(&mis4001->mutex); + return -ENOTTY; +#endif + } else { + mis4001->cur_mode = mode; + h_blank = mode->hts_def - mode->width; + __v4l2_ctrl_modify_range(mis4001->hblank, h_blank, + h_blank, 1, h_blank); + vblank_def = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(mis4001->vblank, vblank_def, + MIS4001_VTS_MAX - mode->height, + 1, vblank_def); + mis4001->cur_fps = mode->max_fps; + } + + mutex_unlock(&mis4001->mutex); + + return 0; +} + +static int mis4001_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct mis4001 *mis4001 = to_mis4001(sd); + const struct mis4001_mode *mode = mis4001->cur_mode; + + mutex_lock(&mis4001->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad); +#else + mutex_unlock(&mis4001->mutex); + return -ENOTTY; +#endif + } else { + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = mode->bus_fmt; + fmt->format.field = V4L2_FIELD_NONE; + /* format info: width/height/data type/virctual channel */ + if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR) + fmt->reserved[0] = mode->vc[fmt->pad]; + else + fmt->reserved[0] = mode->vc[PAD0]; + } + mutex_unlock(&mis4001->mutex); + + return 0; +} + +static int mis4001_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct mis4001 *mis4001 = to_mis4001(sd); + + if (code->index != 0) + return -EINVAL; + code->code = mis4001->cur_mode->bus_fmt; + + return 0; +} + +static int mis4001_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (fse->code != supported_modes[0].bus_fmt) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = supported_modes[fse->index].width; + fse->max_height = supported_modes[fse->index].height; + fse->min_height = supported_modes[fse->index].height; + + return 0; +} + +static int mis4001_enable_test_pattern(struct mis4001 *mis4001, u32 pattern) +{ + u32 val = 0; + int ret = 0; + + ret = mis4001_read_reg(mis4001->client, MIS4001_REG_TEST_PATTERN, + MIS4001_REG_VALUE_08BIT, &val); + if (pattern) + val |= MIS4001_TEST_PATTERN_BIT_MASK; + else + val &= ~MIS4001_TEST_PATTERN_BIT_MASK; + + ret |= mis4001_write_reg(mis4001->client, MIS4001_REG_TEST_PATTERN, + MIS4001_REG_VALUE_08BIT, val); + return ret; +} + +static int mis4001_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct mis4001 *mis4001 = to_mis4001(sd); + const struct mis4001_mode *mode = mis4001->cur_mode; + + if (mis4001->streaming) + fi->interval = mis4001->cur_fps; + else + fi->interval = mode->max_fps; + + return 0; +} + +static int mis4001_g_mbus_config(struct v4l2_subdev *sd, + unsigned int pad_id, + struct v4l2_mbus_config *config) +{ + struct mis4001 *mis4001 = to_mis4001(sd); + const struct mis4001_mode *mode = mis4001->cur_mode; + u32 val = 1 << (MIS4001_LANES - 1) | + V4L2_MBUS_CSI2_CHANNEL_0 | + V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + + if (mode->hdr_mode != NO_HDR) + val |= V4L2_MBUS_CSI2_CHANNEL_1; + if (mode->hdr_mode == HDR_X3) + val |= V4L2_MBUS_CSI2_CHANNEL_2; + + config->type = V4L2_MBUS_CSI2_DPHY; + config->flags = val; + + return 0; +} + +static void mis4001_get_module_inf(struct mis4001 *mis4001, + struct rkmodule_inf *inf) +{ + memset(inf, 0, sizeof(*inf)); + strscpy(inf->base.sensor, MIS4001_NAME, sizeof(inf->base.sensor)); + strscpy(inf->base.module, mis4001->module_name, + sizeof(inf->base.module)); + strscpy(inf->base.lens, mis4001->len_name, sizeof(inf->base.lens)); +} + +static long mis4001_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct mis4001 *mis4001 = to_mis4001(sd); + struct rkmodule_hdr_cfg *hdr; + u32 i, h, w; + long ret = 0; + u32 stream = 0; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + mis4001_get_module_inf(mis4001, (struct rkmodule_inf *)arg); + break; + case RKMODULE_GET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + hdr->esp.mode = HDR_NORMAL_VC; + hdr->hdr_mode = mis4001->cur_mode->hdr_mode; + break; + case RKMODULE_SET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + w = mis4001->cur_mode->width; + h = mis4001->cur_mode->height; + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (w == supported_modes[i].width && + h == supported_modes[i].height && + supported_modes[i].hdr_mode == hdr->hdr_mode) { + mis4001->cur_mode = &supported_modes[i]; + break; + } + } + if (i == ARRAY_SIZE(supported_modes)) { + dev_err(&mis4001->client->dev, + "not find hdr mode:%d %dx%d config\n", + hdr->hdr_mode, w, h); + ret = -EINVAL; + } else { + w = mis4001->cur_mode->hts_def - mis4001->cur_mode->width; + h = mis4001->cur_mode->vts_def - mis4001->cur_mode->height; + __v4l2_ctrl_modify_range(mis4001->hblank, w, w, 1, w); + __v4l2_ctrl_modify_range(mis4001->vblank, h, + MIS4001_VTS_MAX - mis4001->cur_mode->height, 1, h); + } + break; + case RKMODULE_SET_QUICK_STREAM: + + stream = *((u32 *)arg); + + if (stream) + ret = mis4001_write_reg(mis4001->client, MIS4001_REG_CTRL_MODE, + MIS4001_REG_VALUE_08BIT, MIS4001_MODE_STREAMING); + else + ret = mis4001_write_reg(mis4001->client, MIS4001_REG_CTRL_MODE, + MIS4001_REG_VALUE_08BIT, MIS4001_MODE_SW_STANDBY); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +#ifdef CONFIG_COMPAT +static long mis4001_compat_ioctl32(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + void __user *up = compat_ptr(arg); + struct rkmodule_inf *inf; + struct rkmodule_hdr_cfg *hdr; + struct preisp_hdrae_exp_s *hdrae; + long ret; + u32 stream = 0; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + inf = kzalloc(sizeof(*inf), GFP_KERNEL); + if (!inf) { + ret = -ENOMEM; + return ret; + } + + ret = mis4001_ioctl(sd, cmd, inf); + if (!ret) { + if (copy_to_user(up, inf, sizeof(*inf))) + ret = -EFAULT; + } + kfree(inf); + break; + case RKMODULE_GET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = mis4001_ioctl(sd, cmd, hdr); + if (!ret) { + if (copy_to_user(up, hdr, sizeof(*hdr))) + ret = -EFAULT; + } + kfree(hdr); + break; + case RKMODULE_SET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = copy_from_user(hdr, up, sizeof(*hdr)); + if (!ret) + ret = mis4001_ioctl(sd, cmd, hdr); + else + ret = -EFAULT; + kfree(hdr); + break; + case PREISP_CMD_SET_HDRAE_EXP: + hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL); + if (!hdrae) { + ret = -ENOMEM; + return ret; + } + + ret = copy_from_user(hdrae, up, sizeof(*hdrae)); + if (!ret) + ret = mis4001_ioctl(sd, cmd, hdrae); + else + ret = -EFAULT; + kfree(hdrae); + break; + case RKMODULE_SET_QUICK_STREAM: + ret = copy_from_user(&stream, up, sizeof(u32)); + if (!ret) + ret = mis4001_ioctl(sd, cmd, &stream); + else + ret = -EFAULT; + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} +#endif + +static int __mis4001_start_stream(struct mis4001 *mis4001) +{ + int ret; + + ret = mis4001_write_array(mis4001->client, mis4001->cur_mode->reg_list); + if (ret) + return ret; + + /* In case these controls are set before streaming */ + ret = __v4l2_ctrl_handler_setup(&mis4001->ctrl_handler); + if (ret) + return ret; + + return mis4001_write_reg(mis4001->client, MIS4001_REG_CTRL_MODE, + MIS4001_REG_VALUE_08BIT, MIS4001_MODE_STREAMING); +} + +static int __mis4001_stop_stream(struct mis4001 *mis4001) +{ + return mis4001_write_reg(mis4001->client, MIS4001_REG_CTRL_MODE, + MIS4001_REG_VALUE_08BIT, MIS4001_MODE_SW_STANDBY); +} + +static int mis4001_s_stream(struct v4l2_subdev *sd, int on) +{ + struct mis4001 *mis4001 = to_mis4001(sd); + struct i2c_client *client = mis4001->client; + int ret = 0; + + mutex_lock(&mis4001->mutex); + on = !!on; + if (on == mis4001->streaming) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = __mis4001_start_stream(mis4001); + if (ret) { + v4l2_err(sd, "start stream failed while write regs\n"); + pm_runtime_put(&client->dev); + goto unlock_and_return; + } + } else { + __mis4001_stop_stream(mis4001); + pm_runtime_put(&client->dev); + } + + mis4001->streaming = on; + +unlock_and_return: + mutex_unlock(&mis4001->mutex); + + return ret; +} + +static int mis4001_s_power(struct v4l2_subdev *sd, int on) +{ + struct mis4001 *mis4001 = to_mis4001(sd); + struct i2c_client *client = mis4001->client; + int ret = 0; + + mutex_lock(&mis4001->mutex); + + /* If the power state is not modified - no work to do. */ + if (mis4001->power_on == !!on) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = mis4001_write_array(mis4001->client, mis4001_global_regs); + if (ret) { + v4l2_err(sd, "could not set init registers\n"); + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + mis4001->power_on = true; + } else { + pm_runtime_put(&client->dev); + mis4001->power_on = false; + } + +unlock_and_return: + mutex_unlock(&mis4001->mutex); + + return ret; +} + +/* Calculate the delay in us by clock rate and clock cycles */ +static inline u32 mis4001_cal_delay(u32 cycles) +{ + return DIV_ROUND_UP(cycles, MIS4001_XVCLK_FREQ / 1000 / 1000); +} + +static int __mis4001_power_on(struct mis4001 *mis4001) +{ + int ret; + u32 delay_us; + struct device *dev = &mis4001->client->dev; + + if (!IS_ERR_OR_NULL(mis4001->pins_default)) { + ret = pinctrl_select_state(mis4001->pinctrl, + mis4001->pins_default); + if (ret < 0) + dev_err(dev, "could not set pins\n"); + } + ret = clk_set_rate(mis4001->xvclk, MIS4001_XVCLK_FREQ); + if (ret < 0) + dev_warn(dev, "Failed to set xvclk rate (24MHz)\n"); + if (clk_get_rate(mis4001->xvclk) != MIS4001_XVCLK_FREQ) + dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n"); + ret = clk_prepare_enable(mis4001->xvclk); + if (ret < 0) { + dev_err(dev, "Failed to enable xvclk\n"); + return ret; + } + if (!IS_ERR(mis4001->reset_gpio)) + gpiod_set_value_cansleep(mis4001->reset_gpio, 0); + + ret = regulator_bulk_enable(MIS4001_NUM_SUPPLIES, mis4001->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators\n"); + goto disable_clk; + } + + if (!IS_ERR(mis4001->reset_gpio)) + gpiod_set_value_cansleep(mis4001->reset_gpio, 1); + + usleep_range(500, 1000); + if (!IS_ERR(mis4001->pwdn_gpio)) + gpiod_set_value_cansleep(mis4001->pwdn_gpio, 1); + + if (!IS_ERR(mis4001->reset_gpio)) + usleep_range(6000, 8000); + else + usleep_range(12000, 16000); + + /* 8192 cycles prior to first SCCB transaction */ + delay_us = mis4001_cal_delay(8192); + usleep_range(delay_us, delay_us * 2); + + return 0; + +disable_clk: + clk_disable_unprepare(mis4001->xvclk); + + return ret; +} + +static void __mis4001_power_off(struct mis4001 *mis4001) +{ + int ret; + struct device *dev = &mis4001->client->dev; + + if (!IS_ERR(mis4001->pwdn_gpio)) + gpiod_set_value_cansleep(mis4001->pwdn_gpio, 0); + clk_disable_unprepare(mis4001->xvclk); + if (!IS_ERR(mis4001->reset_gpio)) + gpiod_set_value_cansleep(mis4001->reset_gpio, 0); + if (!IS_ERR_OR_NULL(mis4001->pins_sleep)) { + ret = pinctrl_select_state(mis4001->pinctrl, + mis4001->pins_sleep); + if (ret < 0) + dev_dbg(dev, "could not set pins\n"); + } + regulator_bulk_disable(MIS4001_NUM_SUPPLIES, mis4001->supplies); +} + +static int mis4001_runtime_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct mis4001 *mis4001 = to_mis4001(sd); + + return __mis4001_power_on(mis4001); +} + +static int mis4001_runtime_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct mis4001 *mis4001 = to_mis4001(sd); + + __mis4001_power_off(mis4001); + + return 0; +} + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static int mis4001_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct mis4001 *mis4001 = to_mis4001(sd); + struct v4l2_mbus_framefmt *try_fmt = + v4l2_subdev_get_try_format(sd, fh->pad, 0); + const struct mis4001_mode *def_mode = &supported_modes[0]; + + mutex_lock(&mis4001->mutex); + /* Initialize try_fmt */ + try_fmt->width = def_mode->width; + try_fmt->height = def_mode->height; + try_fmt->code = def_mode->bus_fmt; + try_fmt->field = V4L2_FIELD_NONE; + + mutex_unlock(&mis4001->mutex); + /* No crop or compose */ + + return 0; +} +#endif + +static int mis4001_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +{ + if (fie->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + fie->code = supported_modes[fie->index].bus_fmt; + fie->width = supported_modes[fie->index].width; + fie->height = supported_modes[fie->index].height; + fie->interval = supported_modes[fie->index].max_fps; + fie->reserved[0] = supported_modes[fie->index].hdr_mode; + return 0; +} + +static const struct dev_pm_ops mis4001_pm_ops = { + SET_RUNTIME_PM_OPS(mis4001_runtime_suspend, + mis4001_runtime_resume, NULL) +}; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static const struct v4l2_subdev_internal_ops mis4001_internal_ops = { + .open = mis4001_open, +}; +#endif + +static const struct v4l2_subdev_core_ops mis4001_core_ops = { + .s_power = mis4001_s_power, + .ioctl = mis4001_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = mis4001_compat_ioctl32, +#endif +}; + +static const struct v4l2_subdev_video_ops mis4001_video_ops = { + .s_stream = mis4001_s_stream, + .g_frame_interval = mis4001_g_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops mis4001_pad_ops = { + .enum_mbus_code = mis4001_enum_mbus_code, + .enum_frame_size = mis4001_enum_frame_sizes, + .enum_frame_interval = mis4001_enum_frame_interval, + .get_fmt = mis4001_get_fmt, + .set_fmt = mis4001_set_fmt, + .get_mbus_config = mis4001_g_mbus_config, +}; + +static const struct v4l2_subdev_ops mis4001_subdev_ops = { + .core = &mis4001_core_ops, + .video = &mis4001_video_ops, + .pad = &mis4001_pad_ops, +}; + +static void mis4001_modify_fps_info(struct mis4001 *mis4001) +{ + const struct mis4001_mode *mode = mis4001->cur_mode; + + mis4001->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def / + mis4001->cur_vts; +} + +static int mis4001_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct mis4001 *mis4001 = container_of(ctrl->handler, + struct mis4001, ctrl_handler); + struct i2c_client *client = mis4001->client; + s64 max; + int ret = 0; + u32 val = 0; + u32 u32Read0x3102 = 0; + u32 exp_h = 0; + u32 exp_l = 0; + u32 u32Reg0x4007, expmin, expmax, exp_value = 0; + + /* Propagate change of current control to all related controls */ + switch (ctrl->id) { + case V4L2_CID_VBLANK: + /* Update max exposure while meeting expected vblanking */ + max = mis4001->cur_mode->height + ctrl->val - 4; + __v4l2_ctrl_modify_range(mis4001->exposure, + mis4001->exposure->minimum, max, + mis4001->exposure->step, + mis4001->exposure->default_value); + break; + } + + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val); + if (mis4001->cur_mode->hdr_mode == NO_HDR) { + val = ctrl->val; + /* 4 least significant bits of expsoure are fractional part */ + ret = mis4001_write_reg(mis4001->client, + MIS4001_REG_EXPOSURE_H, + MIS4001_REG_VALUE_08BIT, + MIS4001_FETCH_EXP_H(val)); + ret |= mis4001_write_reg(mis4001->client, + MIS4001_REG_EXPOSURE_L, + MIS4001_REG_VALUE_08BIT, + MIS4001_FETCH_EXP_L(val)); + } + break; + case V4L2_CID_ANALOGUE_GAIN: + dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val); + if (mis4001->cur_mode->hdr_mode == NO_HDR) + ret = mis4001_set_gain_reg(mis4001, ctrl->val); + break; + case V4L2_CID_VBLANK: + dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val); + ret = mis4001_write_reg(mis4001->client, + MIS4001_REG_VTS_H, + MIS4001_REG_VALUE_08BIT, + (ctrl->val + mis4001->cur_mode->height) + >> 8); + ret |= mis4001_write_reg(mis4001->client, + MIS4001_REG_VTS_L, + MIS4001_REG_VALUE_08BIT, + (ctrl->val + mis4001->cur_mode->height) + & 0xff); + mis4001->cur_vts = ctrl->val + mis4001->cur_mode->height; + if (mis4001->cur_vts != mis4001->cur_mode->vts_def) + mis4001_modify_fps_info(mis4001); + break; + case V4L2_CID_TEST_PATTERN: + ret = mis4001_enable_test_pattern(mis4001, ctrl->val); + break; + case V4L2_CID_HFLIP: + ret = mis4001_read_reg(mis4001->client, MIS4001_FLIP_MIRROR_REG, + MIS4001_REG_VALUE_08BIT, &val); + if (ctrl->val) + val |= MIRROR_BIT_MASK; + else + val &= ~MIRROR_BIT_MASK; + mis4001_set_orientation_reg(mis4001, val); + break; + case V4L2_CID_VFLIP: + ret = mis4001_read_reg(mis4001->client, MIS4001_FLIP_MIRROR_REG, + MIS4001_REG_VALUE_08BIT, &val); + if (ctrl->val) + val |= FLIP_BIT_MASK; + else + val &= ~FLIP_BIT_MASK; + mis4001_set_orientation_reg(mis4001, val); + break; + default: + dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", + __func__, ctrl->id, ctrl->val); + break; + } + ret = mis4001_read_reg(mis4001->client, + MIS4001_REG_ANA_GAIN, + MIS4001_REG_VALUE_08BIT, + &u32Read0x3102); + ret |= mis4001_read_reg(mis4001->client, + MIS4001_REG_EXPOSURE_H, + MIS4001_REG_VALUE_08BIT, + &exp_h); + ret |= mis4001_read_reg(mis4001->client, + MIS4001_REG_EXPOSURE_L, + MIS4001_REG_VALUE_08BIT, + &exp_l); + exp_value = ((exp_h << 8) | exp_l); + + /* Special strategy: To solve the problem of exposure layering: + * When the exposure is not fully filled, the gain will be increased, + * resulting in layering phenomenon */ + + //When the exposure time is 1/200 (0.005) s, the exp register is 196 + expmin = (mis4001->cur_mode->max_fps.denominator / mis4001->cur_mode->max_fps.numerator) + * mis4001->cur_mode->vts_def * 1/200; + expmax = mis4001->cur_mode->vts_def - expmin; + if((127 == u32Read0x3102) && + ((expmin <= exp_value) && (expmax >= exp_value))) + u32Reg0x4007 = 0x78; + else + u32Reg0x4007 = 0xc4; + + ret = mis4001_write_reg(mis4001->client, + 0x4007, + MIS4001_REG_VALUE_08BIT, + u32Reg0x4007); + + pm_runtime_put(&client->dev); + + return ret; + +} + +static const struct v4l2_ctrl_ops mis4001_ctrl_ops = { + .s_ctrl = mis4001_set_ctrl, +}; + +static int mis4001_initialize_controls(struct mis4001 *mis4001) +{ + const struct mis4001_mode *mode; + struct v4l2_ctrl_handler *handler; + struct v4l2_ctrl *ctrl; + s64 exposure_max, vblank_def; + u32 h_blank; + int ret; + + handler = &mis4001->ctrl_handler; + mode = mis4001->cur_mode; + ret = v4l2_ctrl_handler_init(handler, 9); + if (ret) + return ret; + handler->lock = &mis4001->mutex; + + ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, + 0, 0, link_freq_menu_items); + if (ctrl) + ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, + 0, PIXEL_RATE_WITH_337M_10BIT, 1, PIXEL_RATE_WITH_337M_10BIT); + + h_blank = mode->hts_def - mode->width; + mis4001->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, + h_blank, h_blank, 1, h_blank); + if (mis4001->hblank) + mis4001->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + vblank_def = mode->vts_def - mode->height; + mis4001->vblank = v4l2_ctrl_new_std(handler, &mis4001_ctrl_ops, + V4L2_CID_VBLANK, vblank_def, + MIS4001_VTS_MAX - mode->height, + 1, vblank_def); + mis4001->cur_fps = mode->max_fps; + exposure_max = mode->vts_def - 4; + mis4001->exposure = v4l2_ctrl_new_std(handler, &mis4001_ctrl_ops, + V4L2_CID_EXPOSURE, MIS4001_EXPOSURE_MIN, + exposure_max, MIS4001_EXPOSURE_STEP, + mode->exp_def); + mis4001->anal_gain = v4l2_ctrl_new_std(handler, &mis4001_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, MIS4001_GAIN_MIN, + MIS4001_GAIN_MAX, MIS4001_GAIN_STEP, + MIS4001_GAIN_DEFAULT); + mis4001->test_pattern = v4l2_ctrl_new_std_menu_items(handler, + &mis4001_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(mis4001_test_pattern_menu) - 1, + 0, 0, mis4001_test_pattern_menu); + v4l2_ctrl_new_std(handler, &mis4001_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + v4l2_ctrl_new_std(handler, &mis4001_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + if (handler->error) { + ret = handler->error; + dev_err(&mis4001->client->dev, + "Failed to init controls(%d)\n", ret); + goto err_free_handler; + } + + mis4001->subdev.ctrl_handler = handler; + + return 0; + +err_free_handler: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +/* sensor id check */ +static int mis4001_check_sensor_id(struct mis4001 *mis4001, + struct i2c_client *client) +{ + struct device *dev = &mis4001->client->dev; + u32 id = 0; + int ret; + + ret = mis4001_read_reg(client, MIS4001_REG_CHIP_ID, + MIS4001_REG_VALUE_16BIT, &id); + + if (id != MIS4001_CHIP_ID) { + dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret); + return -ENODEV; + } + + dev_info(dev, "Detected 0x%04x sensor\n", MIS4001_CHIP_ID); + + return 0; +} + +static int mis4001_configure_regulators(struct mis4001 *mis4001) +{ + unsigned int i; + + for (i = 0; i < MIS4001_NUM_SUPPLIES; i++) + mis4001->supplies[i].supply = mis4001_supply_names[i]; + + return devm_regulator_bulk_get(&mis4001->client->dev, + MIS4001_NUM_SUPPLIES, + mis4001->supplies); +} + +static int mis4001_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device_node *node = dev->of_node; + struct mis4001 *mis4001; + struct v4l2_subdev *sd; + char facing[2]; + int ret; + + dev_info(dev, "driver version: %02x.%02x.%02x", + DRIVER_VERSION >> 16, + (DRIVER_VERSION & 0xff00) >> 8, + DRIVER_VERSION & 0x00ff); + + mis4001 = devm_kzalloc(dev, sizeof(*mis4001), GFP_KERNEL); + if (!mis4001) + return -ENOMEM; + + ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, + &mis4001->module_index); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING, + &mis4001->module_facing); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME, + &mis4001->module_name); + ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME, + &mis4001->len_name); + if (ret) { + dev_err(dev, "could not get module information!\n"); + return -EINVAL; + } + + mis4001->client = client; + mis4001->cur_mode = &supported_modes[0]; + + mis4001->xvclk = devm_clk_get(dev, "xvclk"); + if (IS_ERR(mis4001->xvclk)) { + dev_err(dev, "Failed to get xvclk\n"); + return -EINVAL; + } + + mis4001->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(mis4001->reset_gpio)) + dev_warn(dev, "Failed to get reset-gpios\n"); + + mis4001->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW); + if (IS_ERR(mis4001->pwdn_gpio)) + dev_warn(dev, "Failed to get pwdn-gpios\n"); + + mis4001->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(mis4001->pinctrl)) { + mis4001->pins_default = + pinctrl_lookup_state(mis4001->pinctrl, + OF_CAMERA_PINCTRL_STATE_DEFAULT); + if (IS_ERR(mis4001->pins_default)) + dev_err(dev, "could not get default pinstate\n"); + + mis4001->pins_sleep = + pinctrl_lookup_state(mis4001->pinctrl, + OF_CAMERA_PINCTRL_STATE_SLEEP); + if (IS_ERR(mis4001->pins_sleep)) + dev_err(dev, "could not get sleep pinstate\n"); + } else { + dev_err(dev, "no pinctrl\n"); + } + + ret = mis4001_configure_regulators(mis4001); + if (ret) { + dev_err(dev, "Failed to get power regulators\n"); + return ret; + } + + mutex_init(&mis4001->mutex); + + sd = &mis4001->subdev; + v4l2_i2c_subdev_init(sd, client, &mis4001_subdev_ops); + ret = mis4001_initialize_controls(mis4001); + if (ret) + goto err_destroy_mutex; + + ret = __mis4001_power_on(mis4001); + if (ret) + goto err_free_handler; + + ret = mis4001_check_sensor_id(mis4001, client); + if (ret) + goto err_power_off; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + sd->internal_ops = &mis4001_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; +#endif +#if defined(CONFIG_MEDIA_CONTROLLER) + mis4001->pad.flags = MEDIA_PAD_FL_SOURCE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = media_entity_pads_init(&sd->entity, 1, &mis4001->pad); + if (ret < 0) + goto err_power_off; +#endif + + memset(facing, 0, sizeof(facing)); + if (strcmp(mis4001->module_facing, "back") == 0) + facing[0] = 'b'; + else + facing[0] = 'f'; + + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", + mis4001->module_index, facing, + MIS4001_NAME, dev_name(sd->dev)); + ret = v4l2_async_register_subdev_sensor_common(sd); + if (ret) { + dev_err(dev, "v4l2 async register subdev failed\n"); + goto err_clean_entity; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + pm_runtime_idle(dev); + + return 0; + +err_clean_entity: +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif +err_power_off: + __mis4001_power_off(mis4001); +err_free_handler: + v4l2_ctrl_handler_free(&mis4001->ctrl_handler); +err_destroy_mutex: + mutex_destroy(&mis4001->mutex); + + return ret; +} + +static int mis4001_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct mis4001 *mis4001 = to_mis4001(sd); + + v4l2_async_unregister_subdev(sd); +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif + v4l2_ctrl_handler_free(&mis4001->ctrl_handler); + mutex_destroy(&mis4001->mutex); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + __mis4001_power_off(mis4001); + pm_runtime_set_suspended(&client->dev); + + return 0; +} + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id mis4001_of_match[] = { + { .compatible = "imagedesign,mis4001" }, + {}, +}; +MODULE_DEVICE_TABLE(of, mis4001_of_match); +#endif + +static const struct i2c_device_id mis4001_match_id[] = { + { "imagedesign,mis4001", 0 }, + { }, +}; + +static struct i2c_driver mis4001_i2c_driver = { + .driver = { + .name = MIS4001_NAME, + .pm = &mis4001_pm_ops, + .of_match_table = of_match_ptr(mis4001_of_match), + }, + .probe = &mis4001_probe, + .remove = &mis4001_remove, + .id_table = mis4001_match_id, +}; + +static int __init sensor_mod_init(void) +{ + return i2c_add_driver(&mis4001_i2c_driver); +} + +static void __exit sensor_mod_exit(void) +{ + i2c_del_driver(&mis4001_i2c_driver); +} + +device_initcall_sync(sensor_mod_init); +module_exit(sensor_mod_exit); + +MODULE_DESCRIPTION("chengdu image design mis4001 sensor driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/sc2355.c b/drivers/media/i2c/sc2355.c new file mode 100644 index 000000000000..680d279a1702 --- /dev/null +++ b/drivers/media/i2c/sc2355.c @@ -0,0 +1,1522 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SC2355 driver + * + * Copyright (C) 2023 Rockchip Electronics Co., Ltd. + * V0.1.0: MIPI is ok. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00) +#ifndef V4L2_CID_DIGITAL_GAIN +#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN +#endif + +#define MIPI_FREQ_180M 180000000 +#define MIPI_FREQ_360M 360000000 + +#define PIXEL_RATE_WITH_180M (MIPI_FREQ_180M * 2 / 10) +#define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * 2 / 10) + +#define SC2355_XVCLK_FREQ 24000000 + +#define CHIP_ID 0xeb2c +#define SC2355_REG_CHIP_ID 0x3107 + +#define SC2355_REG_CTRL_MODE 0x0100 +#define SC2355_MODE_SW_STANDBY 0x0 +#define SC2355_MODE_STREAMING BIT(0) + +#define SC2355_REG_EXPOSURE 0x3e01 +#define SC2355_EXPOSURE_MIN 6 +#define SC2355_EXPOSURE_STEP 1 +#define SC2355_VTS_MAX 0xffff + +#define SC2355_REG_COARSE_AGAIN 0x3e09 + +#define ANALOG_GAIN_MIN 0x01 +#define ANALOG_GAIN_MAX 0xF8 +#define ANALOG_GAIN_STEP 1 +#define ANALOG_GAIN_DEFAULT 0x1f + +#define SC2355_REG_TEST_PATTERN 0x4501 +#define SC2355_TEST_PATTERN_ENABLE 0xcc +#define SC2355_TEST_PATTERN_DISABLE 0xc4 + +#define SC2355_REG_VTS 0x320e + +#define REG_NULL 0xFFFF + +#define SC2355_REG_VALUE_08BIT 1 +#define SC2355_REG_VALUE_16BIT 2 +#define SC2355_REG_VALUE_24BIT 3 + +#define SC2355_NAME "sc2355" + +#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" +#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" + +#define SC2355_FETCH_3RD_BYTE_EXP(VAL) (((VAL) >> 16) & 0xF) /* 4 Bits */ +#define SC2355_FETCH_2ND_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8 Bits */ +#define SC2355_FETCH_1ST_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 4 Bits */ + +//fps set +#define SC2355_FPS (20) + +//default exposure +#define EXP_DEFAULT_TIME_US (8000) + +#define SC2355_VTS_30_FPS 0x4e2 + +#define TIME_MS 1000 +#define SC2355_VTS (SC2355_VTS_30_FPS * 30 / SC2355_FPS) + +#define SC2355_TIME_TO_EXP_LINE_US(time_us) \ + (uint16_t)(time_us/1000*30*SC2355_VTS_30_FPS/TIME_MS) + +#define SC2355_DEFAULT_EXP_REG \ + SC2355_TIME_TO_EXP_LINE_US(EXP_DEFAULT_TIME_US) + +#define SC2355_FSYNC_RISING_MARGIN_TIME (600)//us +#define SC2355_FSYNC_RISING_MARGIN \ + SC2355_TIME_TO_EXP_LINE_US(SC2355_FSYNC_RISING_MARGIN_TIME) + +#define SC2355_EXP_REG_TO_FSYNC_RISING(exp_reg) \ + (exp_reg - 15 + SC2355_FSYNC_RISING_MARGIN) + +#define SC2355_DEFAULT_FSYNC_RISING \ + SC2355_EXP_REG_TO_FSYNC_RISING(SC2355_DEFAULT_EXP_REG) + +#define SC2355_DEFAULT_FSYNC_FALLING (0x4c0) +#define SC2355_DEFAULT_FSYNC_FALLING_BINNING (0x4c0/2 + 2) +#define SC2355_FSYNC_RISING_REG (0x3217) + +#define SLAVE_MODE +//slave mode max exp time (RB_ROW) +#define EXP_MAX_TIME_US (13*1000) +#define SC2355_SLAVE_RB_ROW SC2355_TIME_TO_EXP_LINE_US(EXP_MAX_TIME_US) + +#define BINNING_MODE + +static const char *const SC2355_supply_names[] = { + "avdd", /* Analog power */ + "dovdd", /* Digital I/O power */ + "dvdd", /* Digital core power */ +}; + +#define SC2355_NUM_SUPPLIES ARRAY_SIZE(SC2355_supply_names) + +enum { + LINK_FREQ_180M_INDEX, + LINK_FREQ_360M_INDEX, +}; + +struct regval { + u16 addr; + u8 val; +}; + +struct SC2355_mode { + u32 width; + u32 height; + struct v4l2_fract max_fps; + u32 hts_def; + u32 vts_def; + u32 exp_def; + u32 link_freq_index; + u64 pixel_rate; + const struct regval *reg_list; + u32 lanes; + u32 bus_fmt; +}; + +struct SC2355 { + struct i2c_client *client; + struct clk *xvclk; + struct gpio_desc *reset_gpio; + struct gpio_desc *pwdn_gpio; + struct regulator_bulk_data supplies[SC2355_NUM_SUPPLIES]; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_sleep; + struct v4l2_subdev subdev; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *anal_gain; + struct v4l2_ctrl *digi_gain; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *test_pattern; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *link_freq; + struct mutex mutex; + struct v4l2_fract cur_fps; + u32 cur_vts; + bool streaming; + bool power_on; + const struct SC2355_mode *cur_mode; + u32 module_index; + const char *module_facing; + const char *module_name; + const char *len_name; +}; + +#define to_SC2355(sd) container_of(sd, struct SC2355, subdev) + +/* + * Xclk 24Mhz + * Pclk 72Mhz + * linelength () + * framelength () + * grabwindow_width 800 + * grabwindow_height 600 + * mipi 1 lane + * max_framerate 30fps + * mipi_datarate per lane 360Mbps + */ +static const struct regval SC2355_1lane_10bit_360Mbps_800x600_30fps_regs[] = { + {0x0103,0x01}, + {0x0100,0x00}, + {0x36e9,0x80}, + {0x36ea,0x0f}, + {0x36eb,0x24}, + {0x36ed,0x14}, + {0x36e9,0x01}, + {0x301f,0x0c}, + {0x303f,0x82}, + {0x3208,0x03}, + {0x3209,0x20}, + {0x320a,0x02}, + {0x320b,0x58}, + {0x3211,0x02}, + {0x3213,0x02}, + {0x3215,0x31}, + {0x3220,0x01}, + {0x3248,0x02}, + {0x3253,0x0a}, + {0x3301,0xff}, + {0x3302,0xff}, + {0x3303,0x10}, + {0x3306,0x28}, + {0x3307,0x02}, + {0x330a,0x00}, + {0x330b,0xb0}, + {0x3318,0x02}, + {0x3320,0x06}, + {0x3321,0x02}, + {0x3326,0x12}, + {0x3327,0x0e}, + {0x3328,0x03}, + {0x3329,0x0f}, + {0x3364,0x4f}, + {0x33b3,0x40}, + {0x33f9,0x2c}, + {0x33fb,0x38}, + {0x33fc,0x0f}, + {0x33fd,0x1f}, + {0x349f,0x03}, + {0x34a6,0x01}, + {0x34a7,0x1f}, + {0x34a8,0x40}, + {0x34a9,0x30}, + {0x34ab,0xa6}, + {0x34ad,0xa6}, + {0x3622,0x60}, + {0x3623,0x40}, + {0x3624,0x61}, + {0x3625,0x08}, + {0x3626,0x03}, + {0x3630,0xa8}, + {0x3631,0x84}, + {0x3632,0x90}, + {0x3633,0x43}, + {0x3634,0x09}, + {0x3635,0x82}, + {0x3636,0x48}, + {0x3637,0xe4}, + {0x3641,0x22}, + {0x3670,0x0f}, + {0x3674,0xc0}, + {0x3675,0xc0}, + {0x3676,0xc0}, + {0x3677,0x86}, + {0x3678,0x88}, + {0x3679,0x8c}, + {0x367c,0x01}, + {0x367d,0x0f}, + {0x367e,0x01}, + {0x367f,0x0f}, + {0x3690,0x63}, + {0x3691,0x63}, + {0x3692,0x73}, + {0x369c,0x01}, + {0x369d,0x1f}, + {0x369e,0x8a}, + {0x369f,0x9e}, + {0x36a0,0xda}, + {0x36a1,0x01}, + {0x36a2,0x03}, + {0x3900,0x0d}, + {0x3904,0x04}, + {0x3905,0x98}, + {0x391b,0x81}, + {0x391c,0x10}, + {0x391d,0x19}, + {0x3933,0x01}, + {0x3934,0x82}, + {0x3940,0x5d}, + {0x3942,0x01}, + {0x3943,0x82}, + {0x3949,0xc8}, + {0x394b,0x64}, + {0x3952,0x02}, + {0x3e00,0x00}, + {0x3e01,0x4d}, + {0x3e02,0xe0}, + {0x4502,0x34}, + {0x4509,0x30}, + {0x450a,0x71}, + {0x4819,0x09}, + {0x481b,0x05}, + {0x481d,0x13}, + {0x481f,0x04}, + {0x4821,0x0a}, + {0x4823,0x05}, + {0x4825,0x04}, + {0x4827,0x05}, + {0x4829,0x08}, + {0x5000,0x46}, + {0x5900,0xf1}, //fix noise + {0x5901,0x04}, + + //vts + {0x320e,(SC2355_VTS>>8)&0xff}, + {0x320f,SC2355_VTS&0xff}, + + //exp + {0x3e00,SC2355_FETCH_3RD_BYTE_EXP(SC2355_DEFAULT_EXP_REG)}, + {0x3e01,SC2355_FETCH_2ND_BYTE_EXP(SC2355_DEFAULT_EXP_REG)}, + {0x3e02,SC2355_FETCH_1ST_BYTE_EXP(SC2355_DEFAULT_EXP_REG)}, + + //[flip] + {0x3221,0x3 << 5}, + + //[gain=1] + {0x3e09,0x00}, + + //fsync +#ifndef SLAVE_MODE + {0x300b,0x44},//FSYNC out + {0x3217,SC2355_DEFAULT_FSYNC_RISING}, + {0x322e,(SC2355_DEFAULT_FSYNC_FALLING_BINNING>>8)&0xff}, + {0x322f,SC2355_DEFAULT_FSYNC_FALLING_BINNING&0xff}, +#else + {0x3222, 0x01 << 1},//slave mode + {0x300a, 0x00 << 2},//input mode + + {0x3230, (SC2355_SLAVE_RB_ROW >> 8)&0xff}, + {0x3231, SC2355_SLAVE_RB_ROW & 0xff}, +#endif + + {REG_NULL, 0x00}, +}; + + +/* + * Xclk 24Mhz + * Pclk 72Mhz + * linelength () + * framelength () + * grabwindow_width 1600 + * grabwindow_height 1200 + * mipi 1 lane + * max_framerate 30fps + */ +static const struct regval SC2355_1lane_10bit_1600x1200_30fps_regs[] = { + {0x0103,0x01}, + {0x0100,0x00}, + + {0x301f,0x01}, + {0x3248,0x02}, + {0x3253,0x0a}, + {0x3301,0xff}, + {0x3302,0xff}, + {0x3303,0x10}, + {0x3306,0x28}, + {0x3307,0x02}, + {0x330a,0x00}, + {0x330b,0xb0}, + {0x3318,0x02}, + {0x3320,0x06}, + {0x3321,0x02}, + {0x3326,0x12}, + {0x3327,0x0e}, + {0x3328,0x03}, + {0x3329,0x0f}, + {0x3364,0x4f}, + {0x33b3,0x40}, + {0x33f9,0x2c}, + {0x33fb,0x38}, + {0x33fc,0x0f}, + {0x33fd,0x1f}, + {0x349f,0x03}, + {0x34a6,0x01}, + {0x34a7,0x1f}, + {0x34a8,0x40}, + {0x34a9,0x30}, + {0x34ab,0xa6}, + {0x34ad,0xa6}, + {0x3622,0x60}, + {0x3623,0x40}, + {0x3624,0x61}, + {0x3625,0x08}, + {0x3626,0x03}, + {0x3630,0xa8}, + {0x3631,0x84}, + {0x3632,0x90}, + {0x3633,0x43}, + {0x3634,0x09}, + {0x3635,0x82}, + {0x3636,0x48}, + {0x3637,0xe4}, + {0x3641,0x22}, + {0x3670,0x0f}, + {0x3674,0xc0}, + {0x3675,0xc0}, + {0x3676,0xc0}, + {0x3677,0x86}, + {0x3678,0x88}, + {0x3679,0x8c}, + {0x367c,0x01}, + {0x367d,0x0f}, + {0x367e,0x01}, + {0x367f,0x0f}, + {0x3690,0x63}, + {0x3691,0x63}, + {0x3692,0x73}, + {0x369c,0x01}, + {0x369d,0x1f}, + {0x369e,0x8a}, + {0x369f,0x9e}, + {0x36a0,0xda}, + {0x36a1,0x01}, + {0x36a2,0x03}, + {0x36e9,0x01}, + {0x36ea,0x0f}, + {0x36eb,0x25}, + {0x36ed,0x04}, + {0x3900,0x0d}, + {0x3904,0x06}, + {0x3905,0x98}, + {0x391b,0x81}, + {0x391c,0x10}, + {0x391d,0x19}, + {0x3933,0x01}, + {0x3934,0x82}, + {0x3940,0x5d}, + {0x3942,0x01}, + {0x3943,0x82}, + {0x3949,0xc8}, + {0x394b,0x64}, + {0x3952,0x02}, + + //vts + {0x320e,(SC2355_VTS>>8)&0xff}, + {0x320f,SC2355_VTS&0xff}, + + {0x3e00, SC2355_FETCH_3RD_BYTE_EXP(SC2355_DEFAULT_EXP_REG)}, + {0x3e01, SC2355_FETCH_2ND_BYTE_EXP(SC2355_DEFAULT_EXP_REG)}, + {0x3e02, SC2355_FETCH_1ST_BYTE_EXP(SC2355_DEFAULT_EXP_REG)}, + {0x4502,0x34}, + {0x4509,0x30}, + {0x450a,0x71}, + + //[flip] + {0x3221,0x3 << 5}, + //[gain=2] + {0x3e09,0x01}, + +#ifndef SLAVE_MODE + {0x300b,0x44},//FSYNC out + {0x3217,SC2355_DEFAULT_FSYNC_RISING}, + {0x322e,(SC2355_DEFAULT_FSYNC_FALLING>>8)&0xff}, + {0x322f,SC2355_DEFAULT_FSYNC_FALLING&0xff}, +#else + {0x3222, 0x01 << 1},//slave mode + {0x300a, 0x00 << 2},//input mode + + {0x3230, (SC2355_SLAVE_RB_ROW >> 8)&0xff},//input mode + {0x3231, SC2355_SLAVE_RB_ROW & 0xff},//input mode +#endif +}; + +static const struct SC2355_mode supported_modes[] = { +#ifdef BINNING_MODE + { + .width = 800, + .height = 600, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .exp_def = SC2355_DEFAULT_EXP_REG, + .hts_def = 0x640, + .vts_def = SC2355_VTS, + .link_freq_index = LINK_FREQ_360M_INDEX, + .pixel_rate = PIXEL_RATE_WITH_360M, + .reg_list = SC2355_1lane_10bit_360Mbps_800x600_30fps_regs, + .lanes = 1, + .bus_fmt = MEDIA_BUS_FMT_Y10_1X10, + }, +#else + { + .width = 1600, + .height = 1200, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .exp_def = SC2355_DEFAULT_EXP_REG, + .hts_def = 0x640, + .vts_def = SC2355_VTS, + .link_freq_index = LINK_FREQ_360M_INDEX, + .pixel_rate = PIXEL_RATE_WITH_360M, + .reg_list = SC2355_1lane_10bit_1600x1200_30fps_regs, + .lanes = 1, + .bus_fmt = MEDIA_BUS_FMT_Y10_1X10, + }, +#endif +}; + +static const char *const SC2355_test_pattern_menu[] = { + "Disabled", + "Vertical Color Bar Type 1", + "Vertical Color Bar Type 2", + "Vertical Color Bar Type 3", + "Vertical Color Bar Type 4" +}; + +static const s64 link_freq_menu_items[] = { + MIPI_FREQ_180M, + MIPI_FREQ_360M, +}; + +/* Write registers up to 4 at a time */ +static int SC2355_write_reg(struct i2c_client *client, + u16 reg, u32 len, u32 val) +{ + u32 buf_i, val_i; + u8 buf[6]; + u8 *val_p; + __be32 val_be; + u32 ret; + + if (len > 4) + return -EINVAL; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + + val_be = cpu_to_be32(val); + val_p = (u8 *)&val_be; + buf_i = 2; + val_i = 4 - len; + + while (val_i < 4) + buf[buf_i++] = val_p[val_i++]; + + ret = i2c_master_send(client, buf, len + 2); + if (ret != len + 2) + return -EIO; + + return 0; +} + +static int SC2355_write_array(struct i2c_client *client, + const struct regval *regs) +{ + u32 i; + int ret = 0; + + for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) { + ret = SC2355_write_reg(client, regs[i].addr, + SC2355_REG_VALUE_08BIT, regs[i].val); + } + + return ret; +} + +/* Read registers up to 4 at a time */ +static int SC2355_read_reg(struct i2c_client *client, + u16 reg, unsigned int len, u32 *val) +{ + struct i2c_msg msgs[2]; + u8 *data_be_p; + __be32 data_be = 0; + __be16 reg_addr_be = cpu_to_be16(reg); + int ret; + + if (len > 4 || !len) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = (u8 *)®_addr_be; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_be_p[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = be32_to_cpu(data_be); + + return 0; +} + +static int SC2355_get_reso_dist(const struct SC2355_mode *mode, + struct v4l2_mbus_framefmt *framefmt) +{ + return abs(mode->width - framefmt->width) + + abs(mode->height - framefmt->height); +} + +static const struct SC2355_mode * +SC2355_find_best_fit(struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *framefmt = &fmt->format; + int dist; + int cur_best_fit = 0; + int cur_best_fit_dist = -1; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + dist = SC2355_get_reso_dist(&supported_modes[i], framefmt); + if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) && + (supported_modes[i].bus_fmt == framefmt->code)) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } + } + return &supported_modes[cur_best_fit]; +} + +static int SC2355_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct SC2355 *SC2355 = to_SC2355(sd); + const struct SC2355_mode *mode; + s64 h_blank, vblank_def; + + mutex_lock(&SC2355->mutex); + + mode = SC2355_find_best_fit(fmt); + fmt->format.code = mode->bus_fmt; + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.field = V4L2_FIELD_NONE; + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format; +#else + mutex_unlock(&SC2355->mutex); + return -ENOTTY; +#endif + } else { + SC2355->cur_mode = mode; + h_blank = mode->hts_def - mode->width; + __v4l2_ctrl_modify_range(SC2355->hblank, h_blank, + h_blank, 1, h_blank); + vblank_def = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(SC2355->vblank, vblank_def, + SC2355_VTS_MAX - mode->height, + 1, vblank_def); + __v4l2_ctrl_s_ctrl_int64(SC2355->pixel_rate, mode->pixel_rate); + __v4l2_ctrl_s_ctrl(SC2355->link_freq, mode->link_freq_index); + SC2355->cur_vts = mode->vts_def; + SC2355->cur_fps = mode->max_fps; + } + + mutex_unlock(&SC2355->mutex); + + return 0; +} + +static int SC2355_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct SC2355 *SC2355 = to_SC2355(sd); + const struct SC2355_mode *mode = SC2355->cur_mode; + + mutex_lock(&SC2355->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad); +#else + mutex_unlock(&SC2355->mutex); + return -ENOTTY; +#endif + } else { + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = mode->bus_fmt; + fmt->format.field = V4L2_FIELD_NONE; + } + mutex_unlock(&SC2355->mutex); + + return 0; +} + +static int SC2355_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct SC2355 *SC2355 = to_SC2355(sd); + + if (code->index != 0) + return -EINVAL; + code->code = SC2355->cur_mode->bus_fmt; + + return 0; +} + +static int SC2355_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (fse->code != supported_modes[fse->index].bus_fmt) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = supported_modes[fse->index].width; + fse->max_height = supported_modes[fse->index].height; + fse->min_height = supported_modes[fse->index].height; + + return 0; +} + +static int SC2355_enable_test_pattern(struct SC2355 *SC2355, u32 pattern) +{ + u32 val; + + if (pattern) + val = (pattern - 1) | SC2355_TEST_PATTERN_ENABLE; + else + val = SC2355_TEST_PATTERN_DISABLE; + + return SC2355_write_reg(SC2355->client, SC2355_REG_TEST_PATTERN, + SC2355_REG_VALUE_08BIT, val); +} + +static void SC2355_get_module_inf(struct SC2355 *SC2355, + struct rkmodule_inf *inf) +{ + memset(inf, 0, sizeof(*inf)); + strscpy(inf->base.sensor, SC2355_NAME, sizeof(inf->base.sensor)); + strscpy(inf->base.module, SC2355->module_name, + sizeof(inf->base.module)); + strscpy(inf->base.lens, SC2355->len_name, sizeof(inf->base.lens)); +} + +static long SC2355_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct SC2355 *SC2355 = to_SC2355(sd); + long ret = 0; + u32 stream = 0; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + SC2355_get_module_inf(SC2355, (struct rkmodule_inf *)arg); + break; + case RKMODULE_SET_QUICK_STREAM: + + stream = *((u32 *)arg); + + if (stream) + ret = SC2355_write_reg(SC2355->client, SC2355_REG_CTRL_MODE, + SC2355_REG_VALUE_08BIT, SC2355_MODE_STREAMING); + else + ret = SC2355_write_reg(SC2355->client, SC2355_REG_CTRL_MODE, + SC2355_REG_VALUE_08BIT, SC2355_MODE_SW_STANDBY); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +#ifdef CONFIG_COMPAT +static long SC2355_compat_ioctl32(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + void __user *up = compat_ptr(arg); + struct rkmodule_inf *inf; + long ret = 0; + u32 stream = 0; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + inf = kzalloc(sizeof(*inf), GFP_KERNEL); + if (!inf) { + ret = -ENOMEM; + return ret; + } + + ret = SC2355_ioctl(sd, cmd, inf); + if (!ret) { + ret = copy_to_user(up, inf, sizeof(*inf)); + if (ret) + ret = -EFAULT; + } + kfree(inf); + break; + case RKMODULE_SET_QUICK_STREAM: + if (copy_from_user(&stream, up, sizeof(u32))) + return -EFAULT; + + ret = SC2355_ioctl(sd, cmd, &stream); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} +#endif + +static int SC2355_set_ctrl_gain(struct SC2355 *SC2355, u32 a_gain) +{ + int ret = 0; + + if (a_gain > 1) + a_gain = ((a_gain + 1) >> 1) << 1; + a_gain -=1; + + ret |= SC2355_write_reg(SC2355->client, + SC2355_REG_COARSE_AGAIN, + SC2355_REG_VALUE_08BIT, + a_gain); + + return ret; +} + + +static int __SC2355_start_stream(struct SC2355 *SC2355) +{ + int ret; + + ret = SC2355_write_array(SC2355->client, SC2355->cur_mode->reg_list); + if (ret) + return ret; + + /* In case these controls are set before streaming */ + mutex_unlock(&SC2355->mutex); + ret = v4l2_ctrl_handler_setup(&SC2355->ctrl_handler); + mutex_lock(&SC2355->mutex); + if (ret) + return ret; + + ret = SC2355_write_reg(SC2355->client, SC2355_REG_CTRL_MODE, + SC2355_REG_VALUE_08BIT, SC2355_MODE_STREAMING); + + return ret; +} + +static int __SC2355_stop_stream(struct SC2355 *SC2355) +{ + return SC2355_write_reg(SC2355->client, SC2355_REG_CTRL_MODE, + SC2355_REG_VALUE_08BIT, SC2355_MODE_SW_STANDBY); +} + +static int SC2355_s_stream(struct v4l2_subdev *sd, int on) +{ + struct SC2355 *SC2355 = to_SC2355(sd); + struct i2c_client *client = SC2355->client; + unsigned int fps; + int ret = 0; + + mutex_lock(&SC2355->mutex); + on = !!on; + if (on == SC2355->streaming) + goto unlock_and_return; + + fps = DIV_ROUND_CLOSEST(SC2355->cur_mode->max_fps.denominator, + SC2355->cur_mode->max_fps.numerator); + + dev_info(&SC2355->client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on, + SC2355->cur_mode->width, + SC2355->cur_mode->height, + fps); + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = __SC2355_start_stream(SC2355); + if (ret) { + v4l2_err(sd, "start stream failed while write regs\n"); + pm_runtime_put(&client->dev); + goto unlock_and_return; + } + } else { + __SC2355_stop_stream(SC2355); + pm_runtime_put(&client->dev); + } + + SC2355->streaming = on; + +unlock_and_return: + mutex_unlock(&SC2355->mutex); + + return ret; +} + +static int SC2355_s_power(struct v4l2_subdev *sd, int on) +{ + struct SC2355 *SC2355 = to_SC2355(sd); + struct i2c_client *client = SC2355->client; + int ret = 0; + + mutex_lock(&SC2355->mutex); + + /* If the power state is not modified - no work to do. */ + if (SC2355->power_on == !!on) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + SC2355->power_on = true; + } else { + pm_runtime_put(&client->dev); + SC2355->power_on = false; + } + +unlock_and_return: + mutex_unlock(&SC2355->mutex); + + return ret; +} + +static int SC2355_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct SC2355 *SC2355 = to_SC2355(sd); + const struct SC2355_mode *mode = SC2355->cur_mode; + + if (SC2355->streaming) + fi->interval = SC2355->cur_fps; + else + fi->interval = mode->max_fps; + + return 0; +} + +/* Calculate the delay in us by clock rate and clock cycles */ +static inline u32 SC2355_cal_delay(u32 cycles) +{ + return DIV_ROUND_UP(cycles, SC2355_XVCLK_FREQ / 1000 / 1000); +} + +static int __SC2355_power_on(struct SC2355 *SC2355) +{ + int ret; + u32 delay_us; + struct device *dev = &SC2355->client->dev; + + if (!IS_ERR_OR_NULL(SC2355->pins_default)) { + ret = pinctrl_select_state(SC2355->pinctrl, + SC2355->pins_default); + if (ret < 0) + dev_err(dev, "could not set pins\n"); + } + + ret = clk_set_rate(SC2355->xvclk, SC2355_XVCLK_FREQ); + if (ret < 0) + dev_warn(dev, "Failed to set xvclk rate (24MHz)\n"); + if (clk_get_rate(SC2355->xvclk) != SC2355_XVCLK_FREQ) + dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n"); + ret = clk_prepare_enable(SC2355->xvclk); + if (ret < 0) { + dev_err(dev, "Failed to enable xvclk\n"); + return ret; + } + + ret = regulator_bulk_enable(SC2355_NUM_SUPPLIES, SC2355->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators\n"); + goto disable_clk; + } + + if (!IS_ERR(SC2355->reset_gpio)) + gpiod_set_value_cansleep(SC2355->reset_gpio, 1); + + usleep_range(1000, 2000); + + if (!IS_ERR(SC2355->pwdn_gpio)) + gpiod_set_value_cansleep(SC2355->pwdn_gpio, 1); + + if (!IS_ERR(SC2355->reset_gpio)) + gpiod_set_value_cansleep(SC2355->reset_gpio, 0); + + /* 8192 cycles prior to first SCCB transaction */ + delay_us = SC2355_cal_delay(8192); + usleep_range(delay_us, delay_us * 2); + + return 0; + +disable_clk: + clk_disable_unprepare(SC2355->xvclk); + + return ret; +} + +static void __SC2355_power_off(struct SC2355 *SC2355) +{ + int ret; + + if (!IS_ERR(SC2355->reset_gpio)) + gpiod_set_value_cansleep(SC2355->reset_gpio, 1); + + if (!IS_ERR(SC2355->pwdn_gpio)) + gpiod_set_value_cansleep(SC2355->pwdn_gpio, 0); + clk_disable_unprepare(SC2355->xvclk); + if (!IS_ERR_OR_NULL(SC2355->pins_sleep)) { + ret = pinctrl_select_state(SC2355->pinctrl, + SC2355->pins_sleep); + if (ret < 0) + dev_dbg(&SC2355->client->dev, "could not set pins\n"); + } + regulator_bulk_disable(SC2355_NUM_SUPPLIES, SC2355->supplies); +} + +static int SC2355_runtime_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct SC2355 *SC2355 = to_SC2355(sd); + + return __SC2355_power_on(SC2355); +} + +static int SC2355_runtime_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct SC2355 *SC2355 = to_SC2355(sd); + + __SC2355_power_off(SC2355); + + return 0; +} + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static int SC2355_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct SC2355 *SC2355 = to_SC2355(sd); + struct v4l2_mbus_framefmt *try_fmt = + v4l2_subdev_get_try_format(sd, fh->pad, 0); + const struct SC2355_mode *def_mode = &supported_modes[0]; + + mutex_lock(&SC2355->mutex); + /* Initialize try_fmt */ + try_fmt->width = def_mode->width; + try_fmt->height = def_mode->height; + try_fmt->code = def_mode->bus_fmt; + try_fmt->field = V4L2_FIELD_NONE; + + mutex_unlock(&SC2355->mutex); + /* No crop or compose */ + + return 0; +} +#endif + +static int SC2355_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +{ + if (fie->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + fie->code = supported_modes[fie->index].bus_fmt; + fie->width = supported_modes[fie->index].width; + fie->height = supported_modes[fie->index].height; + fie->interval = supported_modes[fie->index].max_fps; + return 0; +} + +static int SC2355_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id, + struct v4l2_mbus_config *config) +{ + u32 val = 0; + struct SC2355 *SC2355 = to_SC2355(sd); + + val = 1 << (SC2355->cur_mode->lanes - 1) | + V4L2_MBUS_CSI2_CHANNEL_0 | + V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + config->type = V4L2_MBUS_CSI2_DPHY; + config->flags = val; + + return 0; +} + +static const struct dev_pm_ops SC2355_pm_ops = { + SET_RUNTIME_PM_OPS(SC2355_runtime_suspend, + SC2355_runtime_resume, NULL) +}; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static const struct v4l2_subdev_internal_ops SC2355_internal_ops = { + .open = SC2355_open, +}; +#endif + +static const struct v4l2_subdev_core_ops SC2355_core_ops = { + .s_power = SC2355_s_power, + .ioctl = SC2355_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = SC2355_compat_ioctl32, +#endif +}; + +static const struct v4l2_subdev_video_ops SC2355_video_ops = { + .s_stream = SC2355_s_stream, + .g_frame_interval = SC2355_g_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops SC2355_pad_ops = { + .enum_mbus_code = SC2355_enum_mbus_code, + .enum_frame_size = SC2355_enum_frame_sizes, + .enum_frame_interval = SC2355_enum_frame_interval, + .get_fmt = SC2355_get_fmt, + .set_fmt = SC2355_set_fmt, + .get_mbus_config = SC2355_g_mbus_config, +}; + +static const struct v4l2_subdev_ops SC2355_subdev_ops = { + .core = &SC2355_core_ops, + .video = &SC2355_video_ops, + .pad = &SC2355_pad_ops, +}; + +static void SC2355_modify_fps_info(struct SC2355 *SC2355) +{ + const struct SC2355_mode *mode = SC2355->cur_mode; + + SC2355->cur_fps.denominator = mode->max_fps.denominator * SC2355->cur_vts / + mode->vts_def; +} + +static int SC2355_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct SC2355 *SC2355 = container_of(ctrl->handler, + struct SC2355, ctrl_handler); + struct i2c_client *client = SC2355->client; + s64 max; + int ret = 0; +#ifndef SLAVE_MODE + u16 rising_reg; +#endif + + /* Propagate change of current control to all related controls */ + switch (ctrl->id) { + case V4L2_CID_VBLANK: + /* Update max exposure while meeting expected vblanking */ + max = SC2355->cur_mode->height + ctrl->val - 6; + __v4l2_ctrl_modify_range(SC2355->exposure, + SC2355->exposure->minimum, max, + SC2355->exposure->step, + SC2355->exposure->default_value); + break; + } + + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + /* 4 least significant bits of expsoure are fractional part */ + ret = SC2355_write_reg(SC2355->client, SC2355_REG_EXPOSURE, + SC2355_REG_VALUE_16BIT, ctrl->val << 4); + +#ifndef SLAVE_MODE + /* set fsync rising */ + rising_reg = SC2355_EXP_REG_TO_FSYNC_RISING(ctrl->val); + if (rising_reg > 0xff) { + rising_reg = 0xff; + dev_warn(&client->dev, + "error: rising reg exceed max val 0xff.\n"); + } + + dev_info(&client->dev, "rising: reg:%d\n", rising_reg); + + ret |= SC2355_write_reg(SC2355->client, SC2355_FSYNC_RISING_REG, + SC2355_REG_VALUE_08BIT, rising_reg); +#endif + + break; + case V4L2_CID_ANALOGUE_GAIN: + ret = SC2355_set_ctrl_gain(SC2355, ctrl->val); + break; + case V4L2_CID_VBLANK: + ret = SC2355_write_reg(SC2355->client, SC2355_REG_VTS, + SC2355_REG_VALUE_16BIT, + ctrl->val + SC2355->cur_mode->height); + if (!ret) + SC2355->cur_vts = ctrl->val + SC2355->cur_mode->height; + if (SC2355->cur_vts != SC2355->cur_mode->vts_def) + SC2355_modify_fps_info(SC2355); + break; + case V4L2_CID_TEST_PATTERN: + ret = SC2355_enable_test_pattern(SC2355, ctrl->val); + break; + default: + dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", + __func__, ctrl->id, ctrl->val); + break; + } + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops SC2355_ctrl_ops = { + .s_ctrl = SC2355_set_ctrl, +}; + +static int SC2355_initialize_controls(struct SC2355 *SC2355) +{ + const struct SC2355_mode *mode; + struct v4l2_ctrl_handler *handler; + s64 exposure_max, vblank_def; + u32 h_blank; + int ret; + + handler = &SC2355->ctrl_handler; + mode = SC2355->cur_mode; + ret = v4l2_ctrl_handler_init(handler, 8); + if (ret) + return ret; + handler->lock = &SC2355->mutex; + + SC2355->link_freq = v4l2_ctrl_new_int_menu(handler, + NULL, V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_menu_items) - 1, 0, + link_freq_menu_items); + + SC2355->pixel_rate = v4l2_ctrl_new_std(handler, NULL, + V4L2_CID_PIXEL_RATE, + 0, PIXEL_RATE_WITH_360M, + 1, mode->pixel_rate); + + __v4l2_ctrl_s_ctrl(SC2355->link_freq, mode->pixel_rate); + + h_blank = mode->hts_def - mode->width; + SC2355->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, + h_blank, h_blank, 1, h_blank); + if (SC2355->hblank) + SC2355->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + vblank_def = mode->vts_def - mode->height; + SC2355->cur_vts = mode->vts_def; + SC2355->cur_fps = mode->max_fps; + SC2355->vblank = v4l2_ctrl_new_std(handler, &SC2355_ctrl_ops, + V4L2_CID_VBLANK, vblank_def, + SC2355_VTS_MAX - mode->height, + 1, vblank_def); + + exposure_max = mode->vts_def - 6; + SC2355->exposure = v4l2_ctrl_new_std(handler, &SC2355_ctrl_ops, + V4L2_CID_EXPOSURE, SC2355_EXPOSURE_MIN, + exposure_max, SC2355_EXPOSURE_STEP, + mode->exp_def); + + SC2355->anal_gain = v4l2_ctrl_new_std(handler, &SC2355_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN, + ANALOG_GAIN_MAX, ANALOG_GAIN_STEP, + ANALOG_GAIN_DEFAULT); + + SC2355->test_pattern = v4l2_ctrl_new_std_menu_items(handler, + &SC2355_ctrl_ops, V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(SC2355_test_pattern_menu) - 1, + 0, 0, SC2355_test_pattern_menu); + + if (handler->error) { + ret = handler->error; + dev_err(&SC2355->client->dev, + "Failed to init controls(%d)\n", ret); + goto err_free_handler; + } + + SC2355->subdev.ctrl_handler = handler; + + return 0; + +err_free_handler: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +static int SC2355_check_sensor_id(struct SC2355 *SC2355, + struct i2c_client *client) +{ + struct device *dev = &SC2355->client->dev; + u32 id = 0; + int ret; + + ret = SC2355_read_reg(client, SC2355_REG_CHIP_ID, + SC2355_REG_VALUE_16BIT, &id); + if (ret || id != CHIP_ID) { + dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret); + return -ENODEV; + } + + dev_info(dev, "Detected SC2355 CHIP ID = 0x%04x sensor\n", CHIP_ID); + + return 0; +} + +static int SC2355_configure_regulators(struct SC2355 *SC2355) +{ + unsigned int i; + + for (i = 0; i < SC2355_NUM_SUPPLIES; i++) + SC2355->supplies[i].supply = SC2355_supply_names[i]; + + return devm_regulator_bulk_get(&SC2355->client->dev, + SC2355_NUM_SUPPLIES, + SC2355->supplies); +} + +static int SC2355_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device_node *node = dev->of_node; + struct SC2355 *SC2355; + struct v4l2_subdev *sd; + char facing[2]; + int ret; + + dev_info(dev, "driver version: %02x.%02x.%02x", + DRIVER_VERSION >> 16, + (DRIVER_VERSION & 0xff00) >> 8, + DRIVER_VERSION & 0x00ff); + + SC2355 = devm_kzalloc(dev, sizeof(*SC2355), GFP_KERNEL); + if (!SC2355) + return -ENOMEM; + + ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, + &SC2355->module_index); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING, + &SC2355->module_facing); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME, + &SC2355->module_name); + ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME, + &SC2355->len_name); + if (ret) { + dev_err(dev, "could not get module information!\n"); + return -EINVAL; + } + SC2355->client = client; + SC2355->cur_mode = &supported_modes[0]; + + SC2355->xvclk = devm_clk_get(dev, "xvclk"); + if (IS_ERR(SC2355->xvclk)) { + dev_err(dev, "Failed to get xvclk\n"); + return -EINVAL; + } + + SC2355->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(SC2355->reset_gpio)) + dev_warn(dev, "Failed to get reset-gpios\n"); + + SC2355->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW); + if (IS_ERR(SC2355->pwdn_gpio)) + dev_warn(dev, "Failed to get pwdn-gpios\n"); + ret = SC2355_configure_regulators(SC2355); + if (ret) { + dev_err(dev, "Failed to get power regulators\n"); + return ret; + } + + SC2355->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(SC2355->pinctrl)) { + SC2355->pins_default = + pinctrl_lookup_state(SC2355->pinctrl, + OF_CAMERA_PINCTRL_STATE_DEFAULT); + if (IS_ERR(SC2355->pins_default)) + dev_err(dev, "could not get default pinstate\n"); + + SC2355->pins_sleep = + pinctrl_lookup_state(SC2355->pinctrl, + OF_CAMERA_PINCTRL_STATE_SLEEP); + if (IS_ERR(SC2355->pins_sleep)) + dev_err(dev, "could not get sleep pinstate\n"); + } + mutex_init(&SC2355->mutex); + + sd = &SC2355->subdev; + v4l2_i2c_subdev_init(sd, client, &SC2355_subdev_ops); + ret = SC2355_initialize_controls(SC2355); + if (ret) + goto err_destroy_mutex; + + ret = __SC2355_power_on(SC2355); + if (ret) + goto err_free_handler; + + ret = SC2355_check_sensor_id(SC2355, client); + if (ret) + goto err_power_off; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + sd->internal_ops = &SC2355_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; +#endif +#if defined(CONFIG_MEDIA_CONTROLLER) + SC2355->pad.flags = MEDIA_PAD_FL_SOURCE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = media_entity_pads_init(&sd->entity, 1, &SC2355->pad); + if (ret < 0) + goto err_power_off; +#endif + + memset(facing, 0, sizeof(facing)); + if (strcmp(SC2355->module_facing, "back") == 0) + facing[0] = 'b'; + else + facing[0] = 'f'; + + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", + SC2355->module_index, facing, + SC2355_NAME, dev_name(sd->dev)); + ret = v4l2_async_register_subdev_sensor_common(sd); + if (ret) { + dev_err(dev, "v4l2 async register subdev failed\n"); + goto err_clean_entity; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + pm_runtime_idle(dev); + + return 0; + +err_clean_entity: +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif +err_power_off: + __SC2355_power_off(SC2355); +err_free_handler: + v4l2_ctrl_handler_free(&SC2355->ctrl_handler); +err_destroy_mutex: + mutex_destroy(&SC2355->mutex); + + return ret; +} + +static int SC2355_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct SC2355 *SC2355 = to_SC2355(sd); + + v4l2_async_unregister_subdev(sd); +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif + v4l2_ctrl_handler_free(&SC2355->ctrl_handler); + mutex_destroy(&SC2355->mutex); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + __SC2355_power_off(SC2355); + pm_runtime_set_suspended(&client->dev); + + return 0; +} + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id SC2355_of_match[] = { + { .compatible = "smartsens,sc2355" }, + {}, +}; +MODULE_DEVICE_TABLE(of, SC2355_of_match); +#endif + +static const struct i2c_device_id SC2355_match_id[] = { + { "smartsens,sc2355", 0 }, + { }, +}; + +static struct i2c_driver SC2355_i2c_driver = { + .driver = { + .name = SC2355_NAME, + .pm = &SC2355_pm_ops, + .of_match_table = of_match_ptr(SC2355_of_match), + }, + .probe = &SC2355_probe, + .remove = &SC2355_remove, + .id_table = SC2355_match_id, +}; + +static int __init sensor_mod_init(void) +{ + return i2c_add_driver(&SC2355_i2c_driver); +} + +static void __exit sensor_mod_exit(void) +{ + i2c_del_driver(&SC2355_i2c_driver); +} + +device_initcall_sync(sensor_mod_init); +module_exit(sensor_mod_exit); + +MODULE_DESCRIPTION("Smartsens SC2355 sensor driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/sc5336.c b/drivers/media/i2c/sc5336.c index eb0b925cd7d2..9420ac158fbe 100644 --- a/drivers/media/i2c/sc5336.c +++ b/drivers/media/i2c/sc5336.c @@ -51,7 +51,7 @@ #define SC5336_REG_EXPOSURE_H 0x3e00 #define SC5336_REG_EXPOSURE_M 0x3e01 #define SC5336_REG_EXPOSURE_L 0x3e02 -#define SC5336_EXPOSURE_MIN 1 +#define SC5336_EXPOSURE_MIN 2 #define SC5336_EXPOSURE_STEP 1 #define SC5336_VTS_MAX 0x7fff @@ -244,7 +244,7 @@ static const struct regval sc5336_linear_10_2880x1620_regs[] = { {0x3633, 0x33}, {0x3638, 0xcf}, {0x363f, 0xc0}, - {0x3641, 0x20}, + {0x3641, 0x38}, {0x3670, 0x56}, {0x3674, 0xc0}, {0x3675, 0xa0}, @@ -287,6 +287,7 @@ static const struct regval sc5336_linear_10_2880x1620_regs[] = { {0x37fb, 0x24}, {0x37fc, 0x01}, {0x37fd, 0x36}, + {0x3900, 0x0d}, {0x3901, 0x00}, {0x3904, 0x04}, {0x3905, 0x8c}, @@ -866,6 +867,7 @@ static long sc5336_compat_ioctl32(struct v4l2_subdev *sd, static int __sc5336_start_stream(struct sc5336 *sc5336) { int ret; + u32 chip_version = 0; if (!sc5336->is_thunderboot) { ret = sc5336_write_array(sc5336->client, sc5336->cur_mode->reg_list); @@ -877,6 +879,22 @@ static int __sc5336_start_stream(struct sc5336 *sc5336) if (ret) return ret; } + ret = sc5336_read_reg(sc5336->client, 0x3040, SC5336_REG_VALUE_08BIT, &chip_version); + if (chip_version == 0x00) { + ret |= sc5336_write_reg(sc5336->client, 0x3258, SC5336_REG_VALUE_08BIT, 0x0c); + ret |= sc5336_write_reg(sc5336->client, 0x3249, SC5336_REG_VALUE_08BIT, 0x0b); + ret |= sc5336_write_reg(sc5336->client, 0x3934, SC5336_REG_VALUE_08BIT, 0x0a); + ret |= sc5336_write_reg(sc5336->client, 0x3935, SC5336_REG_VALUE_08BIT, 0x00); + ret |= sc5336_write_reg(sc5336->client, 0x3937, SC5336_REG_VALUE_08BIT, 0x75); + } else if (chip_version == 0x03) { + ret |= sc5336_write_reg(sc5336->client, 0x3258, SC5336_REG_VALUE_08BIT, 0x08); + ret |= sc5336_write_reg(sc5336->client, 0x3249, SC5336_REG_VALUE_08BIT, 0x07); + ret |= sc5336_write_reg(sc5336->client, 0x3934, SC5336_REG_VALUE_08BIT, 0x05); + ret |= sc5336_write_reg(sc5336->client, 0x3935, SC5336_REG_VALUE_08BIT, 0x07); + ret |= sc5336_write_reg(sc5336->client, 0x3937, SC5336_REG_VALUE_08BIT, 0x74); + } + if (ret) + return ret; return sc5336_write_reg(sc5336->client, SC5336_REG_CTRL_MODE, SC5336_REG_VALUE_08BIT, SC5336_MODE_STREAMING); diff --git a/drivers/media/platform/rockchip/cif/capture.c b/drivers/media/platform/rockchip/cif/capture.c index 88f217231fb9..7b5c7ee30fc2 100644 --- a/drivers/media/platform/rockchip/cif/capture.c +++ b/drivers/media/platform/rockchip/cif/capture.c @@ -4506,12 +4506,55 @@ void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num) struct rkcif_rx_buffer *buf; struct rkcif_device *dev = stream->cifdev; struct sditf_priv *priv = dev->sditf[0]; + struct v4l2_subdev *sd; int i = 0; unsigned long flags; + phys_addr_t resmem_free_start; + phys_addr_t resmem_free_end; + u32 share_head_size = 0; if (!priv) return; + sd = get_rkisp_sd(dev->sditf[0]); + if (!sd) + return; + + if (dev->is_rtt_suspend && dev->is_thunderboot) { + stream->curr_buf_toisp = NULL; + stream->next_buf_toisp = NULL; + INIT_LIST_HEAD(&stream->rx_buf_head); + + for (i = 0; i < buf_num; i++) { + buf = &stream->rx_buf[i]; + if (buf->dbufs.is_init) + v4l2_subdev_call(sd, core, ioctl, + RKISP_VICAP_CMD_RX_BUFFER_FREE, &buf->dbufs); + buf->dummy.is_free = true; + } + + if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) { + share_head_size = dev->thunderboot_sensor_num * sizeof(struct rkisp32_thunderboot_resmem_head); + if (share_head_size != dev->share_mem_size) + v4l2_info(&stream->cifdev->v4l2_dev, + "share mem head error, rtt head size %d, arm head size %d\n", + dev->share_mem_size, share_head_size); + resmem_free_start = dev->resmem_pa + share_head_size + dev->nr_buf_size; + resmem_free_end = dev->resmem_pa + dev->resmem_size; + v4l2_info(&stream->cifdev->v4l2_dev, + "free reserved mem start 0x%x, end 0x%x, share_head_size 0x%x, nr_buf_size 0x%x\n", + (u32)resmem_free_start, (u32)resmem_free_end, share_head_size, dev->nr_buf_size); + free_reserved_area(phys_to_virt(resmem_free_start), + phys_to_virt(resmem_free_end), + -1, "rkisp_thunderboot"); + } + atomic_set(&stream->buf_cnt, 0); + stream->total_buf_num = 0; + stream->rx_buf_num = 0; + + return; + } + spin_lock_irqsave(&stream->vbq_lock, flags); stream->curr_buf_toisp = NULL; stream->next_buf_toisp = NULL; @@ -4524,6 +4567,9 @@ void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num) buf = &stream->rx_buf[i]; if (buf->dummy.is_free) continue; + if (buf->dbufs.is_init) + v4l2_subdev_call(sd, core, ioctl, + RKISP_VICAP_CMD_RX_BUFFER_FREE, &buf->dbufs); if (!dev->is_thunderboot) rkcif_free_buffer(dev, &buf->dummy); else @@ -4531,6 +4577,7 @@ void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num) atomic_dec(&stream->buf_cnt); stream->total_buf_num--; } + stream->rx_buf_num = 0; if (dev->is_thunderboot) { spin_unlock_irqrestore(&dev->buffree_lock, flags); @@ -4541,6 +4588,7 @@ void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num) "free rx_buf, buf_num %d\n", buf_num); } +static void rkcif_get_resmem_head(struct rkcif_device *cif_dev); int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num) { struct rkcif_device *dev = stream->cifdev; @@ -4588,10 +4636,12 @@ int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num) dummy->is_need_vaddr = true; dummy->is_need_dbuf = true; if (dev->is_thunderboot) { + if (i == 0) + rkcif_get_resmem_head(dev); buf->buf_idx = i; ret = rkcif_alloc_reserved_mem_buf(dev, buf); if (ret) { - priv->buf_num = i; + stream->rx_buf_num = i; v4l2_info(&dev->v4l2_dev, "reserved mem support alloc buf num %d, require buf num %d\n", i, buf_num); @@ -4604,7 +4654,7 @@ int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num) } else { ret = rkcif_alloc_buffer(dev, dummy); if (ret) { - priv->buf_num = i; + stream->rx_buf_num = i; v4l2_info(&dev->v4l2_dev, "alloc buf num %d, require buf num %d\n", i, buf_num); @@ -4627,10 +4677,10 @@ int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num) } i++; if (!dev->is_thunderboot && i >= buf_num) { - priv->buf_num = buf_num; + stream->rx_buf_num = buf_num; break; } else if (i >= RKISP_VICAP_BUF_CNT_MAX) { - priv->buf_num = i; + stream->rx_buf_num = i; v4l2_info(&dev->v4l2_dev, "reserved mem alloc buf num %d\n", i); break; @@ -4639,9 +4689,9 @@ int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num) "init rx_buf,dma_addr 0x%llx size: 0x%x\n", (u64)dummy->dma_addr, pixm->plane_fmt[0].sizeimage); } - if (priv->buf_num) { - stream->total_buf_num = priv->buf_num; - atomic_set(&stream->buf_cnt, priv->buf_num); + if (stream->rx_buf_num) { + stream->total_buf_num = stream->rx_buf_num; + atomic_set(&stream->buf_cnt, stream->rx_buf_num); return 0; } else { return -EINVAL; @@ -6559,6 +6609,7 @@ void rkcif_stream_init(struct rkcif_device *dev, u32 id) stream->is_stop_capture = false; stream->is_single_cap = false; atomic_set(&stream->buf_cnt, 0); + stream->rx_buf_num = 0; } static int rkcif_fh_open(struct file *filp) @@ -10303,10 +10354,14 @@ static void rkcif_get_resmem_head(struct rkcif_device *cif_dev) head = &tmp->head; cif_dev->resume_mode = head->rtt_mode; + cif_dev->nr_buf_size = head->nr_buf_size; + cif_dev->share_mem_size = head->share_mem_size; + cif_dev->thunderboot_sensor_num = head->camera_num; } } v4l2_err(&cif_dev->v4l2_dev, - "get camera index %02x, resume_mode 0x%x\n", cam_idx, cif_dev->resume_mode); + "get camera index %02x, resume_mode 0x%x, nr_buf_size %d\n", + cam_idx, cif_dev->resume_mode, cif_dev->nr_buf_size); } static int rkcif_subdevs_set_power(struct rkcif_device *cif_dev, int on) @@ -10551,20 +10606,31 @@ int rkcif_stream_resume(struct rkcif_device *cif_dev, int mode) } spin_unlock_irqrestore(&stream->vbq_lock, flags); + if (priv) { - if (capture_mode == RKCIF_STREAM_MODE_TOISP) + if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE) { sditf_change_to_online(priv); - else + if (cif_dev->resume_mode == RKISP_RTT_MODE_MULTI_FRAME && + stream->rx_buf_num && + (priv->hdr_cfg.hdr_mode == NO_HDR || + (priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 1) || + (priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id == 2))) + rkcif_free_rx_buf(stream, priv->buf_num); + else if (!stream->rx_buf_num && + ((priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 0) || + (priv->hdr_cfg.hdr_mode == HDR_X3 && (stream->id == 0 || stream->id == 1)))) + rkcif_init_rx_buf(stream, 1); + } else { sditf_disable_immediately(priv); + if (!stream->rx_buf_num && + capture_mode == RKCIF_STREAM_MODE_TOISP_RDBK) { + if (cif_dev->resume_mode == RKISP_RTT_MODE_ONE_FRAME) + rkcif_init_rx_buf(stream, 1); + else + rkcif_init_rx_buf(stream, priv->buf_num); + } + } } - if (!stream->total_buf_num && priv && - (capture_mode == RKCIF_STREAM_MODE_TOISP_RDBK || - (capture_mode == RKCIF_STREAM_MODE_TOISP && - ((priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 0) || - (priv->hdr_cfg.hdr_mode == HDR_X3 && (stream->id == 0 || stream->id == 1)))))) - rkcif_init_rx_buf(stream, 1); - if (priv && cif_dev->resume_mode == RKISP_RTT_MODE_MULTI_FRAME && stream->total_buf_num) - rkcif_init_rx_buf(stream, priv->buf_num); stream->lack_buf_cnt = 0; if (cif_dev->active_sensor && diff --git a/drivers/media/platform/rockchip/cif/dev.h b/drivers/media/platform/rockchip/cif/dev.h index 5122ec706f16..9fbd5bb7b6ef 100644 --- a/drivers/media/platform/rockchip/cif/dev.h +++ b/drivers/media/platform/rockchip/cif/dev.h @@ -530,6 +530,7 @@ struct rkcif_stream { struct rkcif_rx_buffer rx_buf[RKISP_VICAP_BUF_CNT_MAX]; struct list_head rx_buf_head; int total_buf_num; + int rx_buf_num; u64 line_int_cnt; int lack_buf_cnt; unsigned int buf_wake_up_cnt; @@ -894,6 +895,9 @@ struct rkcif_device { struct rkcif_err_state_work err_state_work; struct rkcif_sensor_work sensor_work; int resume_mode; + u32 nr_buf_size; + u32 share_mem_size; + u32 thunderboot_sensor_num; int sensor_state; }; diff --git a/drivers/media/platform/rockchip/cif/subdev-itf.c b/drivers/media/platform/rockchip/cif/subdev-itf.c index c60bebcfa817..a0ad4026f81d 100644 --- a/drivers/media/platform/rockchip/cif/subdev-itf.c +++ b/drivers/media/platform/rockchip/cif/subdev-itf.c @@ -278,14 +278,14 @@ static void sditf_free_buf(struct sditf_priv *priv) struct rkcif_device *cif_dev = priv->cif_dev; if (priv->hdr_cfg.hdr_mode == HDR_X2) { - rkcif_free_rx_buf(&cif_dev->stream[0], priv->buf_num); - rkcif_free_rx_buf(&cif_dev->stream[1], priv->buf_num); + rkcif_free_rx_buf(&cif_dev->stream[0], cif_dev->stream[0].rx_buf_num); + rkcif_free_rx_buf(&cif_dev->stream[1], cif_dev->stream[1].rx_buf_num); } else if (priv->hdr_cfg.hdr_mode == HDR_X3) { - rkcif_free_rx_buf(&cif_dev->stream[0], priv->buf_num); - rkcif_free_rx_buf(&cif_dev->stream[1], priv->buf_num); - rkcif_free_rx_buf(&cif_dev->stream[2], priv->buf_num); + rkcif_free_rx_buf(&cif_dev->stream[0], cif_dev->stream[0].rx_buf_num); + rkcif_free_rx_buf(&cif_dev->stream[1], cif_dev->stream[1].rx_buf_num); + rkcif_free_rx_buf(&cif_dev->stream[2], cif_dev->stream[2].rx_buf_num); } else { - rkcif_free_rx_buf(&cif_dev->stream[0], priv->buf_num); + rkcif_free_rx_buf(&cif_dev->stream[0], cif_dev->stream[0].rx_buf_num); } if (cif_dev->is_thunderboot) { cif_dev->wait_line_cache = 0; @@ -617,22 +617,26 @@ void sditf_change_to_online(struct sditf_priv *priv) sditf_channel_enable(priv, 0); sditf_channel_enable(priv, 1); } - if (priv->hdr_cfg.hdr_mode == NO_HDR) { - rkcif_free_rx_buf(&cif_dev->stream[0], priv->buf_num); - cif_dev->stream[0].is_line_wake_up = false; - } else if (priv->hdr_cfg.hdr_mode == HDR_X2) { - rkcif_free_rx_buf(&cif_dev->stream[1], priv->buf_num); - cif_dev->stream[0].is_line_wake_up = false; - cif_dev->stream[1].is_line_wake_up = false; - } else if (priv->hdr_cfg.hdr_mode == HDR_X3) { - rkcif_free_rx_buf(&cif_dev->stream[2], priv->buf_num); - cif_dev->stream[0].is_line_wake_up = false; - cif_dev->stream[1].is_line_wake_up = false; - cif_dev->stream[2].is_line_wake_up = false; + + if (cif_dev->is_thunderboot) { + if (priv->hdr_cfg.hdr_mode == NO_HDR) { + rkcif_free_rx_buf(&cif_dev->stream[0], cif_dev->stream[0].rx_buf_num); + cif_dev->stream[0].is_line_wake_up = false; + } else if (priv->hdr_cfg.hdr_mode == HDR_X2) { + rkcif_free_rx_buf(&cif_dev->stream[1], cif_dev->stream[1].rx_buf_num); + cif_dev->stream[0].is_line_wake_up = false; + cif_dev->stream[1].is_line_wake_up = false; + } else if (priv->hdr_cfg.hdr_mode == HDR_X3) { + rkcif_free_rx_buf(&cif_dev->stream[2], cif_dev->stream[2].rx_buf_num); + cif_dev->stream[0].is_line_wake_up = false; + cif_dev->stream[1].is_line_wake_up = false; + cif_dev->stream[2].is_line_wake_up = false; + } + cif_dev->wait_line_cache = 0; + cif_dev->wait_line = 0; + cif_dev->wait_line_bak = 0; + cif_dev->is_thunderboot = false; } - cif_dev->wait_line_cache = 0; - cif_dev->wait_line = 0; - cif_dev->wait_line_bak = 0; } void sditf_disable_immediately(struct sditf_priv *priv) @@ -857,6 +861,7 @@ static int sditf_s_rx_buffer(struct v4l2_subdev *sd, if (!list_empty(&stream->rx_buf_head) && cif_dev->is_thunderboot && + (!cif_dev->is_rtt_suspend) && (dbufs->type == BUF_SHORT || (dbufs->type != BUF_SHORT && (!dbufs->is_switch)))) { spin_lock_irqsave(&cif_dev->buffree_lock, buffree_flags); diff --git a/drivers/soc/rockchip/fiq_debugger/fiq_debugger.c b/drivers/soc/rockchip/fiq_debugger/fiq_debugger.c index cab5d169ffbc..e4a915ff81e8 100644 --- a/drivers/soc/rockchip/fiq_debugger/fiq_debugger.c +++ b/drivers/soc/rockchip/fiq_debugger/fiq_debugger.c @@ -50,6 +50,7 @@ #endif #include +#include #include "fiq_debugger.h" #include "fiq_debugger_priv.h" @@ -148,10 +149,7 @@ static bool initial_debug_enable; static bool initial_console_enable; #endif -#ifdef CONFIG_FIQ_DEBUGGER_TRUST_ZONE -static struct fiq_debugger_state *state_tf; -#endif - +static struct fiq_debugger_state *g_state; static bool fiq_kgdb_enable; static bool fiq_debugger_disable; @@ -1076,7 +1074,7 @@ static void fiq_debugger_fiq(struct fiq_glue_handler *h, #ifdef CONFIG_FIQ_DEBUGGER_TRUST_ZONE void fiq_debugger_fiq(void *regs, u32 cpu) { - struct fiq_debugger_state *state = state_tf; + struct fiq_debugger_state *state = g_state; bool need_irq; if (!state) @@ -1443,6 +1441,18 @@ static int fiq_debugger_dev_resume(struct device *dev) return 0; } +static int fiq_debugger_cpu_offine_migrate_irq(unsigned int cpu) +{ + if (g_state && cpu == g_state->current_cpu) { + unsigned int new_cpu = cpumask_any_but(cpu_online_mask, cpu); + + if (new_cpu < nr_cpu_ids) + g_state->current_cpu = new_cpu; + } + + return 0; +} + static int fiq_debugger_probe(struct platform_device *pdev) { int ret; @@ -1450,6 +1460,7 @@ static int fiq_debugger_probe(struct platform_device *pdev) struct fiq_debugger_state *state; int fiq; int uart_irq; + enum cpuhp_state cs = -1; if (pdev->id >= MAX_FIQ_DEBUGGER_PORTS) return -EINVAL; @@ -1569,6 +1580,15 @@ static int fiq_debugger_probe(struct platform_device *pdev) * can. */ enable_irq_wake(state->uart_irq); + + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "soc/fiq_debugger", + NULL, + fiq_debugger_cpu_offine_migrate_irq); + if (ret < 0) + pr_err("%s: could not setup cpu offine handler\n", __func__); + else + cs = ret; } if (state->signal_irq >= 0) { @@ -1599,10 +1619,6 @@ static int fiq_debugger_probe(struct platform_device *pdev) if (state->no_sleep) fiq_debugger_handle_wakeup(state); -#ifdef CONFIG_FIQ_DEBUGGER_TRUST_ZONE - state_tf = state; -#endif - if (pdata->uart_init) { ret = pdata->uart_init(pdev); if (ret) @@ -1629,7 +1645,7 @@ console_out: /* switch to cpu0 default */ fiq_debugger_switch_cpu(state, 0); - + g_state = state; return 0; err_register_irq: @@ -1640,6 +1656,8 @@ err_uart_init: clk_disable(state->clk); if (state->clk) clk_put(state->clk); + if (cs >= 0) + cpuhp_remove_state_nocalls(cs); wakeup_source_remove(&state->debugger_wake_src); __pm_relax(&state->debugger_wake_src); platform_set_drvdata(pdev, NULL); diff --git a/drivers/soc/rockchip/minidump/minidump_log.c b/drivers/soc/rockchip/minidump/minidump_log.c index 8c911827de70..18b1934e9356 100644 --- a/drivers/soc/rockchip/minidump/minidump_log.c +++ b/drivers/soc/rockchip/minidump/minidump_log.c @@ -659,20 +659,68 @@ static int md_register_minidump_entry(char *name, u64 virt_addr, return ret; } -static int md_is_kernel_address(u64 addr) +static struct page *md_vmalloc_to_page(const void *vmalloc_addr) +{ + unsigned long addr = (unsigned long) vmalloc_addr; + struct page *page = NULL; + pgd_t *pgd = pgd_offset_k(addr); + p4d_t *p4d; + pud_t *pud; + pmd_t *pmd; + pte_t *ptep, pte; + + if (pgd_none(*pgd)) + return NULL; + p4d = p4d_offset(pgd, addr); + if (p4d_none(*p4d)) + return NULL; + pud = pud_offset(p4d, addr); + + if (pud_none(*pud) || pud_bad(*pud)) + return NULL; + pmd = pmd_offset(pud, addr); + if (pmd_none(*pmd) || pmd_bad(*pmd)) + return NULL; + + ptep = pte_offset_map(pmd, addr); + pte = *ptep; + if (pte_present(pte)) + page = pte_page(pte); + pte_unmap(ptep); + return page; +} + +static bool md_is_kernel_address(u64 addr) { u32 data; + u64 phys_addr = 0; + struct page *page; - if (addr < PAGE_OFFSET || addr > -4096UL) - return 0; + if (!is_ttbr1_addr(addr)) + return false; if (addr >= (u64)_text && addr < (u64)_end) - return 0; + return false; + + if (__is_lm_address(addr)) { + phys_addr = virt_to_phys((void *)addr); + } else if (is_vmalloc_or_module_addr((const void *)addr)) { + page = md_vmalloc_to_page((const void *) addr); + if (page) + phys_addr = page_to_phys(page); + else + return false; + } else { + return false; + } + + if (!md_is_ddr_address(phys_addr)) + return false; if (aarch64_insn_read((void *)addr, &data)) - return 0; + return false; else - return 1; + return true; } static int md_save_page(u64 addr, bool flush) @@ -689,8 +737,8 @@ static int md_save_page(u64 addr, bool flush) if (__is_lm_address(virt_addr)) { phys_addr = virt_to_phys((void *)virt_addr); - } else if (virt_addr >= VMALLOC_START && virt_addr < VMALLOC_END) { - page = vmalloc_to_page((const void *) virt_addr); + } else if (is_vmalloc_or_module_addr((const void *)virt_addr)) { + page = md_vmalloc_to_page((const void *) virt_addr); phys_addr = page_to_phys(page); } else { return -1; diff --git a/drivers/soc/rockchip/minidump/minidump_memory.c b/drivers/soc/rockchip/minidump/minidump_memory.c index 95fc78aa1e69..d7f93e2f12b6 100644 --- a/drivers/soc/rockchip/minidump/minidump_memory.c +++ b/drivers/soc/rockchip/minidump/minidump_memory.c @@ -933,7 +933,7 @@ static ssize_t slab_owner_dump_size_read(struct file *file, char __user *ubuf, { char buf[100]; - snprintf(buf, sizeof(buf), "%llu MB\n", md_slabowner_dump_size/SZ_1M); + snprintf(buf, sizeof(buf), "%lu MB\n", md_slabowner_dump_size/SZ_1M); return simple_read_from_buffer(ubuf, count, offset, buf, strlen(buf)); } diff --git a/drivers/soc/rockchip/minidump/rk_minidump.c b/drivers/soc/rockchip/minidump/rk_minidump.c index 0f90fce431e2..d742b7e2eda6 100644 --- a/drivers/soc/rockchip/minidump/rk_minidump.c +++ b/drivers/soc/rockchip/minidump/rk_minidump.c @@ -72,6 +72,8 @@ static bool md_init_done; static void __iomem *md_elf_mem; static resource_size_t md_elf_size; static struct proc_dir_entry *proc_rk_minidump; +static bool md_is_ddr_address_default(u64 phys_addr); +bool (*md_is_ddr_address)(u64 virt_addr) = md_is_ddr_address_default; /* Number of pending entries to be added in ToC regions */ static unsigned int pendings; @@ -621,6 +623,22 @@ static const struct proc_ops rk_minidump_proc_ops = { .proc_read = rk_minidump_read_elf, }; +static bool md_is_ddr_address_rk3588(u64 phys_addr) +{ + /* peripheral address space */ + if (phys_addr >= 0xf0000000 && phys_addr < 0x100000000) + return false; + /* DDR is up to 32GB */ + if (phys_addr > 0x800000000) + return false; + return true; +} + +static bool md_is_ddr_address_default(u64 phys_addr) +{ + return true; +} + static int rk_minidump_driver_probe(struct platform_device *pdev) { unsigned int i; @@ -689,6 +707,9 @@ static int rk_minidump_driver_probe(struct platform_device *pdev) pr_info("Create /proc/rk_md/minidump fail...\n"); } + if (of_machine_is_compatible("rockchip,rk3588")) + md_is_ddr_address = md_is_ddr_address_rk3588; + /* Check global minidump support initialization */ if (!md_global_toc->md_toc_init) { pr_err("System Minidump TOC not initialized\n"); diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 571d34c08603..6548dd38b534 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -5,6 +5,7 @@ source "drivers/video/rockchip/rga3/Kconfig" source "drivers/video/rockchip/rve/Kconfig" source "drivers/video/rockchip/iep/Kconfig" source "drivers/video/rockchip/mpp/Kconfig" +source "drivers/video/rockchip/mpp_osal/Kconfig" source "drivers/video/rockchip/dvbm/Kconfig" source "drivers/video/rockchip/vehicle/Kconfig" source "drivers/video/rockchip/vtunnel/Kconfig" diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index b13d93a1cd6f..867ac56fe5b7 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_ROCKCHIP_MULTI_RGA) += rga3/ obj-$(CONFIG_ROCKCHIP_RVE) += rve/ obj-$(CONFIG_IEP) += iep/ obj-$(CONFIG_ROCKCHIP_MPP_SERVICE) += mpp/ +obj-$(CONFIG_ROCKCHIP_MPP_OSAL) += mpp_osal/ obj-$(CONFIG_ROCKCHIP_DVBM) += dvbm/ obj-$(CONFIG_VIDEO_REVERSE_IMAGE) += vehicle/ obj-$(CONFIG_ROCKCHIP_VIDEO_TUNNEL) += vtunnel/ diff --git a/drivers/video/rockchip/mpp_osal/Kconfig b/drivers/video/rockchip/mpp_osal/Kconfig new file mode 100644 index 000000000000..75cd7028615f --- /dev/null +++ b/drivers/video/rockchip/mpp_osal/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +config ROCKCHIP_MPP_OSAL + bool "mpp osal" + depends on CPU_RV1106 + default y + help + rockchip mpp osal adapt for kmpp diff --git a/drivers/video/rockchip/mpp_osal/Makefile b/drivers/video/rockchip/mpp_osal/Makefile new file mode 100644 index 000000000000..f4ca9643fff2 --- /dev/null +++ b/drivers/video/rockchip/mpp_osal/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +obj-$(CONFIG_ROCKCHIP_MPP_OSAL) += mpp_osal.o diff --git a/drivers/video/rockchip/mpp_osal/mpp_osal.c b/drivers/video/rockchip/mpp_osal/mpp_osal.c new file mode 100644 index 000000000000..a778b1904044 --- /dev/null +++ b/drivers/video/rockchip/mpp_osal/mpp_osal.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd + * + */ +#include "mpp_osal.h" + +struct device_node *mpp_dev_of_node(struct device *dev) +{ + return dev_of_node(dev); +} +EXPORT_SYMBOL(mpp_dev_of_node); + +void mpp_pm_relax(struct device *dev) +{ + return pm_relax(dev); +} +EXPORT_SYMBOL(mpp_pm_relax); + +void mpp_pm_stay_awake(struct device *dev) +{ + return pm_stay_awake(dev); +} +EXPORT_SYMBOL(mpp_pm_stay_awake); + +int mpp_device_init_wakeup(struct device *dev, bool enable) +{ + return device_init_wakeup(dev, enable); +} +EXPORT_SYMBOL(mpp_device_init_wakeup); diff --git a/drivers/video/rockchip/mpp_osal/mpp_osal.h b/drivers/video/rockchip/mpp_osal/mpp_osal.h new file mode 100644 index 000000000000..d798dfd0c293 --- /dev/null +++ b/drivers/video/rockchip/mpp_osal/mpp_osal.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd + * + */ + +#ifndef __ROCKCHIP_MPP_OSAL_H__ +#define __ROCKCHIP_MPP_OSAL_H__ + +#include +#include + +struct device_node *mpp_dev_of_node(struct device *dev); +void mpp_pm_relax(struct device *dev); +void mpp_pm_stay_awake(struct device *dev); +int mpp_device_init_wakeup(struct device *dev, bool enable); + +#endif diff --git a/include/soc/rockchip/rk_minidump.h b/include/soc/rockchip/rk_minidump.h index d025a9a35bbc..c9e9efd2222b 100644 --- a/include/soc/rockchip/rk_minidump.h +++ b/include/soc/rockchip/rk_minidump.h @@ -71,4 +71,5 @@ static inline int rk_minidump_hardlock_notify(struct notifier_block *nb, #endif void rk_md_flush_dcache_area(void *addr, size_t len); +extern bool (*md_is_ddr_address)(u64 virt_addr); #endif /* __RK_MINIDUMP_H */ diff --git a/include/uapi/linux/rk-isp2-config.h b/include/uapi/linux/rk-isp2-config.h index 28f0803bf1ad..8d1db6506600 100644 --- a/include/uapi/linux/rk-isp2-config.h +++ b/include/uapi/linux/rk-isp2-config.h @@ -1994,6 +1994,8 @@ struct rkisp_thunderboot_resmem_head { __u32 exp_time_reg[3]; __u32 exp_gain_reg[3]; __u32 exp_isp_dgain[3]; + __u32 nr_buf_size; + __u32 share_mem_size; } __attribute__ ((packed)); /**