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drm/rockchip: dw_hdmi: Fix phy pll rate overflow when frl 48G mode

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Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Id2612aaedb887f518d9d7458c2b33e3b969af51e
This commit is contained in:
Algea Cao
2023-04-25 16:28:53 +08:00
parent 006505ca76
commit 86f4cace86
1 changed files with 5 additions and 5 deletions
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10
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -2468,7 +2468,7 @@ static int dw_hdmi_dclk_set(void *data, bool enable, int vp_id)
static int dw_hdmi_link_clk_set(void *data, bool enable)
{
struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
u32 phy_clk;
u64 phy_clk = hdmi->phy_bus_width;
int ret;
if (enable) {
@@ -2478,11 +2478,11 @@ static int dw_hdmi_link_clk_set(void *data, bool enable)
return ret;
}
if (((hdmi->phy_bus_width & DATA_RATE_MASK) <= 6000000) &&
(hdmi->phy_bus_width & COLOR_DEPTH_10BIT))
phy_clk = (hdmi->phy_bus_width & DATA_RATE_MASK) * 100 * 8 / 10;
if (((phy_clk & DATA_RATE_MASK) <= 6000000) &&
(phy_clk & COLOR_DEPTH_10BIT))
phy_clk = (phy_clk & DATA_RATE_MASK) * 10 * 8;
else
phy_clk = (hdmi->phy_bus_width & DATA_RATE_MASK) * 100;
phy_clk = (phy_clk & DATA_RATE_MASK) * 100;
/*
* To be compatible with vop dclk usage scenarios, hdmi phy pll clk